diff --git a/src/chipset/CMakeLists.txt b/src/chipset/CMakeLists.txt
index cc7498ddc..fc06eb1f8 100644
--- a/src/chipset/CMakeLists.txt
+++ b/src/chipset/CMakeLists.txt
@@ -16,7 +16,7 @@
 add_library(chipset OBJECT acc2168.c cs8230.c ali1217.c ali1429.c ali1489.c headland.c
 	intel_82335.c cs4031.c intel_420ex.c intel_4x0.c intel_sio.c intel_piix.c ../ioapic.c
 	neat.c opti283.c opti291.c opti495.c opti822.c opti895.c opti5x7.c scamp.c scat.c
-	sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c sis_5598.c
+	sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c sis_5511.c sis_5571.c sis_5598.c
 	umc_8886.c umc_8890.c umc_hb4.c
 	via_vt82c49x.c via_vt82c505.c sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c
 	gc100.c olivetti_eva.c stpc.c 
diff --git a/src/chipset/sis_5511.c b/src/chipset/sis_5511.c
new file mode 100644
index 000000000..e9a566d44
--- /dev/null
+++ b/src/chipset/sis_5511.c
@@ -0,0 +1,727 @@
+/*
+ * 86Box	A hypervisor and IBM PC system emulator that specializes in
+ *		running old operating systems and software designed for IBM
+ *		PC systems and compatibles from 1981 through fairly recent
+ *		system designs based on the PCI bus.
+ *
+ *		This file is part of the 86Box distribution.
+ *
+ *		Implementation of the SiS 5511/5512/5513 Pentium PCI/ISA Chipset.
+ *
+ *
+ *
+ * Authors:	Tiseno100,
+ *
+ *		Copyright 2021 Tiseno100.
+ */
+
+#include <stdarg.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <wchar.h>
+#define HAVE_STDARG_H
+#include <86box/86box.h>
+#include <86box/device.h>
+#include <86box/io.h>
+#include <86box/timer.h>
+
+#include <86box/mem.h>
+#include <86box/hdd.h>
+#include <86box/hdc.h>
+#include <86box/hdc_ide.h>
+#include <86box/hdc_ide_sff8038i.h>
+#include <86box/pci.h>
+#include <86box/port_92.h>
+#include <86box/smram.h>
+
+#include <86box/chipset.h>
+
+/* IDE Flags (1 Native / 0 Compatibility)*/
+#define PRIMARY_COMP_NAT_SWITCH (dev->pci_conf_sb[1][9] & 1)
+#define SECONDARY_COMP_NAT_SWITCH (dev->pci_conf_sb[1][9] & 4)
+#define PRIMARY_NATIVE_BASE (dev->pci_conf_sb[1][0x11] << 8) | (dev->pci_conf_sb[1][0x10] & 0xf8)
+#define PRIMARY_NATIVE_SIDE (((dev->pci_conf_sb[1][0x15] << 8) | (dev->pci_conf_sb[1][0x14] & 0xfc)) + 2)
+#define SECONDARY_NATIVE_BASE (dev->pci_conf_sb[1][0x19] << 8) | (dev->pci_conf_sb[1][0x18] & 0xf8)
+#define SECONDARY_NATIVE_SIDE (((dev->pci_conf_sb[1][0x1d] << 8) | (dev->pci_conf_sb[1][0x1c] & 0xfc)) + 2)
+#define BUS_MASTER_BASE ((dev->pci_conf_sb[1][0x20] & 0xf0) | (dev->pci_conf_sb[1][0x21] << 8))
+
+#ifdef ENABLE_SIS_5511_LOG
+int sis_5511_do_log = ENABLE_SIS_5511_LOG;
+static void
+sis_5511_log(const char *fmt, ...)
+{
+	va_list ap;
+
+	if (sis_5511_do_log)
+	{
+		va_start(ap, fmt);
+		pclog_ex(fmt, ap);
+		va_end(ap);
+	}
+}
+#else
+#define sis_5511_log(fmt, ...)
+#endif
+
+typedef struct sis_5511_t
+{
+	uint8_t pci_conf[256], pci_conf_sb[2][256],
+		index, regs[16];
+
+	int nb_pci_slot, sb_pci_slot;
+
+	sff8038i_t *ide_drive[2];
+	smram_t *smram;
+	port_92_t *port_92;
+
+} sis_5511_t;
+
+static void
+sis_5511_shadow_recalc(int cur_reg, sis_5511_t *dev)
+{
+	if (cur_reg == 0x86)
+		mem_set_mem_state_both(0xf0000, 0x10000, ((dev->pci_conf[cur_reg] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->pci_conf[cur_reg] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
+	else
+	{
+		mem_set_mem_state_both(0xc0000 + ((cur_reg & 7) << 15), 0x4000, ((dev->pci_conf[cur_reg] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->pci_conf[cur_reg] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
+		mem_set_mem_state_both(0xc4000 + ((cur_reg & 7) << 15), 0x4000, ((dev->pci_conf[cur_reg] & 8) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->pci_conf[cur_reg] & 2) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
+	}
+
+	flushmmucache_nopc();
+}
+
+static void
+sis_5511_smram_recalc(sis_5511_t *dev)
+{
+	smram_disable_all();
+
+		switch (dev->pci_conf[0x65] >> 6)
+		{
+		case 0:
+			smram_enable(dev->smram, 0x000e0000, 0x000e0000, 0x8000, dev->pci_conf[0x65] & 0x10, 1);
+			break;
+		case 1:
+			smram_enable(dev->smram, 0x000e0000, 0x000a0000, 0x8000, dev->pci_conf[0x65] & 0x10, 1);
+			break;
+		case 2:
+			smram_enable(dev->smram, 0x000e0000, 0x000b0000, 0x8000, dev->pci_conf[0x65] & 0x10, 1);
+			break;
+		}
+
+	flushmmucache();
+}
+
+void sis_5513_ide_handler(sis_5511_t *dev)
+{
+	ide_pri_disable();
+	ide_sec_disable();
+	if (dev->pci_conf_sb[1][4] & 1)
+	{
+		if (dev->pci_conf_sb[1][0x4a] & 4)
+		{
+			ide_set_base(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_BASE : 0x1f0);
+			ide_set_side(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_SIDE : 0x3f6);
+			ide_pri_enable();
+		}
+		if (dev->pci_conf_sb[1][0x4a] & 2)
+		{
+			ide_set_base(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_BASE : 0x170);
+			ide_set_side(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_SIDE : 0x376);
+			ide_sec_enable();
+		}
+	}
+}
+
+void sis_5513_bm_handler(sis_5511_t *dev)
+{
+	sff_bus_master_handler(dev->ide_drive[0], dev->pci_conf_sb[1][4] & 4, BUS_MASTER_BASE);
+	sff_bus_master_handler(dev->ide_drive[1], dev->pci_conf_sb[1][4] & 4, BUS_MASTER_BASE + 8);
+}
+
+static void
+sis_5511_write(int func, int addr, uint8_t val, void *priv)
+{
+	sis_5511_t *dev = (sis_5511_t *)priv;
+
+	switch (addr)
+	{
+	case 0x04: /* Command - low  byte */
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x05: /* Command - high  byte */
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x06: /* Status - Low Byte */
+		dev->pci_conf[addr] &= val;
+		break;
+
+	case 0x07: /* Status - High Byte */
+		dev->pci_conf[addr] &= 0x16;
+		break;
+
+	case 0x50:
+		dev->pci_conf[addr] = (val & 0xf9) | 4;
+		cpu_cache_ext_enabled = !!(val & 0x40);
+		cpu_update_waitstates();
+		break;
+
+	case 0x51:
+		dev->pci_conf[addr] = val & 0xfe;
+		break;
+
+	case 0x52:
+		dev->pci_conf[addr] = val & 0x3f;
+		break;
+
+	case 0x53:
+	case 0x54:
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x55:
+		dev->pci_conf[addr] = val & 0xf8;
+		break;
+
+	case 0x57:
+	case 0x58:
+	case 0x59:
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x5a:
+		dev->pci_conf[addr] = val;
+		port_92_set_features(dev->port_92, !!(val & 0x40), !!(val & 0x80));
+		break;
+
+	case 0x5b:
+		dev->pci_conf[addr] = val & 0xf7;
+		break;
+
+	case 0x5c:
+		dev->pci_conf[addr] = val & 0xcf;
+		break;
+
+	case 0x5d:
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x5e:
+		dev->pci_conf[addr] = val & 0xfe;
+		break;
+
+	case 0x5f:
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x60:
+		dev->pci_conf[addr] = val & 0x3e;
+		if (!!(val & 2) && (dev->pci_conf[0x68] & 1))
+		{
+			smi_line = 1;
+			dev->pci_conf[0x69] |= 1;
+		}
+		break;
+
+	case 0x61: /* STPCLK# Assertion Timer */
+	case 0x62: /* STPCLK# De-assertion Timer */
+	case 0x63: /* System Standby Timer */
+	case 0x64:
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x65:
+		dev->pci_conf[addr] = val & 0xd0;
+		sis_5511_smram_recalc(dev);
+		break;
+
+	case 0x66:
+		dev->pci_conf[addr] = val & 0x7f;
+		break;
+
+	case 0x67:
+	case 0x68:
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x69:
+		dev->pci_conf[addr] &= val;
+		break;
+
+	case 0x6a:
+	case 0x6b:
+	case 0x6c:
+	case 0x6d:
+	case 0x6e:
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x6f:
+		dev->pci_conf[addr] = val & 0x3f;
+		break;
+
+	case 0x70: /* DRAM Bank Register 0-0 */
+	case 0x71: /* DRAM Bank Register 0-0 */
+	case 0x72: /* DRAM Bank Register 0-1 */
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x73: /* DRAM Bank Register 0-1 */
+		dev->pci_conf[addr] = val & 0x83;
+		break;
+
+	case 0x74: /* DRAM Bank Register 1-0 */
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x75: /* DRAM Bank Register 1-0 */
+		dev->pci_conf[addr] = val & 0x7f;
+		break;
+
+	case 0x76: /* DRAM Bank Register 1-1 */
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x77: /* DRAM Bank Register 1-1 */
+		dev->pci_conf[addr] = val & 0x83;
+		break;
+
+	case 0x78: /* DRAM Bank Register 2-0 */
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x79: /* DRAM Bank Register 2-0 */
+		dev->pci_conf[addr] = val & 0x7f;
+		break;
+
+	case 0x7a: /* DRAM Bank Register 2-1 */
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x7b: /* DRAM Bank Register 2-1 */
+		dev->pci_conf[addr] = val & 0x83;
+		break;
+
+	case 0x7c: /* DRAM Bank Register 3-0 */
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x7d: /* DRAM Bank Register 3-0 */
+		dev->pci_conf[addr] = val & 0x7f;
+		break;
+
+	case 0x7e: /* DRAM Bank Register 3-1 */
+		dev->pci_conf[addr] = val;
+		break;
+
+	case 0x7f: /* DRAM Bank Register 3-1 */
+		dev->pci_conf[addr] = val & 0x83;
+		break;
+
+	case 0x80:
+	case 0x81:
+	case 0x82:
+	case 0x83:
+	case 0x84:
+	case 0x85:
+	case 0x86:
+		dev->pci_conf[addr] = val & ((addr == 0x86) ? 0xe8 : 0xee);
+		sis_5511_shadow_recalc(addr, dev);
+		sis_5511_smram_recalc(dev);
+		break;
+
+	case 0x90: /* 5512 General Purpose Register Index */
+	case 0x91: /* 5512 General Purpose Register Index */
+	case 0x92: /* 5512 General Purpose Register Index */
+	case 0x93: /* 5512 General Purpose Register Index */
+		dev->pci_conf[addr] = val;
+		break;
+	}
+	sis_5511_log("SiS 5511: dev->pci_conf[%02x] = %02x POST: %02x\n", addr, dev->pci_conf[addr], inb(0x80));
+}
+
+static uint8_t
+sis_5511_read(int func, int addr, void *priv)
+{
+	sis_5511_t *dev = (sis_5511_t *)priv;
+	sis_5511_log("SiS 5511: dev->pci_conf[%02x] (%02x) POST %02x\n", addr, dev->pci_conf[addr], inb(0x80));
+	return dev->pci_conf[addr];
+}
+
+void sis_5513_pci_to_isa_write(int addr, uint8_t val, sis_5511_t *dev)
+{
+	switch (addr)
+	{
+	case 0x04: /* Command */
+		dev->pci_conf_sb[0][addr] = val & 7;
+		break;
+
+	case 0x07: /* Status */
+		dev->pci_conf_sb[0][addr] &= val & 0x36;
+		break;
+
+	case 0x40: /* BIOS Control Register */
+		dev->pci_conf_sb[0][addr] = val & 0x3f;
+		break;
+
+	case 0x41: /* INTA# Remapping Control Register */
+	case 0x42: /* INTB# Remapping Control Register */
+	case 0x43: /* INTC# Remapping Control Register */
+	case 0x44: /* INTD# Remapping Control Register */
+		dev->pci_conf_sb[0][addr] = val & 0x8f;
+		pci_set_irq_routing(addr & 7, (val & 0x80) ? (val & 0x80) : PCI_IRQ_DISABLED);
+		break;
+
+	case 0x48: /* ISA Master/DMA Memory Cycle Control Register 1 */
+	case 0x49: /* ISA Master/DMA Memory Cycle Control Register 2 */
+	case 0x4a: /* ISA Master/DMA Memory Cycle Control Register 3 */
+	case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */
+	case 0x4c:
+	case 0x4d:
+	case 0x4e:
+	case 0x4f:
+	case 0x50:
+	case 0x51:
+	case 0x52:
+	case 0x53:
+	case 0x54:
+	case 0x55:
+	case 0x56:
+	case 0x57:
+	case 0x58:
+	case 0x59:
+	case 0x5a:
+	case 0x5b:
+	case 0x5c:
+	case 0x5d:
+	case 0x5e:
+	case 0x5f:
+		dev->pci_conf_sb[0][addr] = val;
+		break;
+
+	case 0x60: /* MIRQ0 Remapping Control Register */
+	case 0x61: /* MIRQ1 Remapping Control Register */
+		dev->pci_conf_sb[0][addr] = val & 0xcf;
+		pci_set_mirq_routing(addr & 1, (val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED);
+		break;
+
+	case 0x62: /* On-board Device DMA Control Register */
+		dev->pci_conf_sb[0][addr] = val;
+		break;
+
+	case 0x63: /* IDEIRQ Remapping Control Register */
+		dev->pci_conf_sb[0][addr] = val & 0x8f;
+		if (val & 0x80)
+		{
+			sff_set_irq_line(dev->ide_drive[0], (val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED);
+			sff_set_irq_line(dev->ide_drive[1], (val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED);
+		}
+		break;
+
+	case 0x64: /* GPIO0 Control Register */
+		dev->pci_conf_sb[0][addr] = val & 0xef;
+		break;
+
+	case 0x65:
+		dev->pci_conf_sb[0][addr] = val & 0x80;
+		break;
+
+	case 0x66: /* GPIO0 Output Mode Control Register */
+	case 0x67: /* GPIO0 Output Mode Control Register */
+		dev->pci_conf_sb[0][addr] = val;
+		break;
+
+	case 0x6a: /* GPIO Status Register */
+		dev->pci_conf_sb[0][addr] &= val & 0x15;
+		break;
+	}
+}
+
+void sis_5513_ide_write(int addr, uint8_t val, sis_5511_t *dev)
+{
+	switch (addr)
+	{
+	case 0x04: /* Command low byte */
+		dev->pci_conf_sb[1][addr] = val & 5;
+		sis_5513_ide_handler(dev);
+		sis_5513_bm_handler(dev);
+		break;
+	case 0x07: /* Status high byte */
+		dev->pci_conf_sb[1][addr] &= val & 0x3f;
+		break;
+	case 0x09: /* Programming Interface Byte */
+		dev->pci_conf_sb[1][addr] = val;
+		sis_5513_ide_handler(dev);
+		break;
+	case 0x0d: /* Latency Timer */
+		dev->pci_conf_sb[1][addr] = val;
+		break;
+
+	case 0x10: /* Primary Channel Base Address Register */
+	case 0x11: /* Primary Channel Base Address Register */
+	case 0x12: /* Primary Channel Base Address Register */
+	case 0x13: /* Primary Channel Base Address Register */
+	case 0x14: /* Primary Channel Base Address Register */
+	case 0x15: /* Primary Channel Base Address Register */
+	case 0x16: /* Primary Channel Base Address Register */
+	case 0x17: /* Primary Channel Base Address Register */
+	case 0x18: /* Secondary Channel Base Address Register */
+	case 0x19: /* Secondary Channel Base Address Register */
+	case 0x1a: /* Secondary Channel Base Address Register */
+	case 0x1b: /* Secondary Channel Base Address Register */
+	case 0x1c: /* Secondary Channel Base Address Register */
+	case 0x1d: /* Secondary Channel Base Address Register */
+	case 0x1e: /* Secondary Channel Base Address Register */
+	case 0x1f: /* Secondary Channel Base Address Register */
+		dev->pci_conf_sb[1][addr] = val;
+		sis_5513_ide_handler(dev);
+		break;
+
+	case 0x20: /* Bus Master IDE Control Register Base Address */
+	case 0x21: /* Bus Master IDE Control Register Base Address */
+	case 0x22: /* Bus Master IDE Control Register Base Address */
+	case 0x23: /* Bus Master IDE Control Register Base Address */
+		dev->pci_conf_sb[1][addr] = val;
+		sis_5513_bm_handler(dev);
+		break;
+
+	case 0x30: /* Expansion ROM Base Address */
+	case 0x31: /* Expansion ROM Base Address */
+	case 0x32: /* Expansion ROM Base Address */
+	case 0x33: /* Expansion ROM Base Address */
+		dev->pci_conf_sb[1][addr] = val;
+		break;
+
+	case 0x40: /* IDE Primary Channel/Master Drive Data Recovery Time Control */
+	case 0x41: /* IDE Primary Channel/Master Drive DataActive Time Control */
+	case 0x42: /* IDE Primary Channel/Slave Drive Data Recovery Time Control */
+	case 0x43: /* IDE Primary Channel/Slave Drive Data Active Time Control */
+	case 0x44: /* IDE Secondary Channel/Master Drive Data Recovery Time Control */
+	case 0x45: /* IDE Secondary Channel/Master Drive Data Active Time Control */
+	case 0x46: /* IDE Secondary Channel/Slave Drive Data Recovery Time Control */
+	case 0x47: /* IDE Secondary Channel/Slave Drive Data Active Time Control */
+	case 0x48: /* IDE Command Recovery Time Control */
+	case 0x49: /* IDE Command Active Time Control */
+		dev->pci_conf_sb[1][addr] = val;
+		break;
+
+	case 0x4a: /* IDE General Control Register 0 */
+		dev->pci_conf_sb[1][addr] = val & 0x9f;
+		sis_5513_ide_handler(dev);
+		break;
+
+	case 0x4b: /* IDE General Control Register 1 */
+		dev->pci_conf_sb[1][addr] = val & 0xef;
+		break;
+
+	case 0x4c: /* Prefetch Count of Primary Channel (Low Byte) */
+	case 0x4d: /* Prefetch Count of Primary Channel (High Byte) */
+	case 0x4e: /* Prefetch Count of Secondary Channel (Low Byte) */
+	case 0x4f: /* Prefetch Count of Secondary Channel (High Byte) */
+		dev->pci_conf_sb[1][addr] = val;
+		break;
+	}
+}
+
+static void
+sis_5513_write(int func, int addr, uint8_t val, void *priv)
+{
+	sis_5511_t *dev = (sis_5511_t *)priv;
+	switch (func)
+	{
+	case 0:
+		sis_5513_pci_to_isa_write(addr, val, dev);
+		break;
+	case 1:
+		sis_5513_ide_write(addr, val, dev);
+		break;
+	}
+	sis_5511_log("SiS 5513: dev->pci_conf[%02x][%02x] = %02x POST: %02x\n", func, addr, dev->pci_conf_sb[func][addr], inb(0x80));
+}
+
+static uint8_t
+sis_5513_read(int func, int addr, void *priv)
+{
+	sis_5511_t *dev = (sis_5511_t *)priv;
+
+	sis_5511_log("SiS 5513: dev->pci_conf[%02x][%02x] = %02x POST %02x\n", func, addr, dev->pci_conf_sb[func][addr], inb(0x80));
+	if ((func >= 0) && (func <= 1))
+		return dev->pci_conf_sb[func][addr];
+	else
+		return 0xff;
+}
+
+static void
+sis_5513_isa_write(uint16_t addr, uint8_t val, void *priv)
+{
+	sis_5511_t *dev = (sis_5511_t *)priv;
+
+	switch (addr)
+	{
+	case 0x22:
+		dev->index = val - 0x50;
+		break;
+	case 0x23:
+		switch (dev->index)
+		{
+		case 0x00:
+			dev->regs[dev->index] = val & 0xed;
+			switch (val >> 6)
+			{
+			case 0:
+				cpu_set_isa_speed(7.159);
+				break;
+			case 1:
+				cpu_set_isa_pci_div(4);
+				break;
+			case 2:
+				cpu_set_isa_pci_div(3);
+				break;
+			}
+			break;
+		case 0x01:
+			dev->regs[dev->index] = val & 0xf4;
+			break;
+		case 0x03:
+			dev->regs[dev->index] = val & 3;
+			break;
+		case 0x04: /* BIOS Register */
+			dev->regs[dev->index] = val;
+			break;
+		case 0x05:
+			dev->regs[dev->index] = inb(0x70);
+			break;
+		case 0x08:
+		case 0x09:
+		case 0x0a:
+		case 0x0b:
+			dev->regs[dev->index] = val;
+			break;
+		}
+		sis_5511_log("SiS 5513-ISA: dev->regs[%02x] = %02x POST: %02x\n", dev->index + 0x50, dev->regs[dev->index], inb(0x80));
+		break;
+	}
+}
+
+static uint8_t
+sis_5513_isa_read(uint16_t addr, void *priv)
+{
+	sis_5511_t *dev = (sis_5511_t *)priv;
+
+	if (addr == 0x23)
+	{
+		sis_5511_log("SiS 5513-ISA: dev->regs[%02x] (%02x) POST: %02x\n", dev->index + 0x50, dev->regs[dev->index], inb(0x80));
+		return dev->regs[dev->index];
+	}
+	else
+		return 0xff;
+}
+
+static void
+sis_5511_reset(void *priv)
+{
+	sis_5511_t *dev = (sis_5511_t *)priv;
+
+	/* SiS 5511 */
+	dev->pci_conf[0x00] = 0x39;
+	dev->pci_conf[0x01] = 0x10;
+	dev->pci_conf[0x02] = 0x11;
+	dev->pci_conf[0x03] = 0x55;
+	dev->pci_conf[0x04] = 7;
+	dev->pci_conf[0x07] = 2;
+	dev->pci_conf[0x0b] = 6;
+	dev->pci_conf[0x52] = 0x20;
+	dev->pci_conf[0x61] = 0xff;
+	dev->pci_conf[0x62] = 0xff;
+	dev->pci_conf[0x63] = 0xff;
+	dev->pci_conf[0x67] = 0xff;
+	dev->pci_conf[0x6b] = 0xff;
+	dev->pci_conf[0x6c] = 0xff;
+	dev->pci_conf[0x70] = 4;
+	dev->pci_conf[0x72] = 4;
+	dev->pci_conf[0x73] = 0x80;
+	dev->pci_conf[0x74] = 4;
+	dev->pci_conf[0x76] = 4;
+	dev->pci_conf[0x77] = 0x80;
+	dev->pci_conf[0x78] = 4;
+	dev->pci_conf[0x7a] = 4;
+	dev->pci_conf[0x7b] = 0x80;
+	dev->pci_conf[0x7c] = 4;
+	dev->pci_conf[0x7e] = 4;
+	dev->pci_conf[0x7f] = 0x80;
+
+	/* SiS 5513 */
+	dev->pci_conf_sb[0][0x00] = 0x39;
+	dev->pci_conf_sb[0][0x01] = 0x10;
+	dev->pci_conf_sb[0][0x02] = 8;
+	dev->pci_conf_sb[0][0x04] = 7;
+	dev->pci_conf_sb[0][0x0a] = 1;
+	dev->pci_conf_sb[0][0x0b] = 6;
+	dev->pci_conf_sb[0][0x0e] = 0x80;
+
+	/* SiS 5513 IDE Controller */
+	dev->pci_conf_sb[1][0x00] = 0x39;
+	dev->pci_conf_sb[1][0x01] = 0x10;
+	dev->pci_conf_sb[1][0x02] = 0x13;
+	dev->pci_conf_sb[1][0x03] = 0x55;
+	dev->pci_conf_sb[1][0x0a] = 1;
+	dev->pci_conf_sb[1][0x0b] = 1;
+	dev->pci_conf_sb[1][0x0e] = 0x80;
+	sff_set_slot(dev->ide_drive[0], dev->sb_pci_slot);
+	sff_set_slot(dev->ide_drive[1], dev->sb_pci_slot);
+    sff_bus_master_reset(dev->ide_drive[0], BUS_MASTER_BASE);
+    sff_bus_master_reset(dev->ide_drive[1], BUS_MASTER_BASE + 8);
+}
+
+static void
+sis_5511_close(void *priv)
+{
+	sis_5511_t *dev = (sis_5511_t *)priv;
+
+	smram_del(dev->smram);
+	free(dev);
+}
+
+static void *
+sis_5511_init(const device_t *info)
+{
+	sis_5511_t *dev = (sis_5511_t *)malloc(sizeof(sis_5511_t));
+	memset(dev, 0, sizeof(sis_5511_t));
+
+	dev->nb_pci_slot = pci_add_card(PCI_ADD_NORTHBRIDGE, sis_5511_read, sis_5511_write, dev);		   /* Device 0: SiS 5511 */
+	dev->sb_pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_5513_read, sis_5513_write, dev);		   /* Device 1: SiS 5513 */
+	io_sethandler(0x0022, 0x0002, sis_5513_isa_read, NULL, NULL, sis_5513_isa_write, NULL, NULL, dev); /* Ports 22h-23h: SiS 5513 ISA */
+
+	/* MIRQ */
+	pci_enable_mirq(0);
+	pci_enable_mirq(1);
+
+	/* Port 92h */
+	dev->port_92 = device_add(&port_92_device);
+
+	/* SFF IDE */
+	dev->ide_drive[0] = device_add_inst(&sff8038i_device, 1);
+	dev->ide_drive[1] = device_add_inst(&sff8038i_device, 2);
+
+	/* SMRAM */
+	dev->smram = smram_add();
+
+	sis_5511_reset(dev);
+
+	return dev;
+}
+
+const device_t sis_5511_device = {
+	"SiS 5511",
+	DEVICE_PCI,
+	0,
+	sis_5511_init,
+	sis_5511_close,
+	sis_5511_reset,
+	{NULL},
+	NULL,
+	NULL,
+	NULL};
diff --git a/src/chipset/sis_5571.c b/src/chipset/sis_5571.c
index cea1ec970..93f3911a8 100644
--- a/src/chipset/sis_5571.c
+++ b/src/chipset/sis_5571.c
@@ -25,7 +25,6 @@
 #include <86box/io.h>
 #include <86box/timer.h>
 
-#include <86box/apm.h>
 #include <86box/dma.h>
 #include <86box/mem.h>
 #include <86box/pci.h>
@@ -45,11 +44,13 @@
 #define SYSTEM_READ ((dev->pci_conf[0x76] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY)
 #define SYSTEM_WRITE ((dev->pci_conf[0x76] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)
 
-/* IDE Controller */
-#define PRI_BASE ((dev->pci_conf_sb[1][0x13]) | (dev->pci_conf_sb[1][0x12] << 4) | (dev->pci_conf_sb[1][0x11] << 8) | (dev->pci_conf_sb[1][0x10] << 12))
-#define PRI_SIDE ((dev->pci_conf_sb[1][0x17]) | (dev->pci_conf_sb[1][0x16] << 4) | (dev->pci_conf_sb[1][0x15] << 8) | (dev->pci_conf_sb[1][0x14] << 12))
-#define SEC_BASE ((dev->pci_conf_sb[1][0x1b]) | (dev->pci_conf_sb[1][0x1a] << 4) | (dev->pci_conf_sb[1][0x19] << 8) | (dev->pci_conf_sb[1][0x18] << 12))
-#define SEC_SIDE ((dev->pci_conf_sb[1][0x1f]) | (dev->pci_conf_sb[1][0x1e] << 4) | (dev->pci_conf_sb[1][0x1d] << 8) | (dev->pci_conf_sb[1][0x1c] << 12))
+/* IDE Flags (1 Native / 0 Compatibility)*/
+#define PRIMARY_COMP_NAT_SWITCH (dev->pci_conf_sb[1][9] & 1)
+#define SECONDARY_COMP_NAT_SWITCH (dev->pci_conf_sb[1][9] & 4)
+#define PRIMARY_NATIVE_BASE (dev->pci_conf_sb[1][0x11] << 8) | (dev->pci_conf_sb[1][0x10] & 0xf8)
+#define PRIMARY_NATIVE_SIDE (((dev->pci_conf_sb[1][0x15] << 8) | (dev->pci_conf_sb[1][0x14] & 0xfc)) + 2)
+#define SECONDARY_NATIVE_BASE (dev->pci_conf_sb[1][0x19] << 8) | (dev->pci_conf_sb[1][0x18] & 0xf8)
+#define SECONDARY_NATIVE_SIDE (((dev->pci_conf_sb[1][0x1d] << 8) | (dev->pci_conf_sb[1][0x1c] & 0xfc)) + 2)
 #define BUS_MASTER_BASE ((dev->pci_conf_sb[1][0x20] & 0xf0) | (dev->pci_conf_sb[1][0x21] << 8))
 
 #ifdef ENABLE_SIS_5571_LOG
@@ -72,15 +73,12 @@ sis_5571_log(const char *fmt, ...)
 
 typedef struct sis_5571_t
 {
-	uint8_t pci_conf[256], pci_conf_sb[3][256],
-		sb_pci_slot;
+	uint8_t pci_conf[256], pci_conf_sb[3][256];
 
-	int old_smi_value;
+	int nb_pci_slot, sb_pci_slot;
 
-	apm_t *apm;
 	port_92_t *port_92;
-	sff8038i_t *bm[2];
-	uint32_t program_status_pri, program_status_sec;
+	sff8038i_t *ide_drive[2];
 	smram_t *smram;
 	usb_t *usb;
 
@@ -108,16 +106,13 @@ sis_5571_smm_recalc(sis_5571_t *dev)
 	switch ((dev->pci_conf[0xa3] & 0xc0) >> 6)
 	{
 	case 0x00:
-		if (dev->pci_conf[0x74] == 0)
-			smram_enable(dev->smram, 0xe0000, 0xe0000, 0x8000, (dev->pci_conf[0xa3] & 0x10), 1);
+		smram_enable(dev->smram, 0xe0000, 0xe0000, 0x8000, (dev->pci_conf[0xa3] & 0x10), 1);
 		break;
 	case 0x01:
-		if (dev->pci_conf[0x74] == 0)
-			smram_enable(dev->smram, 0xe0000, 0xa0000, 0x8000, (dev->pci_conf[0xa3] & 0x10), 1);
+		smram_enable(dev->smram, 0xe0000, 0xa0000, 0x8000, (dev->pci_conf[0xa3] & 0x10), 1);
 		break;
 	case 0x02:
-		if (dev->pci_conf[0x74] == 0)
-			smram_enable(dev->smram, 0xe0000, 0xb0000, 0x8000, (dev->pci_conf[0xa3] & 0x10), 1);
+		smram_enable(dev->smram, 0xe0000, 0xb0000, 0x8000, (dev->pci_conf[0xa3] & 0x10), 1);
 		break;
 	case 0x03:
 		smram_enable(dev->smram, 0xa0000, 0xa0000, 0x10000, (dev->pci_conf[0xa3] & 0x10), 1);
@@ -127,57 +122,31 @@ sis_5571_smm_recalc(sis_5571_t *dev)
 	flushmmucache();
 }
 
-static void
-sis_5571_ide_handler(void *priv)
+void sis_5571_ide_handler(sis_5571_t *dev)
 {
-	sis_5571_t *dev = (sis_5571_t *)priv;
-
-	/* IDE IRQ remap */
-	if (!(dev->pci_conf_sb[0][0x63] & 0x80))
-	{
-		sff_set_irq_line(dev->bm[0], dev->pci_conf_sb[0][0x63] & 0x0f);
-		sff_set_irq_line(dev->bm[1], dev->pci_conf_sb[0][0x63] & 0x0f);
-	}
-
-	/* Compatibility(0)/Native(1) Mode Status Programming */
-	if (dev->pci_conf_sb[1][0x08])
-		dev->program_status_sec = dev->pci_conf_sb[1][0x09] & 0x04;
-
-	if (dev->pci_conf_sb[1][0x02])
-		dev->program_status_pri = dev->pci_conf_sb[1][0x09] & 0x01;
-
-	/* Setting Base/Side */
-	ide_set_base(0, dev->program_status_pri ? PRI_BASE : 0x1f0);
-	ide_set_side(0, dev->program_status_pri ? PRI_SIDE : 0x3f6);
-
-	ide_set_base(1, dev->program_status_sec ? SEC_BASE : 0x170);
-	ide_set_side(1, dev->program_status_sec ? SEC_SIDE : 0x376);
-
-	/* Enable/Disable(Default is Enabled) */
 	ide_pri_disable();
 	ide_sec_disable();
-
-	if (dev->pci_conf_sb[1][0x4a] & 0x02)
-		ide_pri_enable();
-
-	if (dev->pci_conf_sb[1][0x4a] & 0x04)
-		ide_sec_enable();
-
-	/* Bus Mastering */
-	sff_bus_master_handler(dev->bm[0], dev->pci_conf_sb[1][0x09] & 0x80, BUS_MASTER_BASE);
-	sff_bus_master_handler(dev->bm[1], dev->pci_conf_sb[1][0x09] & 0x80, BUS_MASTER_BASE + 8);
+	if (dev->pci_conf_sb[1][4] & 1)
+	{
+		if (dev->pci_conf_sb[1][0x4a] & 4)
+		{
+			ide_set_base(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_BASE : 0x1f0);
+			ide_set_side(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_SIDE : 0x3f6);
+			ide_pri_enable();
+		}
+		if (dev->pci_conf_sb[1][0x4a] & 2)
+		{
+			ide_set_base(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_BASE : 0x170);
+			ide_set_side(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_SIDE : 0x376);
+			ide_sec_enable();
+		}
+	}
 }
 
-static void
-sis_5571_usb_handler(void *priv)
+void sis_5571_bm_handler(sis_5571_t *dev)
 {
-	sis_5571_t *dev = (sis_5571_t *)priv;
-
-	/* USB Memory Base */
-	ohci_update_mem_mapping(dev->usb, dev->pci_conf_sb[2][0x11], dev->pci_conf_sb[2][0x12], dev->pci_conf_sb[2][0x13], dev->pci_conf_sb[0][0x68] & 0x40);
-
-	/* USB I/O Base*/
-	uhci_update_io_mapping(dev->usb, dev->pci_conf_sb[2][0x14], dev->pci_conf_sb[2][0x17], dev->pci_conf_sb[0][0x68] & 0x40);
+	sff_bus_master_handler(dev->ide_drive[0], dev->pci_conf_sb[1][4] & 4, BUS_MASTER_BASE);
+	sff_bus_master_handler(dev->ide_drive[1], dev->pci_conf_sb[1][4] & 4, BUS_MASTER_BASE + 8);
 }
 
 static void
@@ -193,11 +162,11 @@ memory_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
 		break;
 
 	case 0x06: /* Status - Low Byte */
-		dev->pci_conf[addr] = val;
+		dev->pci_conf[addr] &= val;
 		break;
 
 	case 0x07: /* Status - High Byte */
-		dev->pci_conf[addr] = val & 0xbe;
+		dev->pci_conf[addr] &= val & 0xbe;
 		break;
 
 	case 0x0d: /* Master latency timer */
@@ -339,7 +308,13 @@ memory_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
 	case 0x9a:
 	case 0x9b:
 	case 0x9c:
+		dev->pci_conf[addr] = val;
+		break;
+
 	case 0x9d:
+		dev->pci_conf[addr] &= val;
+		break;
+
 	case 0x9e: /* STPCLK# Assertion Timer */
 	case 0x9f: /* STPCLK# De-assertion Timer */
 	case 0xa0:
@@ -378,7 +353,7 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
 			break;
 
 		case 0x06: /* Status */
-			dev->pci_conf_sb[0][addr] = val;
+			dev->pci_conf_sb[0][addr] &= val;
 			break;
 
 		case 0x40: /* BIOS Control Register */
@@ -466,7 +441,11 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
 
 		case 0x63: /* IDEIRQ Remapping Control Register */
 			dev->pci_conf_sb[0][addr] = val & 0x8f;
-			sis_5571_ide_handler(dev);
+			if (val & 0x80)
+			{
+				sff_set_irq_line(dev->ide_drive[0], val & 0x0f);
+				sff_set_irq_line(dev->ide_drive[1], val & 0x0f);
+			}
 			break;
 
 		case 0x64: /* GPIO Control Register */
@@ -482,9 +461,8 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
 			dev->pci_conf_sb[0][addr] = val;
 			break;
 
-		case 0x68: /* USBIRQ Remapping Control Registe */
+		case 0x68: /* USBIRQ Remapping Control Register */
 			dev->pci_conf_sb[0][addr] = val & 0x1b;
-			sis_5571_usb_handler(dev);
 			break;
 
 		case 0x69:
@@ -536,14 +514,17 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
 		{
 		case 0x04: /* Command low byte */
 			dev->pci_conf_sb[1][addr] = val & 0x05;
+			sis_5571_ide_handler(dev);
+			sis_5571_bm_handler(dev);
 			break;
 
 		case 0x07: /* Status high byte */
-			dev->pci_conf_sb[1][addr] = val;
+			dev->pci_conf_sb[1][addr] &= val;
 			break;
 
 		case 0x09: /* Programming Interface Byte */
 			dev->pci_conf_sb[1][addr] = val & 0xcf;
+			sis_5571_ide_handler(dev);
 			break;
 
 		case 0x0d: /* Latency Time */
@@ -563,10 +544,18 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
 		case 0x1d: /* Secondary Channel Base Address Register */
 		case 0x1e: /* Secondary Channel Base Address Register */
 		case 0x1f: /* Secondary Channel Base Address Register */
+			dev->pci_conf_sb[1][addr] = val;
+			sis_5571_ide_handler(dev);
+			break;
+
 		case 0x20: /* Bus Master IDE Control Register Base Address */
 		case 0x21: /* Bus Master IDE Control Register Base Address */
 		case 0x22: /* Bus Master IDE Control Register Base Address */
 		case 0x23: /* Bus Master IDE Control Register Base Address */
+			dev->pci_conf_sb[1][addr] = val;
+			sis_5571_bm_handler(dev);
+			break;
+
 		case 0x30: /* Expansion ROM Base Address */
 		case 0x31: /* Expansion ROM Base Address */
 		case 0x32: /* Expansion ROM Base Address */
@@ -586,6 +575,7 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
 
 		case 0x4a: /* IDE General Control Register 0 */
 			dev->pci_conf_sb[1][addr] = val & 0xaf;
+			sis_5571_ide_handler(dev);
 			break;
 
 		case 0x4b: /* IDE General Control register 1 */
@@ -597,29 +587,36 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
 			break;
 		}
 		sis_5571_log("SiS5571-IDE: dev->pci_conf[%02x] = %02x\n", addr, val);
-
-		if (((addr >= 0x09) && (addr <= 0x23)) || (addr == 0x4a))
-			sis_5571_ide_handler(dev);
 		break;
 
 	case 2: /* USB Controller */
 		switch (addr)
 		{
 		case 0x04: /* Command - Low Byte */
-			dev->pci_conf_sb[2][addr] |= val;
+			dev->pci_conf_sb[2][addr] = val;
+			ohci_update_mem_mapping(dev->usb, dev->pci_conf_sb[2][0x11], dev->pci_conf_sb[2][0x12], dev->pci_conf_sb[2][0x13], dev->pci_conf_sb[2][4] & 1);
+			break;
+
 		case 0x05: /* Command - High Byte */
-			dev->pci_conf_sb[2][addr] |= val & 0x03;
+			dev->pci_conf_sb[2][addr] = val & 0x03;
 			break;
 
 		case 0x06: /* Status - Low Byte */
-			dev->pci_conf_sb[2][addr] = val & 0xc0;
+			dev->pci_conf_sb[2][addr] &= val & 0xc0;
 			break;
 
 		case 0x07: /* Status - High Byte */
+			dev->pci_conf_sb[2][addr] &= val;
+			break;
+
 		case 0x10: /* Memory Space Base Address Register */
 		case 0x11: /* Memory Space Base Address Register */
 		case 0x12: /* Memory Space Base Address Register */
 		case 0x13: /* Memory Space Base Address Register */
+			dev->pci_conf_sb[2][addr] = val & ((addr == 0x11) ? 0x0f : 0xff);
+			ohci_update_mem_mapping(dev->usb, dev->pci_conf_sb[2][0x11], dev->pci_conf_sb[2][0x12], dev->pci_conf_sb[2][0x13], dev->pci_conf_sb[2][4] & 1);
+			break;
+
 		case 0x14: /* IO Space Base Address Register */
 		case 0x15: /* IO Space Base Address Register */
 		case 0x16: /* IO Space Base Address Register */
@@ -629,10 +626,6 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
 			break;
 		}
 		sis_5571_log("SiS5571-USB: dev->pci_conf[%02x] = %02x\n", addr, val);
-
-		if ((addr >= 0x11) && (addr <= 0x17))
-			sis_5571_usb_handler(dev);
-		break;
 	}
 }
 
@@ -668,97 +661,47 @@ sis_5571_reset(void *priv)
 	dev->pci_conf[0x02] = 0x71;
 	dev->pci_conf[0x03] = 0x55;
 	dev->pci_conf[0x04] = 0xfd;
-	dev->pci_conf[0x05] = 0x00;
-	dev->pci_conf[0x06] = 0x00;
-	dev->pci_conf[0x07] = 0x00;
-	dev->pci_conf[0x08] = 0x00;
-	dev->pci_conf[0x09] = 0x00;
-	dev->pci_conf[0x0a] = 0x00;
 	dev->pci_conf[0x0b] = 0x06;
-	dev->pci_conf[0x0c] = 0x00;
-	dev->pci_conf[0x0d] = 0x00;
-	dev->pci_conf[0x0e] = 0x00;
-	dev->pci_conf[0x0f] = 0x00;
-
-	memory_pci_bridge_write(0, 0x51, 0x00, dev);
 	dev->pci_conf[0x9e] = 0xff;
 	dev->pci_conf[0x9f] = 0xff;
 	dev->pci_conf[0xa2] = 0xff;
-	memory_pci_bridge_write(0, 0xa3, 0x00, dev);
 
 	/* PCI to ISA bridge */
 	dev->pci_conf_sb[0][0x00] = 0x39;
 	dev->pci_conf_sb[0][0x01] = 0x10;
 	dev->pci_conf_sb[0][0x02] = 0x08;
-	dev->pci_conf_sb[0][0x03] = 0x00;
 	dev->pci_conf_sb[0][0x04] = 0xfd;
-	dev->pci_conf_sb[0][0x05] = 0x00;
-	dev->pci_conf_sb[0][0x06] = 0x00;
-	dev->pci_conf_sb[0][0x07] = 0x00;
 	dev->pci_conf_sb[0][0x08] = 0x01;
-	dev->pci_conf_sb[0][0x09] = 0x00;
 	dev->pci_conf_sb[0][0x0a] = 0x01;
 	dev->pci_conf_sb[0][0x0b] = 0x06;
-	dev->pci_conf_sb[0][0x0c] = 0x00;
-	dev->pci_conf_sb[0][0x0d] = 0x00;
-	dev->pci_conf_sb[0][0x0e] = 0x00;
-	dev->pci_conf_sb[0][0x0f] = 0x00;
-
-	pci_isa_bridge_write(0, 0x41, 0x80, dev);
-	pci_isa_bridge_write(0, 0x42, 0x80, dev);
-	pci_isa_bridge_write(0, 0x43, 0x80, dev);
-	pci_isa_bridge_write(0, 0x44, 0x80, dev);
-	pci_isa_bridge_write(0, 0x61, 0x80, dev);
-	pci_isa_bridge_write(0, 0x62, 0x80, dev);
-	dev->pci_conf_sb[0][0x63] = 0x80;
 
 	/* IDE Controller */
 	dev->pci_conf_sb[1][0x00] = 0x39;
 	dev->pci_conf_sb[1][0x01] = 0x10;
 	dev->pci_conf_sb[1][0x02] = 0x13;
 	dev->pci_conf_sb[1][0x03] = 0x55;
-	dev->pci_conf_sb[1][0x04] = 0x00;
-	dev->pci_conf_sb[1][0x05] = 0x00;
-	dev->pci_conf_sb[1][0x06] = 0x00;
-	dev->pci_conf_sb[1][0x07] = 0x00;
 	dev->pci_conf_sb[1][0x08] = 0xc0;
-	dev->pci_conf_sb[1][0x09] = 0x00;
 	dev->pci_conf_sb[1][0x0a] = 0x01;
 	dev->pci_conf_sb[1][0x0b] = 0x01;
-	dev->pci_conf_sb[1][0x0c] = 0x00;
-	dev->pci_conf_sb[1][0x0d] = 0x00;
 	dev->pci_conf_sb[1][0x0e] = 0x80;
-	dev->pci_conf_sb[1][0x0f] = 0x00;
 	dev->pci_conf_sb[1][0x4a] = 0x06;
-
-	sff_set_slot(dev->bm[0], dev->sb_pci_slot);
-	sff_set_slot(dev->bm[1], dev->sb_pci_slot);
-	sff_bus_master_reset(dev->bm[0], BUS_MASTER_BASE);
-	sff_bus_master_reset(dev->bm[1], BUS_MASTER_BASE + 8);
-
-	sis_5571_ide_handler(dev);
+	sff_set_slot(dev->ide_drive[0], dev->sb_pci_slot);
+	sff_set_slot(dev->ide_drive[1], dev->sb_pci_slot);
+	sff_bus_master_reset(dev->ide_drive[0], BUS_MASTER_BASE);
+	sff_bus_master_reset(dev->ide_drive[1], BUS_MASTER_BASE + 8);
 
 	/* USB Controller */
 	dev->pci_conf_sb[2][0x00] = 0x39;
 	dev->pci_conf_sb[2][0x01] = 0x10;
 	dev->pci_conf_sb[2][0x02] = 0x01;
 	dev->pci_conf_sb[2][0x03] = 0x70;
-	dev->pci_conf_sb[2][0x04] = 0x00;
-	dev->pci_conf_sb[2][0x05] = 0x00;
-	dev->pci_conf_sb[2][0x06] = 0x00;
-	dev->pci_conf_sb[2][0x07] = 0x00;
 	dev->pci_conf_sb[2][0x08] = 0xb0;
 	dev->pci_conf_sb[2][0x09] = 0x10;
 	dev->pci_conf_sb[2][0x0a] = 0x03;
 	dev->pci_conf_sb[2][0x0b] = 0xc0;
-	dev->pci_conf_sb[2][0x0c] = 0x00;
-	dev->pci_conf_sb[2][0x0d] = 0x00;
 	dev->pci_conf_sb[2][0x0e] = 0x80;
-	dev->pci_conf_sb[2][0x0f] = 0x00;
 	dev->pci_conf_sb[2][0x14] = 0x01;
 	dev->pci_conf_sb[2][0x3d] = 0x01;
-
-	sis_5571_usb_handler(dev);
 }
 
 static void
@@ -776,15 +719,9 @@ sis_5571_init(const device_t *info)
 	sis_5571_t *dev = (sis_5571_t *)malloc(sizeof(sis_5571_t));
 	memset(dev, 0x00, sizeof(sis_5571_t));
 
-	pci_add_card(PCI_ADD_NORTHBRIDGE, memory_pci_bridge_read, memory_pci_bridge_write, dev);
+	dev->nb_pci_slot = pci_add_card(PCI_ADD_NORTHBRIDGE, memory_pci_bridge_read, memory_pci_bridge_write, dev);
 	dev->sb_pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, pci_isa_bridge_read, pci_isa_bridge_write, dev);
 
-	/* APM */
-	dev->apm = device_add(&apm_pci_device);
-
-	/* DMA */
-	dma_alias_set();
-
 	/* MIRQ */
 	pci_enable_mirq(0);
 
@@ -793,10 +730,8 @@ sis_5571_init(const device_t *info)
 	dev->smram = smram_add();
 
 	/* SFF IDE */
-	dev->bm[0] = device_add_inst(&sff8038i_device, 1);
-	dev->bm[1] = device_add_inst(&sff8038i_device, 2);
-	dev->program_status_pri = 0;
-	dev->program_status_sec = 0;
+	dev->ide_drive[0] = device_add_inst(&sff8038i_device, 1);
+	dev->ide_drive[1] = device_add_inst(&sff8038i_device, 2);
 
 	/* USB */
 	dev->usb = device_add(&usb_device);
diff --git a/src/chipset/sis_5598.c b/src/chipset/sis_5598.c
index 15fc44d89..fd9455bb6 100644
--- a/src/chipset/sis_5598.c
+++ b/src/chipset/sis_5598.c
@@ -99,104 +99,104 @@ void sis_5598_dimm_programming(sis_5598_t *dev)
 Based completely off the PC Chips M571 Manual
 Configurations are forced and don't work as intended
 */
-switch(mem_size >> 10)
-{
-case 8:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 0xc0;
-break;
-case 16:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 0xc0;
-DIMM_BANK1 = 0xc0;
-break;
-case 24:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 0xc2;
-DIMM_BANK1 = 0xc0;
-break;
-case 32:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 0xc2;
-DIMM_BANK1 = 0xc2;
-break;
-case 40:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 0xc8;
-DIMM_BANK1 = 0xc0;
-break;
-case 48:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 0xc8;
-DIMM_BANK1 = 0xc2;
-break;
-case 56: /* Unintended */
-case 64:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 0xc8;
-DIMM_BANK1 = 0xc8;
-break;
-case 72:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 0xc6;
-DIMM_BANK1 = 0xc0;
-break;
-case 80:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 0xc6;
-DIMM_BANK1 = 0xc2;
-break;
-case 88: /* Unintended */
-case 96:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 0xc6;
-DIMM_BANK1 = 0xc8;
-break;
-case 104: /* Unintended */
-case 112: /* Unintended */
-case 120: /* Unintended */
-case 128:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 0xc6;
-DIMM_BANK1 = 0xc6;
-break;
-case 136:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 10 | 0xca;
-DIMM_BANK1 = 0xc0;
-break;
-case 144:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 10 | 0xca;
-DIMM_BANK1 = 2 | 0xc2;
-break;
-case 152: /* Unintended */
-case 160:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 10 | 0xca;
-DIMM_BANK1 = 8 | 0xc8;
-break;
-case 168: /* Unintended */
-case 176: /* Unintended */
-case 184: /* Unintended */
-case 192:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 10 | 0xca;
-DIMM_BANK1 = 6 | 0xc6;
-break;
-case 200: /* Unintended */
-case 208: /* Unintended */
-case 216: /* Unintended */
-case 224: /* Unintended */
-case 232: /* Unintended */
-case 240: /* Unintended */
-case 248: /* Unintended */
-case 256:
-DIMM_BANK_ENABLE = 1;
-DIMM_BANK0 = 10 | 0xca;
-DIMM_BANK1 = 10 | 0xca;
-break;
-}
+    switch (mem_size >> 10)
+    {
+    case 8:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 0xc0;
+        break;
+    case 16:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 0xc0;
+        DIMM_BANK1 = 0xc0;
+        break;
+    case 24:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 0xc2;
+        DIMM_BANK1 = 0xc0;
+        break;
+    case 32:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 0xc2;
+        DIMM_BANK1 = 0xc2;
+        break;
+    case 40:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 0xc8;
+        DIMM_BANK1 = 0xc0;
+        break;
+    case 48:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 0xc8;
+        DIMM_BANK1 = 0xc2;
+        break;
+    case 56: /* Unintended */
+    case 64:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 0xc8;
+        DIMM_BANK1 = 0xc8;
+        break;
+    case 72:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 0xc6;
+        DIMM_BANK1 = 0xc0;
+        break;
+    case 80:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 0xc6;
+        DIMM_BANK1 = 0xc2;
+        break;
+    case 88: /* Unintended */
+    case 96:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 0xc6;
+        DIMM_BANK1 = 0xc8;
+        break;
+    case 104: /* Unintended */
+    case 112: /* Unintended */
+    case 120: /* Unintended */
+    case 128:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 0xc6;
+        DIMM_BANK1 = 0xc6;
+        break;
+    case 136:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 10 | 0xca;
+        DIMM_BANK1 = 0xc0;
+        break;
+    case 144:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 10 | 0xca;
+        DIMM_BANK1 = 2 | 0xc2;
+        break;
+    case 152: /* Unintended */
+    case 160:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 10 | 0xca;
+        DIMM_BANK1 = 8 | 0xc8;
+        break;
+    case 168: /* Unintended */
+    case 176: /* Unintended */
+    case 184: /* Unintended */
+    case 192:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 10 | 0xca;
+        DIMM_BANK1 = 6 | 0xc6;
+        break;
+    case 200: /* Unintended */
+    case 208: /* Unintended */
+    case 216: /* Unintended */
+    case 224: /* Unintended */
+    case 232: /* Unintended */
+    case 240: /* Unintended */
+    case 248: /* Unintended */
+    case 256:
+        DIMM_BANK_ENABLE = 1;
+        DIMM_BANK0 = 10 | 0xca;
+        DIMM_BANK1 = 10 | 0xca;
+        break;
+    }
 }
 
 void sis_5598_shadow(int cur_reg, sis_5598_t *dev)
@@ -236,7 +236,7 @@ void sis_5598_smram(sis_5598_t *dev)
         break;
     }
 
-    flushmmucache_nopc();
+    flushmmucache();
 }
 
 void sis_5598_ddma_update(sis_5598_t *dev)
@@ -248,18 +248,18 @@ void sis_5598_ddma_update(sis_5598_t *dev)
 
 void sis_5598_ide_handler(sis_5598_t *dev)
 {
+    ide_pri_disable();
+    ide_sec_disable();
     if (dev->pci_conf_sb[1][4] & 1)
     {
         if (dev->pci_conf_sb[1][0x4a] & 4)
         {
-            ide_pri_disable();
             ide_set_base(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_BASE : 0x1f0);
             ide_set_side(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_SIDE : 0x3f6);
             ide_pri_enable();
         }
         if (dev->pci_conf_sb[1][0x4a] & 2)
         {
-            ide_sec_disable();
             ide_set_base(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_BASE : 0x170);
             ide_set_side(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_SIDE : 0x376);
             ide_sec_enable();
diff --git a/src/include/86box/chipset.h b/src/include/86box/chipset.h
index 2daee66a2..9d8414abb 100644
--- a/src/include/86box/chipset.h
+++ b/src/include/86box/chipset.h
@@ -109,9 +109,8 @@ extern const device_t	sis_85c471_device;
 extern const device_t	sis_85c496_device;
 extern const device_t	sis_85c496_ls486e_device;
 extern const device_t	sis_85c50x_device;
-#if defined(DEV_BRANCH) && defined(USE_SIS_5571)
+extern const device_t	sis_5511_device;
 extern const device_t	sis_5571_device;
-#endif
 extern const device_t	sis_5598_device;
 
 /* ST */
diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h
index 9830f6a91..804cc3e4a 100644
--- a/src/include/86box/machine.h
+++ b/src/include/86box/machine.h
@@ -422,6 +422,8 @@ extern const device_t	*at_thor_get_device(void);
 #endif
 
 /* m_at_socket7_s7.c */
+extern int	machine_at_ap5s_init(const machine_t *);
+
 extern int	machine_at_chariot_init(const machine_t *);
 extern int	machine_at_mr586_init(const machine_t *);
 extern int	machine_at_thor_init(const machine_t *);
@@ -462,10 +464,9 @@ extern int	machine_at_an430tx_init(const machine_t *);
 extern int	machine_at_mb540n_init(const machine_t *);
 extern int	machine_at_p5mms98_init(const machine_t *);
 
-#if defined(DEV_BRANCH) && defined(USE_SIS_5571)
 extern int	machine_at_r534f_init(const machine_t *);
 extern int	machine_at_ms5146_init(const machine_t *);
-#endif
+
 #if defined(DEV_BRANCH) && defined(USE_M154X)
 extern int	machine_at_m560_init(const machine_t *);
 extern int	machine_at_ms5164_init(const machine_t *);
diff --git a/src/machine/m_at_socket7.c b/src/machine/m_at_socket7.c
index 03e6ee84d..5ba8a69a3 100644
--- a/src/machine/m_at_socket7.c
+++ b/src/machine/m_at_socket7.c
@@ -45,6 +45,35 @@
 #include <86box/fdc.h>
 #include <86box/nvr.h>
 
+int
+machine_at_ap5s_init(const machine_t *model)
+{
+    int ret;
+
+    ret = bios_load_linear("roms/machines/ap5s/AP5S150.BIN",
+			   0x000e0000, 131072, 0);
+
+    if (bios_only || !ret)
+	return ret;
+
+    machine_at_common_init(model);
+
+    pci_init(PCI_CONFIG_TYPE_1);
+    pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
+    pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
+    pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
+    pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
+    pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 4, 2, 1);
+    pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 3, 2, 1);
+	
+    device_add(&sis_5511_device);
+    device_add(&keyboard_ps2_ami_pci_device);
+    device_add(&fdc37c665_device);
+    device_add(&sst_flash_29ee010_device);
+
+    return ret;
+}
+
 int
 machine_at_chariot_init(const machine_t *model)
 {
@@ -1163,7 +1192,6 @@ machine_at_ms5164_init(const machine_t *model)
 }
 #endif
 
-#if defined(DEV_BRANCH) && defined(USE_SIS_5571)
 int
 machine_at_r534f_init(const machine_t *model)
 {
@@ -1189,7 +1217,6 @@ machine_at_r534f_init(const machine_t *model)
     device_add(&keyboard_ps2_ami_pci_device);
     device_add(&w83877f_device);
     device_add(&sst_flash_29ee010_device);
-    spd_register(SPD_TYPE_SDRAM, 0x3, 128);
 
     return ret;
 }
@@ -1218,11 +1245,10 @@ machine_at_ms5146_init(const machine_t *model)
     device_add(&sis_5571_device);
     device_add(&keyboard_ps2_ami_pci_device);
     device_add(&w83877f_device);
-    device_add(&intel_flash_bxt_device);
+    device_add(&sst_flash_29ee010_device);
 
     return ret;
 }
-#endif
 
 int
 machine_at_ficva502_init(const machine_t *model)
@@ -1298,7 +1324,7 @@ machine_at_sp97xv_init(const machine_t *model)
     if (bios_only || !ret)
 	return ret;
 
-    machine_at_common_init(model);
+    machine_at_common_init_ex(model, 2);
 
     pci_init(PCI_CONFIG_TYPE_1);
     pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
@@ -1322,7 +1348,7 @@ machine_at_m571_init(const machine_t *model)
     if (bios_only || !ret)
 	return ret;
 
-    machine_at_common_init(model);
+    machine_at_common_init_ex(model, 2);
 
     pci_init(PCI_CONFIG_TYPE_1);
     pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c
index 3eb7c5f7f..b8390528a 100644
--- a/src/machine/machine_table.c
+++ b/src/machine/machine_table.c
@@ -318,6 +318,9 @@ const machine_t machines[] = {
     /* 430VX */
     { "[i430VX] Gateway 2000 Tigereye",		"gw2kte",		MACHINE_TYPE_SOCKET7_3V,	CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0,							MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL,		 		 8192, 131072, 8192, 127,	       machine_at_gw2kte_init, NULL			},
 
+    /* SiS 5511 */
+    { "[SiS 5511] AOpen AP5S",		"ap5s",		MACHINE_TYPE_SOCKET7_3V,	CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0,							MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL,		 		 8192, 524288, 8192, 127,	       machine_at_ap5s_init, NULL			},
+
     /* Socket 7 (Dual Voltage) machines */
     /* 430HX */
     { "[i430HX] Acer V35N",			"acerv35n",		MACHINE_TYPE_SOCKET7,		CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_Cx6x86MX), 50000000, 66666667, 2800, 3520, 1.5, 3.0,				MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL,				 8192, 196608, 8192, 127,	     machine_at_acerv35n_init, NULL			},
@@ -357,10 +360,8 @@ const machine_t machines[] = {
     { "[VIA VP3] FIC PA-2012",			"ficpa2012",		MACHINE_TYPE_SOCKET7,		CPU_PKG_SOCKET5_7, 0, 55000000, 75000000, 2100, 3520, 1.5, 5.5,							MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL,		 		 8192,1048576, 8192, 127,	    machine_at_ficpa2012_init, NULL			},
 
     /* SiS 5571 */
-#if defined(DEV_BRANCH) && defined(USE_SIS_5571)
     { "[SiS 5571] Rise R534F",			"r534f",		MACHINE_TYPE_SOCKET7,		CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0,							MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL,		  		 8192, 393216, 8192, 127,		machine_at_r534f_init, NULL			},
-    { "[SiS 5571] MSI MS-5146",			"ms5146",		MACHINE_TYPE_SOCKET7,		CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0,							MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL,		  		 8192, 393216, 8192, 127,	       machine_at_ms5146_init, NULL			},
-#endif
+    { "[SiS 5571] MSI MS-5146",			"ms5146",		MACHINE_TYPE_SOCKET7,		CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0,							MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL,		  		 8192, 262144, 8192, 127,	       machine_at_ms5146_init, NULL			},
 
     /* SiS 5598 */
     { "[SiS 5598] ASUS SP97-XV",		"sp97xv",		MACHINE_TYPE_SOCKET7,		CPU_PKG_SOCKET5_7, 0, 60000000, 66666667, 2100, 3200, 1.5, 2.5,							MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL,				 8192, 262144, 8192, 255,	     machine_at_sp97xv_init, NULL			},
diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw
index 04b35caaa..4546f4af4 100644
--- a/src/win/Makefile.mingw
+++ b/src/win/Makefile.mingw
@@ -87,9 +87,6 @@ ifeq ($(DEV_BUILD), y)
  ifndef M6117
   M6117		:= y
  endif
- ifndef SIS_5571
-  SIS_5571	:= y
- endif
  ifndef VGAWONDER
   VGAWONDER	:= y
  endif
@@ -166,9 +163,6 @@ else
  ifndef M6117
   M6117		:= n
  endif
- ifndef SIS_5571
-  SIS_5571	:= n
- endif
  ifndef VGAWONDER
   VGAWONDER	:= n
  endif
@@ -577,11 +571,6 @@ OPTS		+= -DUSE_M6117
 DEVBROBJ	+= ali6117.o
 endif
 
-ifeq ($(SIS_5571), y)
-OPTS		+= -DUSE_SIS_5571
-DEVBROBJ	+= sis_5571.o
-endif
-
 ifeq ($(VGAWONDER), y)
 OPTS		+= -DUSE_VGAWONDER
 endif
@@ -632,7 +621,7 @@ CHIPSETOBJ	:= acc2168.o cs8230.o ali1217.o ali1429.o ali1489.o headland.o intel_
 		    intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \
 		    neat.o opti495.o opti822.o opti895.o opti5x7.o scamp.o scat.o via_vt82c49x.o via_vt82c505.o \
 		    gc100.o olivetti_eva.o \
-		    sis_85c310.o sis_85c4xx.o sis_85c496.o sis_85c50x.o sis_5598.o stpc.o opti283.o opti291.o \
+		    sis_85c310.o sis_85c4xx.o sis_85c496.o sis_85c50x.o sis_5511.o sis_5571.o sis_5598.o stpc.o opti283.o opti291.o \
 		    umc_8886.o umc_8890.o umc_hb4.o \
 		    via_apollo.o via_pipc.o wd76c10.o vl82c480.o