From af96922c3a6f307f2e8bec69360b1e5bf9b77d97 Mon Sep 17 00:00:00 2001 From: dob205 Date: Sat, 4 Sep 2021 15:21:37 +0200 Subject: [PATCH 1/4] Adding new AMD K6 (Model 6) processor variants Adding new 66, 100 and 133 MHz variants of the AMD K6 (Model 6) processors --- src/cpu/cpu_table.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index e40d64400..b29e20ce0 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -15,12 +15,14 @@ * Miran Grca, * Fred N. van Kempen, * RichardG, + * dob205, * * Copyright 2008-2019 Sarah Walker. * Copyright 2016-2019 leilei. * Copyright 2016-2019 Miran Grca. * Copyright 2017-2019 Fred N. van Kempen. * Copyright 2020 RichardG. + * Copyright 2021 dob205. */ #include #include @@ -760,6 +762,9 @@ const cpu_family_t cpu_families[] = { .name = "K6 (Model 6)", .internal_name = "k6_m6", .cpus = (const CPU[]) { + {"66", CPU_K6, fpus_internal, 66666666, 1.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, /* out of spec */ + {"100", CPU_K6, fpus_internal, 100000000, 1.5, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, /* out of spec */ + {"133", CPU_K6, fpus_internal, 133333333, 2.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, /* out of spec */ {"166", CPU_K6, fpus_internal, 166666666, 2.5, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, {"200", CPU_K6, fpus_internal, 200000000, 3.0, 2900, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, {"233", CPU_K6, fpus_internal, 233333333, 3.5, 3200, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, @@ -1513,6 +1518,9 @@ static const cpu_legacy_table_t cpus_K5[] = { }; static const cpu_legacy_table_t cpus_K56[] = { + {"k6_m6", 66666666, 1.0}, + {"k6_m6", 100000000, 1.5}, + {"k6_m6", 133333333, 2.0}, {"k6_m6", 166666666, 2.5}, {"k6_m6", 200000000, 3.0}, {"k6_m6", 233333333, 3.5}, From b9cdf0521fe6d1395e5a84d7452a01ce153625eb Mon Sep 17 00:00:00 2001 From: TC1995 Date: Sun, 5 Sep 2021 23:17:38 +0200 Subject: [PATCH 2/4] Fix 3 for the dword mode for duke3d/lxpic/standard and miro drivers for win3.1 (I swear). Re-added the byte swap bit in pix trans write word mode that was accidentally removed, fixes buttons in pifedit using the 968 in Win3.1. --- src/video/vid_s3.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/src/video/vid_s3.c b/src/video/vid_s3.c index d3fb9c468..bb68540d0 100644 --- a/src/video/vid_s3.c +++ b/src/video/vid_s3.c @@ -507,6 +507,8 @@ s3_accel_out_pixtrans_w(s3_t *s3, uint16_t val) case 0x400: if (svga->crtc[0x53] & 0x08) { if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) { + if ((s3->accel.cmd & 0x1000) && (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))) + val = (val >> 8) | (val << 8); s3_accel_start(32, 1, val | (val << 16), 0, s3); } else s3_accel_start(4, 1, 0xffffffff, val | (val << 16), s3); @@ -1348,16 +1350,16 @@ s3_accel_write_fifo(s3_t *s3, uint32_t addr, uint8_t val) s3_accel_out_fifo(s3, addr & 0xffff, val); } else { if (s3->accel.cmd & 0x100) { - if (!(s3->accel.cmd & 0x600)) { - if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) { - s3_accel_start(8, 1, val, 0, s3); - } else - s3_accel_start(1, 1, 0xffffffff, val, s3); - } else if ((s3->accel.cmd & 0x600) == 0x200) { + if ((s3->accel.cmd & 0x600) == 0x200) { if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) { s3_accel_start(16, 1, val, 0, s3); } else s3_accel_start(2, 1, 0xffffffff, val, s3); + } else { + if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) { + s3_accel_start(8, 1, val, 0, s3); + } else + s3_accel_start(1, 1, 0xffffffff, val, s3); } } } @@ -2711,12 +2713,8 @@ static void s3_recalctimings(svga_t *svga) svga->lowres = !((svga->gdcreg[5] & 0x40) && (svga->crtc[0x3a] & 0x10)); if (((svga->gdcreg[5] & 0x40) && (svga->crtc[0x3a] & 0x10)) || (svga->crtc[0x3a] & 0x10)) { - if (svga->crtc[0x31] & 0x08) { - if (!(svga->crtc[0x17] & 0x40) && (svga->crtc[0x14] & 0x40)) /*Disable dword mode addressing when CRTC14 bit 6 is not enabled, regardless of the S3 dword mode bit.*/ - svga->force_dword_mode = 1; - } else - svga->force_dword_mode = 0; - + if (((svga->crtc[0x17] & 0x60) == 0x20) && (svga->crtc[0x31] & 0x08)) + svga->crtc[0x17] |= 0x40; switch (svga->bpp) { case 8: svga->render = svga_render_8bpp_highres; @@ -2853,12 +2851,8 @@ static void s3_trio64v_recalctimings(svga_t *svga) svga->lowres = !((svga->gdcreg[5] & 0x40) && (svga->crtc[0x3a] & 0x10)); if ((svga->gdcreg[5] & 0x40) && (svga->crtc[0x3a] & 0x10)) { - if (svga->crtc[0x31] & 0x08) { - if (!(svga->crtc[0x17] & 0x40) && (svga->crtc[0x14] & 0x40)) /*Disable dword mode addressing when CRTC14 bit 6 is not enabled, regardless of the S3 dword mode bit.*/ - svga->force_dword_mode = 1; - } else - svga->force_dword_mode = 0; - + if (((svga->crtc[0x17] & 0x60) == 0x20) && (svga->crtc[0x31] & 0x08)) + svga->crtc[0x17] |= 0x40; switch (svga->bpp) { case 8: svga->render = svga_render_8bpp_highres; @@ -4760,7 +4754,7 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, s3_ } } } - + if (cpu_input && (((s3->accel.multifunc[0xa] & 0xc0) != 0x80) || (!(s3->accel.cmd & 2)))) { if ((s3->bpp == 3) && count == 2) { if (s3->accel.dat_count) { From ead818c5bdb66f2b65cef7097f63e5398abc37ff Mon Sep 17 00:00:00 2001 From: OBattler Date: Sun, 5 Sep 2021 23:20:58 +0200 Subject: [PATCH 3/4] Disabled 286/386 prefetch queue timings emulation on 486+, improves performance. --- src/cpu/386_dynarec.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpu/386_dynarec.c b/src/cpu/386_dynarec.c index a030ac915..15c33100d 100644 --- a/src/cpu/386_dynarec.c +++ b/src/cpu/386_dynarec.c @@ -196,6 +196,9 @@ static void prefetch_run(int instr_cycles, int bytes, int modrm, int reads, int { int mem_cycles = reads*cpu_cycles_read + reads_l*cpu_cycles_read_l + writes*cpu_cycles_write + writes_l*cpu_cycles_write_l; + if (is486) + return; + if (instr_cycles < mem_cycles) instr_cycles = mem_cycles; From 4bf3c88a26c29b45b6fe70a96ab4143ebe9fd2cf Mon Sep 17 00:00:00 2001 From: OBattler Date: Sun, 5 Sep 2021 23:59:52 +0200 Subject: [PATCH 4/4] Reverted the peformance "improving" CPU change. --- src/cpu/386_dynarec.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/cpu/386_dynarec.c b/src/cpu/386_dynarec.c index 15c33100d..a030ac915 100644 --- a/src/cpu/386_dynarec.c +++ b/src/cpu/386_dynarec.c @@ -196,9 +196,6 @@ static void prefetch_run(int instr_cycles, int bytes, int modrm, int reads, int { int mem_cycles = reads*cpu_cycles_read + reads_l*cpu_cycles_read_l + writes*cpu_cycles_write + writes_l*cpu_cycles_write_l; - if (is486) - return; - if (instr_cycles < mem_cycles) instr_cycles = mem_cycles;