diff --git a/src/chipset/sis_85c496.c b/src/chipset/sis_85c496.c
index f309e3a36..e06dc54c5 100644
--- a/src/chipset/sis_85c496.c
+++ b/src/chipset/sis_85c496.c
@@ -299,7 +299,7 @@ sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
 
 			smram_disable_all();
 
-			if (val & 0x06) {
+			if (val & 0x02) {
 				host_base = 0x00060000;
 				ram_base = 0x000a0000;
 				size = 0x00010000;
@@ -453,6 +453,12 @@ sis_85c49x_pci_read(int func, int addr, void *priv)
     uint8_t ret = dev->pci_conf[addr];
 
     switch (addr) {
+	case 0xa0:
+		ret &= 0x10;
+		break;
+	case 0xa1:
+		ret = 0x00;
+		break;
 	case 0x82: /*Port 22h Mirror*/
 		ret = dev->cur_reg;
 		break;
@@ -517,6 +523,7 @@ sis_85c496_reset(void *priv)
     sis_85c49x_pci_write(0, 0x58, 0x00, dev);
     sis_85c49x_pci_write(0, 0x59, 0x00, dev);
     sis_85c49x_pci_write(0, 0x5a, 0x00, dev);
+    // sis_85c49x_pci_write(0, 0x5a, 0x06, dev);
 
     for (i = 0; i < 8; i++)
 	sis_85c49x_pci_write(0, 0x48 + i, 0x00, dev);
@@ -589,7 +596,7 @@ static void
 
     pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c49x_pci_read, sis_85c49x_pci_write, dev);
 
-    sis_85c497_isa_reset(dev);
+    // sis_85c497_isa_reset(dev);
 
     dev->port_92 = device_add(&port_92_device);
     port_92_set_period(dev->port_92, 2ULL * TIMER_USEC);
@@ -609,6 +616,8 @@ static void
 
     timer_add(&dev->rmsmiblk_timer, sis_85c496_rmsmiblk_count, dev, 0);
 
+    sis_85c496_reset(dev);
+
     return dev;
 }
 
diff --git a/src/cpu/386_common.c b/src/cpu/386_common.c
index 9324976af..5aa1d4b3c 100644
--- a/src/cpu/386_common.c
+++ b/src/cpu/386_common.c
@@ -1027,7 +1027,7 @@ enter_smm(int in_hlt)
     uint32_t smram_state = smbase + 0x10000;
 
     /* If it's a CPU on which SMM is not supported, do nothing. */
-    if (!is_am486 && !is_pentium && !is_k5 && !is_k6 && !is_p6 && !is_cx6x86)
+    if (!is_am486 && !is_pentium && !is_k5 && !is_k6 && !is_p6 && !is_cxsmm)
 	return;
 
     x386_common_log("enter_smm(): smbase = %08X\n", smbase);
@@ -1066,7 +1066,7 @@ enter_smm(int in_hlt)
     smram_backup_all();
     smram_recalc_all(0);
 
-    if (cpu_iscyrix) {
+    if (is_cxsmm) {
 	if (!(cyrix.smhr & SMHR_VALID))
 		cyrix.smhr = (cyrix.arr[3].base + cyrix.arr[3].size) | SMHR_VALID;
 	smram_state = cyrix.smhr & SMHR_ADDR_MASK;
@@ -1074,11 +1074,11 @@ enter_smm(int in_hlt)
 
     memset(saved_state, 0x00, SMM_SAVE_STATE_MAP_SIZE * sizeof(uint32_t));
 
-    if (cpu_iscyrix)			/* Cx6x86 */
+    if (is_cxsmm)			/* Cx6x86 */
 	smram_save_state_cyrix(saved_state, in_hlt);
-    if (is_pentium || is_am486)		/* Am486 / 5x86 / Intel P5 (Pentium) */
+    else if (is_pentium || is_am486)	/* Am486 / 5x86 / Intel P5 (Pentium) */
 	smram_save_state_p5(saved_state, in_hlt);
-    else if (is_k5 || is_k6)	/* AMD K5 and K6 */
+    else if (is_k5 || is_k6)		/* AMD K5 and K6 */
 	smram_save_state_amd_k(saved_state, in_hlt);
     else if (is_p6)			/* Intel P6 (Pentium Pro, Pentium II, Celeron) */
 	smram_save_state_p6(saved_state, in_hlt);
@@ -1091,8 +1091,11 @@ enter_smm(int in_hlt)
 
     dr[7] = 0x400;
 
-    if (cpu_iscyrix) {
+    if (is_cxsmm) {
 	cpu_state.pc = 0x0000;
+	cpl_override = 1;
+	cyrix_write_seg_descriptor(smram_state - 0x20, &cpu_state.seg_cs);
+	cpl_override = 0;
 	cpu_state.seg_cs.seg = (cyrix.arr[3].base >> 4);
 	cpu_state.seg_cs.base = cyrix.arr[3].base;
 	cpu_state.seg_cs.limit = 0xffffffff;
@@ -1137,15 +1140,14 @@ enter_smm(int in_hlt)
     cpu_state.op32 = use32;
 
     cpl_override = 1;
-    if (cpu_iscyrix) {
+    if (is_cxsmm) {
 	writememl(0, smram_state - 0x04, saved_state[0]);
 	writememl(0, smram_state - 0x08, saved_state[1]);
 	writememl(0, smram_state - 0x0c, saved_state[2]);
 	writememl(0, smram_state - 0x10, saved_state[3]);
 	writememl(0, smram_state - 0x14, saved_state[4]);
 	writememl(0, smram_state - 0x18, saved_state[5]);
-	cyrix_write_seg_descriptor(smram_state - 0x20, &cpu_state.seg_cs);
-	writememl(0, smram_state - 0x18, saved_state[6]);
+	writememl(0, smram_state - 0x24, saved_state[6]);
     } else {
 	for (n = 0; n < SMM_SAVE_STATE_MAP_SIZE; n++) {
 		smram_state -= 4;
@@ -1214,13 +1216,13 @@ leave_smm(void)
     uint32_t smram_state = smbase + 0x10000;
 
     /* If it's a CPU on which SMM is not supported (or not implemented in 86Box), do nothing. */
-    if (!is_am486 && !is_pentium && !is_k5 && !is_k6 && !is_p6 && !is_cx6x86)
+    if (!is_am486 && !is_pentium && !is_k5 && !is_k6 && !is_p6 && !is_cxsmm)
 	return;
 
     memset(saved_state, 0x00, SMM_SAVE_STATE_MAP_SIZE * sizeof(uint32_t));
 
     cpl_override = 1;
-    if (cpu_iscyrix) {
+    if (is_cxsmm) {
 	smram_state = cyrix.smhr & SMHR_ADDR_MASK;
 	saved_state[0] = readmeml(0, smram_state - 0x04);
 	saved_state[1] = readmeml(0, smram_state - 0x08);
@@ -1246,13 +1248,13 @@ leave_smm(void)
     }
 
     x386_common_log("New SMBASE: %08X (%08X)\n", saved_state[SMRAM_FIELD_P5_SMBASE_OFFSET], saved_state[66]);
-    if (cpu_iscyrix)		/* Cx6x86 */
+    if (is_cxsmm)			/* Cx6x86 */
 	smram_restore_state_cyrix(saved_state);
-    else if (is_pentium)	/* Intel P5 (Pentium) */
+    else if (is_pentium || is_am486)	/* Am486 / 5x86 / Intel P5 (Pentium) */
 	smram_restore_state_p5(saved_state);
-    else if (is_k5 || is_k6)	/* AMD K5 and K6 */
+    else if (is_k5 || is_k6)		/* AMD K5 and K6 */
 	smram_restore_state_amd_k(saved_state);
-    else if (is_p6)		/* Intel P6 (Pentium Pro, Pentium II, Celeron) */
+    else if (is_p6)			/* Intel P6 (Pentium Pro, Pentium II, Celeron) */
 	smram_restore_state_p6(saved_state);
 
     in_smm = 0;
@@ -1637,7 +1639,6 @@ sysenter(uint32_t fetchdat)
     cpu_state.seg_cs.base = 0;
     cpu_state.seg_cs.limit_low = 0;
     cpu_state.seg_cs.limit = 0xffffffff;
-    cpu_state.seg_cs.limit_raw = 0x000fffff;
     cpu_state.seg_cs.limit_high = 0xffffffff;
     cpu_state.seg_cs.access = 0x9b;
     cpu_state.seg_cs.ar_high = 0xcf;
@@ -1648,7 +1649,6 @@ sysenter(uint32_t fetchdat)
     cpu_state.seg_ss.base = 0;
     cpu_state.seg_ss.limit_low = 0;
     cpu_state.seg_ss.limit = 0xffffffff;
-    cpu_state.seg_ss.limit_raw = 0x000fffff;
     cpu_state.seg_ss.limit_high = 0xffffffff;
     cpu_state.seg_ss.access = 0x93;
     cpu_state.seg_ss.ar_high = 0xcf;
@@ -1726,7 +1726,6 @@ sysexit(uint32_t fetchdat)
     cpu_state.seg_cs.base = 0;
     cpu_state.seg_cs.limit_low = 0;
     cpu_state.seg_cs.limit = 0xffffffff;
-    cpu_state.seg_cs.limit_raw = 0x000fffff;
     cpu_state.seg_cs.limit_high = 0xffffffff;
     cpu_state.seg_cs.access = 0xfb;
     cpu_state.seg_cs.ar_high = 0xcf;
@@ -1737,7 +1736,6 @@ sysexit(uint32_t fetchdat)
     cpu_state.seg_ss.base = 0;
     cpu_state.seg_ss.limit_low = 0;
     cpu_state.seg_ss.limit = 0xffffffff;
-    cpu_state.seg_ss.limit_raw = 0x000fffff;
     cpu_state.seg_ss.limit_high = 0xffffffff;
     cpu_state.seg_ss.access = 0xf3;
     cpu_state.seg_ss.ar_high = 0xcf;
@@ -1789,7 +1787,6 @@ syscall_op(uint32_t fetchdat)
     cpu_state.seg_cs.base = 0;
     cpu_state.seg_cs.limit_low = 0;
     cpu_state.seg_cs.limit = 0xffffffff;
-    cpu_state.seg_cs.limit_raw = 0x000fffff;
     cpu_state.seg_cs.limit_high = 0xffffffff;
     cpu_state.seg_cs.access = 0x9b;
     cpu_state.seg_cs.ar_high = 0xcf;
@@ -1801,7 +1798,6 @@ syscall_op(uint32_t fetchdat)
     cpu_state.seg_ss.base = 0;
     cpu_state.seg_ss.limit_low = 0;
     cpu_state.seg_ss.limit = 0xffffffff;
-    cpu_state.seg_ss.limit_raw = 0x000fffff;
     cpu_state.seg_ss.limit_high = 0xffffffff;
     cpu_state.seg_ss.access = 0x93;
     cpu_state.seg_ss.ar_high = 0xcf;
@@ -1852,7 +1848,6 @@ sysret(uint32_t fetchdat)
     cpu_state.seg_cs.base = 0;
     cpu_state.seg_cs.limit_low = 0;
     cpu_state.seg_cs.limit = 0xffffffff;
-    cpu_state.seg_cs.limit_raw = 0x000fffff;
     cpu_state.seg_cs.limit_high = 0xffffffff;
     cpu_state.seg_cs.access = 0xfb;
     cpu_state.seg_cs.ar_high = 0xcf;
@@ -1864,7 +1859,6 @@ sysret(uint32_t fetchdat)
     cpu_state.seg_ss.base = 0;
     cpu_state.seg_ss.limit_low = 0;
     cpu_state.seg_ss.limit = 0xffffffff;
-    cpu_state.seg_ss.limit_raw = 0x000fffff;
     cpu_state.seg_ss.limit_high = 0xffffffff;
     cpu_state.seg_ss.access = 0xf3;
     cpu_state.seg_cs.ar_high = 0xcf;
diff --git a/src/cpu/386_ops.h b/src/cpu/386_ops.h
index acfbb8532..b12c5476f 100644
--- a/src/cpu/386_ops.h
+++ b/src/cpu/386_ops.h
@@ -635,6 +635,98 @@ const OpFn OP_TABLE(486_0f)[1024] =
 /*e0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 /*f0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
 };
+
+const OpFn OP_TABLE(c486_0f)[1024] = 
+{
+        /*16-bit data, 16-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
+/*00*/  op0F00_a16,     op0F01_w_a16,   opLAR_w_a16,    opLSL_w_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         opLOADALL386,   opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opRDSHR_a16,    opWRSHR_a16,    ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*70*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opSVDC_a16,     opRSDC_a16,     opSVLDT_a16,    opRSLDT_a16,    opSVTS_a16,     opRSTS_a16,     ILLEGAL,        ILLEGAL,
+
+/*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
+/*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a16,   opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a16,  opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL,        opIMUL_w_w_a16,
+/*b0*/  opCMPXCHG_b_a16,opCMPXCHG_w_a16,opLSS_w_a16,    opBTR_w_r_a16,  opLFS_w_a16,    opLGS_w_a16,    opMOVZX_w_b_a16,opMOVZX_w_w_a16,ILLEGAL,        ILLEGAL,        opBA_w_a16,     opBTC_w_r_a16,  opBSF_w_a16,    opBSR_w_a16,    opMOVSX_w_b_a16,ILLEGAL,
+
+/*c0*/  opXADD_b_a16,   opXADD_w_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*e0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*f0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+        /*32-bit data, 16-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
+/*00*/  op0F00_a16,     op0F01_l_a16,   opLAR_l_a16,    opLSL_l_a16,    ILLEGAL,        ILLEGAL,        opCLTS,         opLOADALL386,   opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL,        opMOV_TRx_r_a16,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opRDSHR_a16,    opWRSHR_a16,    opSVDC_a16,     opRSDC_a16,     opSVLDT_a16,    opRSLDT_a16,    opSVTS_a16,     opRSTS_a16,     ILLEGAL,        ILLEGAL,
+
+/*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*70*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
+/*90*/  opSETO_a16,     opSETNO_a16,    opSETB_a16,     opSETNB_a16,    opSETE_a16,     opSETNE_a16,    opSETBE_a16,    opSETNBE_a16,   opSETS_a16,     opSETNS_a16,    opSETP_a16,     opSETNP_a16,    opSETL_a16,     opSETNL_a16,    opSETLE_a16,    opSETNLE_a16,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a16,   opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a16,  opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL,        opIMUL_l_l_a16,
+/*b0*/  opCMPXCHG_b_a16,opCMPXCHG_l_a16,opLSS_l_a16,    opBTR_l_r_a16,  opLFS_l_a16,    opLGS_l_a16,    opMOVZX_l_b_a16,opMOVZX_l_w_a16,ILLEGAL,        ILLEGAL,        opBA_l_a16,     opBTC_l_r_a16,  opBSF_l_a16,    opBSR_l_a16,    opMOVSX_l_b_a16,opMOVSX_l_w_a16,
+
+/*c0*/  opXADD_b_a16,   opXADD_l_a16,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*e0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*f0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+        /*16-bit data, 32-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
+/*00*/  op0F00_a32,     op0F01_w_a32,   opLAR_w_a32,    opLSL_w_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         opLOADALL386,   opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opRDSHR_a32,    opWRSHR_a32,    ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*70*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opSVDC_a32,     opRSDC_a32,     opSVLDT_a32,    opRSLDT_a32,    opSVTS_a32,     opRSTS_a32,     ILLEGAL,        ILLEGAL,
+
+/*80*/  opJO_w,         opJNO_w,        opJB_w,         opJNB_w,        opJE_w,         opJNE_w,        opJBE_w,        opJNBE_w,       opJS_w,         opJNS_w,        opJP_w,         opJNP_w,        opJL_w,         opJNL_w,        opJLE_w,        opJNLE_w,
+/*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
+/*a0*/  opPUSH_FS_w,    opPOP_FS_w,     opCPUID,        opBT_w_r_a32,   opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_w,    opPOP_GS_w,     opRSM,          opBTS_w_r_a32,  opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL,        opIMUL_w_w_a32,
+/*b0*/  opCMPXCHG_b_a32,opCMPXCHG_w_a32,opLSS_w_a32,    opBTR_w_r_a32,  opLFS_w_a32,    opLGS_w_a32,    opMOVZX_w_b_a32,opMOVZX_w_w_a32,ILLEGAL,        ILLEGAL,        opBA_w_a32,     opBTC_w_r_a32,  opBSF_w_a32,    opBSR_w_a32,    opMOVSX_w_b_a32,ILLEGAL,
+
+/*c0*/  opXADD_b_a32,   opXADD_w_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*e0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*f0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+        /*32-bit data, 32-bit addr*/
+/*      00              01              02              03              04              05              06              07              08              09              0a              0b              0c              0d              0e              0f*/        
+/*00*/  op0F00_a32,     op0F01_l_a32,   opLAR_l_a32,    opLSL_l_a32,    ILLEGAL,        ILLEGAL,        opCLTS,         opLOADALL386,   opINVD,         opWBINVD,       ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*10*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*20*/  opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL,        opMOV_TRx_r_a32,ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*30*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opRDSHR_a32,    opWRSHR_a32,    ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+
+/*40*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*50*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*60*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*70*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opSVDC_a16,     opRSDC_a16,     opSVLDT_a16,    opRSLDT_a16,    opSVTS_a16,     opRSTS_a16,     ILLEGAL,        ILLEGAL,
+
+/*80*/  opJO_l,         opJNO_l,        opJB_l,         opJNB_l,        opJE_l,         opJNE_l,        opJBE_l,        opJNBE_l,       opJS_l,         opJNS_l,        opJP_l,         opJNP_l,        opJL_l,         opJNL_l,        opJLE_l,        opJNLE_l,
+/*90*/  opSETO_a32,     opSETNO_a32,    opSETB_a32,     opSETNB_a32,    opSETE_a32,     opSETNE_a32,    opSETBE_a32,    opSETNBE_a32,   opSETS_a32,     opSETNS_a32,    opSETP_a32,     opSETNP_a32,    opSETL_a32,     opSETNL_a32,    opSETLE_a32,    opSETNLE_a32,
+/*a0*/  opPUSH_FS_l,    opPOP_FS_l,     opCPUID,        opBT_l_r_a32,   opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL,        ILLEGAL,        opPUSH_GS_l,    opPOP_GS_l,     opRSM,          opBTS_l_r_a32,  opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL,        opIMUL_l_l_a32,
+/*b0*/  opCMPXCHG_b_a32,opCMPXCHG_l_a32,opLSS_l_a32,    opBTR_l_r_a32,  opLFS_l_a32,    opLGS_l_a32,    opMOVZX_l_b_a32,opMOVZX_l_w_a32,ILLEGAL,        ILLEGAL,        opBA_l_a32,     opBTC_l_r_a32,  opBSF_l_a32,    opBSR_l_a32,    opMOVSX_l_b_a32,opMOVSX_l_w_a32,
+
+/*c0*/  opXADD_b_a32,   opXADD_l_a32,   ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        opBSWAP_EAX,    opBSWAP_ECX,    opBSWAP_EDX,    opBSWAP_EBX,    opBSWAP_ESP,    opBSWAP_EBP,    opBSWAP_ESI,    opBSWAP_EDI,
+/*d0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*e0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+/*f0*/  ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,        ILLEGAL,
+};
+
 const OpFn OP_TABLE(ibm486_0f)[1024] = 
 {
         /*16-bit data, 16-bit addr*/
diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c
index 4f31ab5ad..7d71744e9 100644
--- a/src/cpu/cpu.c
+++ b/src/cpu/cpu.c
@@ -110,7 +110,7 @@ int		isa_cycles,
 
  		is286, is386, is486 = 1, is486sx, is486dx, is486sx2, is486dx2, isdx4,
 		cpu_isintel, cpu_iscyrix, hascache, isibm486, israpidcad, is_vpc,
-		is_am486, is_pentium, is_k5, is_k6, is_p6, is_cx6x86, hasfpu,
+		is_am486, is_486_org, is_pentium, is_k5, is_k6, is_p6, is_cxsmm, hasfpu,
 
 		timing_rr, timing_mr, timing_mrl, timing_rm, timing_rml,
 		timing_mm, timing_mml, timing_bt, timing_bnt,
@@ -373,6 +373,8 @@ cpu_set(void)
     is486dx      = (cpu_s->cpu_type >= CPU_i486DX) && (cpu_s->cpu_type < CPU_i486DX2);
     is486dx2     = (cpu_s->cpu_type >= CPU_i486DX2) && (cpu_s->cpu_type < CPU_iDX4);	
     isdx4        = (cpu_s->cpu_type >= CPU_iDX4) && (cpu_s->cpu_type < CPU_WINCHIP);
+    is_486_org   = (cpu_s->cpu_type == CPU_i486SX) || (cpu_s->cpu_type == CPU_i486DX) ||
+		   (cpu_s->cpu_type == CPU_Am486SX) || (cpu_s->cpu_type == CPU_Am486DX);
     is_am486     = !strcmp(cpu_f->manufacturer, "AMD") && (cpu_s->cpu_type >= CPU_Am486SX) && (cpu_s->cpu_type <= CPU_Am5x86);
 
     cpu_isintel = !strcmp(cpu_f->manufacturer, "Intel");
@@ -380,13 +382,13 @@ cpu_set(void)
 
     /* The 486DX2 and iDX4 have the same SMM save state table layout as Pentiums,
        and the WinChip datasheet claims those are Pentium-compatible as well. */
-    is_pentium   = (cpu_isintel && (cpu_s->cpu_type >= CPU_i486DX2) && (cpu_s->cpu_type < CPU_PENTIUMPRO)) ||
+    is_pentium   = (cpu_isintel && (cpu_s->cpu_type >= CPU_i486SX) && (cpu_s->cpu_type < CPU_PENTIUMPRO)) ||
 		   !strcmp(cpu_f->manufacturer, "IDT");
     is_k5        = !strcmp(cpu_f->manufacturer, "AMD") && (cpu_s->cpu_type > CPU_Am5x86);
     is_k6        = (cpu_s->cpu_type >= CPU_K6) && !strcmp(cpu_f->manufacturer, "AMD");
     /* The Samuel 2 datasheet claims it's Celeron-compatible. */
     is_p6        = (cpu_isintel && (cpu_s->cpu_type >= CPU_PENTIUMPRO)) || !strcmp(cpu_f->manufacturer, "VIA");
-    is_cx6x86    = !strcmp(cpu_f->manufacturer, "Cyrix") && (cpu_s->cpu_type > CPU_Cx5x86);
+    is_cxsmm     = !strcmp(cpu_f->manufacturer, "Cyrix") && (cpu_s->cpu_type >= CPU_Cx486S);
 
     hasfpu       = (fpu_type != FPU_NONE);
     hascache     = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC) ||
@@ -816,9 +818,9 @@ cpu_set(void)
 	case CPU_Cx486DX2:
 	case CPU_Cx486DX4:
 #ifdef USE_DYNAREC
-		x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
+		x86_setopcodes(ops_386, ops_c486_0f, dynarec_ops_386, dynarec_ops_c486_0f);
 #else
-		x86_setopcodes(ops_386, ops_486_0f);
+		x86_setopcodes(ops_386, ops_c486_0f);
 #endif
 
                 timing_rr			=   1;	/* register dest - register src */
@@ -856,9 +858,9 @@ cpu_set(void)
 
 	case CPU_Cx5x86:
 #ifdef USE_DYNAREC
-		x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
+		x86_setopcodes(ops_386, ops_c486_0f, dynarec_ops_386, dynarec_ops_c486_0f);
 #else
-		x86_setopcodes(ops_386, ops_486_0f);
+		x86_setopcodes(ops_386, ops_c486_0f);
 #endif
 
 		timing_rr			=   1;	/* register dest - register src */
@@ -1027,7 +1029,6 @@ cpu_set(void)
   	case CPU_Cx6x86MX:
 		if (cpu_s->cpu_type == CPU_Cx6x86MX) {
 #ifdef USE_DYNAREC
-			x86_setopcodes(ops_386, ops_c6x86mx_0f, dynarec_ops_386, dynarec_ops_c6x86mx_0f);
 			x86_dynarec_opcodes_da_a16 = dynarec_ops_fpu_686_da_a16;
 			x86_dynarec_opcodes_da_a32 = dynarec_ops_fpu_686_da_a32;
 			x86_dynarec_opcodes_db_a16 = dynarec_ops_fpu_686_db_a16;
@@ -1049,7 +1050,8 @@ cpu_set(void)
 		else if (cpu_s->cpu_type == CPU_Cx6x86L)
 			x86_setopcodes(ops_386, ops_pentium_0f, dynarec_ops_386, dynarec_ops_pentium_0f);
 		else
-			x86_setopcodes(ops_386, ops_c6x86_0f, dynarec_ops_386, dynarec_ops_c6x86_0f);
+			x86_setopcodes(ops_386, ops_c6x86mx_0f, dynarec_ops_386, dynarec_ops_c6x86mx_0f);
+			// x86_setopcodes(ops_386, ops_c6x86_0f, dynarec_ops_386, dynarec_ops_c6x86_0f);
 #else
 		if (cpu_s->cpu_type == CPU_Cx6x86MX)
 			x86_setopcodes(ops_386, ops_c6x86mx_0f);
@@ -2935,23 +2937,27 @@ cpu_write(uint16_t addr, uint8_t val, void *priv)
 		ccr2 = val;
 		break;
 	case 0xc3:	/* CCR3 */
+		pclog("CC3     WRITE: %02X\n", val);
 		if ((ccr3 & CCR3_SMI_LOCK) && !in_smm)
 			val = (val & ~(CCR3_NMI_EN)) | (ccr3 & CCR3_NMI_EN) | CCR3_SMI_LOCK;
 		ccr3 = val;
 		break;
 	case 0xcd:
+		pclog("ARR3_24 WRITE: %02X\n", val);
 		if (!(ccr3 & CCR3_SMI_LOCK) || in_smm) {
 			cyrix.arr[3].base = (cyrix.arr[3].base & ~0xff000000) | (val << 24);
 			cyrix.smhr &= ~SMHR_VALID;
 		}
 		break;
 	case 0xce:
+		pclog("ARR3_16 WRITE: %02X\n", val);
 		if (!(ccr3 & CCR3_SMI_LOCK) || in_smm) {
 			cyrix.arr[3].base = (cyrix.arr[3].base & ~0x00ff0000) | (val << 16);
 			cyrix.smhr &= ~SMHR_VALID;
 		}
 		break;
 	case 0xcf:
+		pclog("ARR3_08 WRITE: %02X\n", val);
 		if (!(ccr3 & CCR3_SMI_LOCK) || in_smm) {
 			cyrix.arr[3].base = (cyrix.arr[3].base & ~0x0000f000) | ((val & 0xf0) << 8);
 			if ((val & 0xf) == 0xf)
diff --git a/src/cpu/cpu.h b/src/cpu/cpu.h
index 2ebd1362e..2a9996a06 100644
--- a/src/cpu/cpu.h
+++ b/src/cpu/cpu.h
@@ -218,8 +218,7 @@ typedef struct {
     uint8_t	access, ar_high;
     int8_t	checked; /*Non-zero if selector is known to be valid*/
     uint16_t	seg;
-    uint32_t	base,
-		limit, limit_raw,
+    uint32_t	base, limit,
 		limit_low, limit_high;
 } x86seg;
 
@@ -484,7 +483,7 @@ extern int	cpu_cyrix_alignment;	/*Cyrix 5x86/6x86 only has data misalignment
 					  penalties when crossing 8-byte boundaries*/
 
 extern int	is8086,	is286, is386, is486, is486sx, is486dx, is486sx2, is486dx2, isdx4;
-extern int	is_am486, is_pentium, is_k5, is_k6, is_p6, is_cx6x86;
+extern int	is_am486, is_486_org, is_pentium, is_k5, is_k6, is_p6, is_cxsmm;
 extern int	hascache;
 extern int	isibm486;
 extern int	is_rapidcad;
diff --git a/src/cpu/x86.c b/src/cpu/x86.c
index 70ef37701..f8e13764e 100644
--- a/src/cpu/x86.c
+++ b/src/cpu/x86.c
@@ -281,7 +281,7 @@ reset_common(int hard)
     smi_block = 0;
 
     if (hard) {
-	smbase = 0x00030000;
+	smbase = is_486_org ? 0x00060000 : 0x00030000;
 	ppi_reset();
     }
     in_sys = 0;
diff --git a/src/cpu/x86_ops.h b/src/cpu/x86_ops.h
index 1e81b386a..dc0d62782 100644
--- a/src/cpu/x86_ops.h
+++ b/src/cpu/x86_ops.h
@@ -79,6 +79,7 @@ extern const OpFn dynarec_ops_386[1024];
 extern const OpFn dynarec_ops_386_0f[1024];
 
 extern const OpFn dynarec_ops_486_0f[1024];
+extern const OpFn dynarec_ops_c486_0f[1024];
 extern const OpFn dynarec_ops_ibm486_0f[1024];
 
 extern const OpFn dynarec_ops_winchip_0f[1024];
@@ -176,6 +177,7 @@ extern const OpFn ops_386[1024];
 extern const OpFn ops_386_0f[1024];
 
 extern const OpFn ops_486_0f[1024];
+extern const OpFn ops_c486_0f[1024];
 extern const OpFn ops_ibm486_0f[1024];
 
 extern const OpFn ops_winchip_0f[1024];
diff --git a/src/cpu/x86_ops_cyrix.h b/src/cpu/x86_ops_cyrix.h
index e6464ce84..9ca01a9b3 100644
--- a/src/cpu/x86_ops_cyrix.h
+++ b/src/cpu/x86_ops_cyrix.h
@@ -35,7 +35,7 @@ static void opSVDC_common(uint32_t fetchdat)
 }
 static int opSVDC_a16(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
         {
                 fetch_ea_16(fetchdat);
                 SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -48,7 +48,7 @@ static int opSVDC_a16(uint32_t fetchdat)
 }
 static int opSVDC_a32(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
         {
                 fetch_ea_32(fetchdat);
                 SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -86,7 +86,7 @@ static void opRSDC_common(uint32_t fetchdat)
 }
 static int opRSDC_a16(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
         {
                 fetch_ea_16(fetchdat);
                 SEG_CHECK_READ(cpu_state.ea_seg);
@@ -99,7 +99,7 @@ static int opRSDC_a16(uint32_t fetchdat)
 }
 static int opRSDC_a32(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
         {
                 fetch_ea_32(fetchdat);
                 SEG_CHECK_READ(cpu_state.ea_seg);
@@ -113,7 +113,7 @@ static int opRSDC_a32(uint32_t fetchdat)
 
 static int opSVLDT_a16(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
         {
                 fetch_ea_16(fetchdat);
                 SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -127,7 +127,7 @@ static int opSVLDT_a16(uint32_t fetchdat)
 }
 static int opSVLDT_a32(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
         {
                 fetch_ea_32(fetchdat);
                 SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -142,7 +142,7 @@ static int opSVLDT_a32(uint32_t fetchdat)
 
 static int opRSLDT_a16(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
         {
                 fetch_ea_16(fetchdat);
                 SEG_CHECK_READ(cpu_state.ea_seg);
@@ -155,7 +155,7 @@ static int opRSLDT_a16(uint32_t fetchdat)
 }
 static int opRSLDT_a32(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
         {
                 fetch_ea_32(fetchdat);
                 SEG_CHECK_READ(cpu_state.ea_seg);
@@ -169,7 +169,7 @@ static int opRSLDT_a32(uint32_t fetchdat)
 
 static int opSVTS_a16(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
         {
                 fetch_ea_16(fetchdat);
                 SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -183,7 +183,7 @@ static int opSVTS_a16(uint32_t fetchdat)
 }
 static int opSVTS_a32(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
         {
                 fetch_ea_32(fetchdat);
                 SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -198,7 +198,7 @@ static int opSVTS_a32(uint32_t fetchdat)
 
 static int opRSTS_a16(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
         {
                 fetch_ea_16(fetchdat);
                 SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -212,7 +212,7 @@ static int opRSTS_a16(uint32_t fetchdat)
 }
 static int opRSTS_a32(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
         {
                 fetch_ea_32(fetchdat);
                 SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -227,7 +227,7 @@ static int opRSTS_a32(uint32_t fetchdat)
 
 static int opSMINT(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
                 fatal("opSMINT\n");
         else
                 x86illegal();
@@ -237,7 +237,7 @@ static int opSMINT(uint32_t fetchdat)
 
 static int opRDSHR_a16(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
                 fatal("opRDSHR_a16\n");
         else
                 x86illegal();
@@ -246,7 +246,7 @@ static int opRDSHR_a16(uint32_t fetchdat)
 }
 static int opRDSHR_a32(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
                 fatal("opRDSHR_a32\n");
         else
                 x86illegal();
@@ -256,7 +256,7 @@ static int opRDSHR_a32(uint32_t fetchdat)
 
 static int opWRSHR_a16(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
                 fatal("opWRSHR_a16\n");
         else
                 x86illegal();
@@ -265,7 +265,7 @@ static int opWRSHR_a16(uint32_t fetchdat)
 }
 static int opWRSHR_a32(uint32_t fetchdat)
 {
-        if (cpu_cur_status & CPU_STATUS_SMM)
+        if (in_smm)
                 fatal("opWRSHR_a32\n");
         else
                 x86illegal();
diff --git a/src/cpu/x86_ops_pmode.h b/src/cpu/x86_ops_pmode.h
index b372da126..b031fac22 100644
--- a/src/cpu/x86_ops_pmode.h
+++ b/src/cpu/x86_ops_pmode.h
@@ -198,7 +198,6 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
                 granularity = readmemb(0, addr + 6) & 0x80;
                 if (cpu_state.abrt) return 1;
                 ldt.limit = limit;
-                ldt.limit_raw = limit;
                 ldt.access = access;
                 ldt.ar_high = ar_high;
                 if (granularity)
@@ -232,7 +231,6 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
                 if (cpu_state.abrt) return 1;
                 tr.seg = sel;
                 tr.limit = limit;
-                tr.limit_raw = limit;
                 tr.access = access;
                 tr.ar_high = ar_high;
                 if (granularity)
diff --git a/src/cpu/x86seg.c b/src/cpu/x86seg.c
index a9c3923c8..1304f041c 100644
--- a/src/cpu/x86seg.c
+++ b/src/cpu/x86seg.c
@@ -227,7 +227,6 @@ void
 do_seg_load(x86seg *s, uint16_t *segdat)
 {
     s->limit = segdat[0] | ((segdat[3] & 0x000f) << 16);
-    s->limit_raw = s->limit;
     if (segdat[3] & 0x0080)
 	s->limit = (s->limit << 12) | 0xfff;
     s->base = segdat[1] | ((segdat[2] & 0x00ff) << 16);
@@ -2382,9 +2381,14 @@ taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
 void
 cyrix_write_seg_descriptor(uint32_t addr, x86seg *seg)
 {
-    writememl(0, addr, (seg->limit_raw & 0xffff) | (seg->base << 16));
+    uint32_t limit_raw = seg->limit;
+
+    if (seg->ar_high & 0x80)
+	limit_raw >>= 12;
+
+    writememl(0, addr, (limit_raw & 0xffff) | (seg->base << 16));
     writememl(0, addr + 4, ((seg->base >> 16) & 0xff) | (seg->access << 8) |
-	      (seg->limit_raw & 0xf0000) | (seg->ar_high << 16) |
+	      (limit_raw & 0xf0000) | (seg->ar_high << 16) |
 	      (seg->base & 0xff000000));
 }
 
@@ -2420,4 +2424,6 @@ cyrix_load_seg_descriptor(uint32_t addr, x86seg *seg)
 		codegen_flat_ss = 0;
 	}
     }
+
+    pclog("clsd(): NEW CS:IP = %04X:%08X (%08X)\n", CS, cpu_state.pc, cs + cpu_state.pc);
 }
diff --git a/src/device/keyboard_at.c b/src/device/keyboard_at.c
index f6b9f7be0..600c61bb4 100644
--- a/src/device/keyboard_at.c
+++ b/src/device/keyboard_at.c
@@ -1061,7 +1061,7 @@ write_output(atkbd_t *dev, uint8_t val)
 		/* Pin 0 selected. */
 		softresetx86(); /*Pulse reset!*/
 		cpu_set_edx();
-		smbase = 0x00030000;
+		smbase = is_486_org ? 0x00060000 : 0x00030000;
 	}
     }
     /* Mask off the A20 stuff because we use mem_a20_key directly for that. */
diff --git a/src/machine/machine.c b/src/machine/machine.c
index e3869c970..045e81c30 100644
--- a/src/machine/machine.c
+++ b/src/machine/machine.c
@@ -81,7 +81,7 @@ machine_init_ex(int m)
 
 	/* Reset the memory state. */
 	mem_reset();
-	smbase = 0x00030000;
+	smbase = is_486_org ? 0x00060000 : 0x00030000;
 
 	lpt_init();
     }