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Add Page Global Enable feature (toggleable by an MSR) to the Cyrix III

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Alexander Babikov
2023-11-01 23:37:50 +05:00
parent b0b857a50e
commit 8b741d511e
1 changed files with 12 additions and 4 deletions
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14
src/cpu/cpu.c
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@@ -1745,8 +1745,8 @@ cpu_set(void)
timing_misaligned = 2; timing_misaligned = 2;
cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MMX | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_3DNOW; cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MMX | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_3DNOW;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21); msr.fcr = (1 << 7) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21);
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE; cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE | CR4_PGE;
cpu_cyrix_alignment = 1; cpu_cyrix_alignment = 1;
@@ -2433,6 +2433,8 @@ cpu_CPUID(void)
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR | CPUID_MCE | CPUID_MMX | CPUID_MTRR; EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR | CPUID_MCE | CPUID_MMX | CPUID_MTRR;
if (cpu_has_feature(CPU_FEATURE_CX8)) if (cpu_has_feature(CPU_FEATURE_CX8))
EDX |= CPUID_CMPXCHG8B; EDX |= CPUID_CMPXCHG8B;
if (msr.fcr & (1 << 7))
EDX |= CPUID_PGE;
break; break;
case 0x80000000: case 0x80000000:
EAX = 0x80000005; EAX = 0x80000005;
@@ -2442,6 +2444,8 @@ cpu_CPUID(void)
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR | CPUID_MCE | CPUID_MMX | CPUID_MTRR | CPUID_3DNOW; EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR | CPUID_MCE | CPUID_MMX | CPUID_MTRR | CPUID_3DNOW;
if (cpu_has_feature(CPU_FEATURE_CX8)) if (cpu_has_feature(CPU_FEATURE_CX8))
EDX |= CPUID_CMPXCHG8B; EDX |= CPUID_CMPXCHG8B;
if (msr.fcr & (1 << 7))
EDX |= CPUID_PGE;
break; break;
case 0x80000002: /* Processor name string */ case 0x80000002: /* Processor name string */
EAX = 0x20414956; /* VIA Samuel */ EAX = 0x20414956; /* VIA Samuel */
@@ -2497,7 +2501,7 @@ cpu_ven_reset(void)
break; break;
case CPU_CYRIX3S: case CPU_CYRIX3S:
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 18) | (1 << 19) | msr.fcr = (1 << 7) (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 18) | (1 << 19) |
(1 << 20) | (1 << 21); (1 << 20) | (1 << 21);
break; break;
} }
@@ -3098,6 +3102,10 @@ cpu_WRMSR(void)
cpu_features |= CPU_FEATURE_CX8; cpu_features |= CPU_FEATURE_CX8;
else else
cpu_features &= ~CPU_FEATURE_CX8; cpu_features &= ~CPU_FEATURE_CX8;
if (EAX & (1 << 7))
cpu_CR4_mask |= CR4_PGE;
else
cpu_CR4_mask &= ~CR4_PGE;
break; break;
case 0x1108: case 0x1108:
msr.fcr2 = EAX | ((uint64_t) EDX << 32); msr.fcr2 = EAX | ((uint64_t) EDX << 32);