From 8b7d643452e531a97019776dbcfb78baa8e3768f Mon Sep 17 00:00:00 2001 From: Panagiotis <58827426+tiseno100@users.noreply.github.com> Date: Sat, 13 Feb 2021 12:31:04 +0200 Subject: [PATCH] Sanitize some old chipset code (Part 3) Fixed the Indentation of the Intel 82335, removed useless includes and numerous bugfixes on the OPTi Python. --- src/chipset/intel_82335.c | 126 ++++++++++++++------------- src/chipset/opti5x7.c | 175 +++++++++++++++++++------------------- 2 files changed, 148 insertions(+), 153 deletions(-) diff --git a/src/chipset/intel_82335.c b/src/chipset/intel_82335.c index edb8f266a..d123b4bdc 100644 --- a/src/chipset/intel_82335.c +++ b/src/chipset/intel_82335.c @@ -8,7 +8,7 @@ * * Implementation of the Intel 82335(KU82335) chipset. * - * Copyright 2020 Tiseno100 + * Copyright 2021 Tiseno100 * */ @@ -24,10 +24,7 @@ #include <86box/timer.h> #include <86box/io.h> #include <86box/device.h> -#include <86box/keyboard.h> #include <86box/mem.h> -#include <86box/fdd.h> -#include <86box/fdc.h> #include <86box/chipset.h> /* Shadow capabilities */ @@ -38,7 +35,7 @@ /* Granularity Register Enable & Recalc */ #define EXTENDED_GRANULARITY_ENABLED (dev->regs[0x2c] & 0x01) -#define GRANULARITY_RECALC ((dev->regs[0x2e] & (1 << (i+8))) ? ((dev->regs[0x2e] & (1 << i)) ? RO_SHADOW : RW_SHADOW) : DISABLED_SHADOW) +#define GRANULARITY_RECALC ((dev->regs[0x2e] & (1 << (i + 8))) ? ((dev->regs[0x2e] & (1 << i)) ? RO_SHADOW : RW_SHADOW) : DISABLED_SHADOW) /* R/W operator for the Video RAM region */ #define DETERMINE_VIDEO_RAM_WRITE_ACCESS ((dev->regs[0x22] & (0x08 << 8)) ? RW_SHADOW : RO_SHADOW) @@ -61,8 +58,8 @@ typedef struct { uint16_t regs[256], - - cfg_locked; + + cfg_locked; } intel_82335_t; @@ -73,10 +70,11 @@ intel_82335_log(const char *fmt, ...) { va_list ap; - if (intel_82335_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + if (intel_82335_do_log) + { + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else @@ -86,92 +84,90 @@ intel_82335_log(const char *fmt, ...) static void intel_82335_write(uint16_t addr, uint16_t val, void *priv) { - intel_82335_t *dev = (intel_82335_t *) priv; + intel_82335_t *dev = (intel_82335_t *)priv; uint32_t romsize = 0, base = 0, i = 0, rc1_remap = 0, rc2_remap = 0; dev->regs[addr] = val; - if(!dev->cfg_locked) + if (!dev->cfg_locked) { - intel_82335_log("Register %02x: Write %04x\n", addr, val); + intel_82335_log("Register %02x: Write %04x\n", addr, val); - switch (addr) { - case 0x22: /* Memory Controller */ + switch (addr) + { + case 0x22: /* Memory Controller */ - /* Check if the ROM chips are 256 or 512Kbit (Just for Shadowing sanity) */ - romsize = ROM_SIZE; + /* Check if the ROM chips are 256 or 512Kbit (Just for Shadowing sanity) */ + romsize = ROM_SIZE; - if (!EXTENDED_GRANULARITY_ENABLED) - { - shadowbios = !!(dev->regs[0x22] & 0x01); - shadowbios_write = !!(dev->regs[0x22] & 0x01); + if (!EXTENDED_GRANULARITY_ENABLED) + { + shadowbios = !!(dev->regs[0x22] & 0x01); + shadowbios_write = !!(dev->regs[0x22] & 0x01); - /* Base System 512/640KB set */ - mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? ENABLE_TOP_128KB : DISABLE_TOP_128KB); + /* Base System 512/640KB set */ + mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? ENABLE_TOP_128KB : DISABLE_TOP_128KB); - /* Video RAM shadow*/ - mem_set_mem_state_both(0xa0000, 0x20000, (dev->regs[0x22] & (0x04 << 8)) ? DETERMINE_VIDEO_RAM_WRITE_ACCESS : DISABLED_SHADOW); + /* Video RAM shadow*/ + mem_set_mem_state_both(0xa0000, 0x20000, (dev->regs[0x22] & (0x04 << 8)) ? DETERMINE_VIDEO_RAM_WRITE_ACCESS : DISABLED_SHADOW); - /* Option ROM shadow */ - mem_set_mem_state_both(0xc0000, 0x20000, (dev->regs[0x22] & (0x02 << 8)) ? ENABLED_SHADOW : DISABLED_SHADOW); + /* Option ROM shadow */ + mem_set_mem_state_both(0xc0000, 0x20000, (dev->regs[0x22] & (0x02 << 8)) ? ENABLED_SHADOW : DISABLED_SHADOW); - /* System ROM shadow */ - mem_set_mem_state_both(0xe0000, 0x20000, (dev->regs[0x22] & 0x01) ? ENABLED_SHADOW : DISABLED_SHADOW); - } - break; + /* System ROM shadow */ + mem_set_mem_state_both(0xe0000, 0x20000, (dev->regs[0x22] & 0x01) ? ENABLED_SHADOW : DISABLED_SHADOW); + } + break; - case 0x24: /* Roll Compare (Just top remapping. Not followed according to datasheet!) */ - case 0x26: - rc1_remap = (dev->regs[0x24] & 0x01) ? DEFINE_RC1_REMAP_SIZE : 0; - rc2_remap = (dev->regs[0x26] & 0x01) ? DEFINE_RC2_REMAP_SIZE : 0; - mem_remap_top(rc1_remap+rc2_remap); - break; + case 0x24: /* Roll Compare (Just top remapping. Not followed according to datasheet!) */ + case 0x26: + rc1_remap = (dev->regs[0x24] & 0x01) ? DEFINE_RC1_REMAP_SIZE : 0; + rc2_remap = (dev->regs[0x26] & 0x01) ? DEFINE_RC2_REMAP_SIZE : 0; + mem_remap_top(rc1_remap + rc2_remap); + break; - case 0x2e: /* Extended Granularity (Enabled if Bit 0 in Register 2Ch is set) */ - if(EXTENDED_GRANULARITY_ENABLED) - { - for(i=0; i<8; i++) - { - base = 0xc0000 + (i << 15); - shadowbios = (dev->regs[0x2e] & (1 << (i+8))) && (base == romsize); - shadowbios_write = (dev->regs[0x2e] & (1 << i)) && (base == romsize); - mem_set_mem_state_both(base, 0x8000, GRANULARITY_RECALC); - } - break; - } - } + case 0x2e: /* Extended Granularity (Enabled if Bit 0 in Register 2Ch is set) */ + if (EXTENDED_GRANULARITY_ENABLED) + { + for (i = 0; i < 8; i++) + { + base = 0xc0000 + (i << 15); + shadowbios = (dev->regs[0x2e] & (1 << (i + 8))) && (base == romsize); + shadowbios_write = (dev->regs[0x2e] & (1 << i)) && (base == romsize); + mem_set_mem_state_both(base, 0x8000, GRANULARITY_RECALC); + } + break; + } + } } /* Unlock/Lock configuration registers */ dev->cfg_locked = LOCK_STATUS; } - static uint16_t intel_82335_read(uint16_t addr, void *priv) { - intel_82335_t *dev = (intel_82335_t *) priv; + intel_82335_t *dev = (intel_82335_t *)priv; intel_82335_log("Register %02x: Read %04x\n", addr, dev->regs[addr]); return dev->regs[addr]; - } static void intel_82335_close(void *priv) { - intel_82335_t *dev = (intel_82335_t *) priv; + intel_82335_t *dev = (intel_82335_t *)priv; free(dev); } - static void * intel_82335_init(const device_t *info) { - intel_82335_t *dev = (intel_82335_t *) malloc(sizeof(intel_82335_t)); + intel_82335_t *dev = (intel_82335_t *)malloc(sizeof(intel_82335_t)); memset(dev, 0, sizeof(intel_82335_t)); memset(dev->regs, 0, sizeof(dev->regs)); @@ -195,17 +191,19 @@ intel_82335_init(const device_t *info) io_sethandler(0x002c, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev); /* Extended Granularity */ - io_sethandler(0x002e, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev); - + io_sethandler(0x002e, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev); + return dev; } - const device_t intel_82335_device = { "Intel 82335", 0, 0, - intel_82335_init, intel_82335_close, NULL, - { NULL }, NULL, NULL, - NULL -}; + intel_82335_init, + intel_82335_close, + NULL, + {NULL}, + NULL, + NULL, + NULL}; diff --git a/src/chipset/opti5x7.c b/src/chipset/opti5x7.c index 8b232e682..f4231c8de 100644 --- a/src/chipset/opti5x7.c +++ b/src/chipset/opti5x7.c @@ -6,13 +6,15 @@ * * This file is part of the 86Box distribution. * - * Implementation of the OPTi 82C546/82C547 & 82C596/82C597 chipsets. + * Implementation of the OPTi 82C546/82C547(Python) & 82C596/82C597(Cobra) chipsets. - * Authors: plant/nerd73 - * Miran Grca, + * Authors: plant/nerd73, + * Miran Grca, + * Tiseno100 * - * Copyright 2020 plant/nerd73. - * Copyright 2020 Miran Grca. + * Copyright 2020 plant/nerd73. + * Copyright 2020 Miran Grca. + * Copyright 2021 Tiseno100. */ #include #include @@ -26,142 +28,134 @@ #include <86box/timer.h> #include <86box/io.h> #include <86box/device.h> -#include <86box/keyboard.h> #include <86box/mem.h> -#include <86box/fdd.h> -#include <86box/fdc.h> #include <86box/port_92.h> #include <86box/chipset.h> +/* Shadow RAM */ +#define SHADOW_RECALC (((dev->regs[(i < 4) ? 4 : 5] & (1 << ((i < 4) ? i : i - 4) * 2)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[(i < 4) ? 4 : 5] & (1 << (((i < 4) ? i : i - 4) * 2 + 1))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)) +#define SHADOW_E_RECALC (((dev->regs[0x06] & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x06] & 2) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)) +#define SHADOW_F_RECALC (((dev->regs[0x06] & 4) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x06] & 8) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)) typedef struct { - uint8_t idx, - regs[16]; - port_92_t *port_92; + uint8_t idx, regs[16]; } opti5x7_t; - #ifdef ENABLE_OPTI5X7_LOG int opti5x7_do_log = ENABLE_OPTI5X7_LOG; - static void opti5x7_log(const char *fmt, ...) { va_list ap; - if (opti5x7_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + if (opti5x7_do_log) + { + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else #define opti5x7_log(fmt, ...) #endif - static void -opti5x7_recalc(opti5x7_t *dev) +shadow_map(opti5x7_t *dev) { - uint32_t base; - uint32_t i, shflags = 0; - uint32_t reg, lowest_bit; - - shadowbios = 0; - shadowbios_write = 0; - - for (i = 0; i < 8; i++) { - base = 0xc0000 + (i << 14); - - lowest_bit = (i << 1) & 0x07; - reg = 0x04 + ((base >> 16) & 0x01); - - shflags = (dev->regs[reg] & (1 << lowest_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - shflags |= (dev->regs[reg] & (1 << (lowest_bit + 1))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; - mem_set_mem_state(base, 0x4000, shflags); - } - - shadowbios |= !!(dev->regs[0x06] & 0x05); - shadowbios_write |= !!(dev->regs[0x06] & 0x0a); - - shflags = (dev->regs[0x06] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - shflags |= (dev->regs[0x06] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; - mem_set_mem_state(0xe0000, 0x10000, shflags); - - shflags = (dev->regs[0x06] & 0x04) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - shflags |= (dev->regs[0x06] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; - mem_set_mem_state(0xf0000, 0x10000, shflags); + for (int i = 0; i < 8; i++) + mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, SHADOW_RECALC); + mem_set_mem_state_both(0xe0000, 0x10000, SHADOW_E_RECALC); + shadowbios = !!(dev->regs[0x06] & 5); + shadowbios_write = !!(dev->regs[0x06] & 0x0a); + mem_set_mem_state_both(0xf0000, 0x10000, SHADOW_F_RECALC); flushmmucache(); } - static void opti5x7_write(uint16_t addr, uint8_t val, void *priv) -{ - opti5x7_t *dev = (opti5x7_t *) priv; - opti5x7_log("Write %02x to OPTi 5x7 address %02x\n", val, addr); - - switch (addr) { - case 0x22: - dev->idx = val; - break; - case 0x24: - dev->regs[dev->idx] = val; - switch(dev->idx) { - case 0x02: - cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x04 & 0x08); - break; +{ + opti5x7_t *dev = (opti5x7_t *)priv; - case 0x04: - case 0x05: - case 0x06: - opti5x7_recalc(dev); - break; - } - break; + switch (addr) + { + case 0x22: + dev->idx = val; + break; + case 0x24: + opti5x7_log("OPTi 5x7: dev->regs[%02x] = %02x\n", dev->idx, val); + switch (dev->idx) + { + case 0x00: /* DRAM Configuration Register #1 */ + dev->regs[dev->idx] = val & 0x7f; + break; + case 0x01: /* DRAM Control Register #1 */ + dev->regs[dev->idx] = val; + break; + case 0x02: /* Cache Control Register #1 */ + dev->regs[dev->idx] = val; + cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x0c); + cpu_update_waitstates(); + break; + case 0x03: /* Cache Control Register #2 */ + dev->regs[dev->idx] = val; + break; + case 0x04: /* Shadow RAM Control Register #1 */ + case 0x05: /* Shadow RAM Control Register #2 */ + case 0x06: /* Shadow RAM Control Register #3 */ + dev->regs[dev->idx] = val; + shadow_map(dev); + break; + case 0x07: /* Tag Test Register */ + case 0x08: /* CPU Cache Control Register #1 */ + case 0x09: /* System Memory Function Register #1 */ + case 0x0a: /* System Memory Address Decode Register #1 */ + case 0x0b: /* System Memory Address Decode Register #2 */ + dev->regs[dev->idx] = val; + break; + case 0x0c: /* Extended DMA Register */ + dev->regs[dev->idx] = val & 0xcf; + break; + case 0x0d: /* ROMCS# Register */ + case 0x0e: /* Local Master Preemption Register */ + case 0x0f: /* Deturbo Control Register #1 */ + case 0x10: /* Cache Write-Hit Control Register */ + case 0x11: /* Master Cycle Control Register */ + dev->regs[dev->idx] = val; + break; + } + break; } } - static uint8_t opti5x7_read(uint16_t addr, void *priv) { - uint8_t ret = 0xff; - opti5x7_t *dev = (opti5x7_t *) priv; + opti5x7_t *dev = (opti5x7_t *)priv; - switch (addr) { - case 0x24: - opti5x7_log("Read from OPTi 5x7 register %02x\n", dev->idx); - ret = dev->regs[dev->idx]; - break; - } - - return ret; + return (addr == 0x24) ? dev->regs[dev->idx] : 0xff; } - static void opti5x7_close(void *priv) { - opti5x7_t *dev = (opti5x7_t *) priv; + opti5x7_t *dev = (opti5x7_t *)priv; free(dev); } - static void * opti5x7_init(const device_t *info) { - opti5x7_t *dev = (opti5x7_t *) malloc(sizeof(opti5x7_t)); + opti5x7_t *dev = (opti5x7_t *)malloc(sizeof(opti5x7_t)); memset(dev, 0, sizeof(opti5x7_t)); io_sethandler(0x0022, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev); io_sethandler(0x0024, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev); - dev->port_92 = device_add(&port_92_device); + device_add(&port_92_device); return dev; } @@ -170,7 +164,10 @@ const device_t opti5x7_device = { "OPTi 82C5x6/82C5x7", 0, 0, - opti5x7_init, opti5x7_close, NULL, - { NULL }, NULL, NULL, - NULL -}; + opti5x7_init, + opti5x7_close, + NULL, + {NULL}, + NULL, + NULL, + NULL};