From 8c6fc11bb216a5ef2521a1267f455d33c141df71 Mon Sep 17 00:00:00 2001
From: Cacodemon345 <wahil1976@outlook.com>
Date: Mon, 15 Jan 2024 00:05:48 +0600
Subject: [PATCH] Fix TSS trap-bit handling

---
 src/cpu/386_dynarec.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/cpu/386_dynarec.c b/src/cpu/386_dynarec.c
index 73441a346..dcdb3c151 100644
--- a/src/cpu/386_dynarec.c
+++ b/src/cpu/386_dynarec.c
@@ -268,7 +268,7 @@ exec386_dynarec_int(void)
     cpu_block_end = 0;
     x86_was_reset = 0;
 
-    if (trap == 2) {
+    if (trap & 2) {
         /* Handle the T bit in the new TSS first. */
         CPU_BLOCK_END();
         goto block_ended;
@@ -342,6 +342,7 @@ exec386_dynarec_int(void)
 
 block_ended:
     if (!cpu_state.abrt && trap) {
+        //pclog("Debug trap 0x%X\n", trap);
         if (trap & 2) dr[6] |= 0x8000;
         if (trap & 1) dr[6] |= 0x4000;