Fixed cycles accumulation in update_tsc() when cache is enabled (and the actual recompiler kicks in), and also fixed a warning in the 82091AA code.

src/codegen/codegen_accumulate_x86-64.c

@@ -20,6 +20,14 @@ static struct
 void codegen_accumulate(int acc_reg, int delta)
 {
         acc_regs[acc_reg].count += delta;
+
+	if (delta != 0) {
+		addbyte(0x81); /*ADD $acc_regs[c].count,acc_regs[c].dest*/
+		addbyte(0x04);
+		addbyte(0x25);
+		addlong((uint32_t) (uintptr_t) &(acycs));
+		addlong(delta);
+	}
 }
 
 void codegen_accumulate_flush(void)

src/codegen/codegen_accumulate_x86.c

@@ -14,12 +14,19 @@ static struct
 } acc_regs[] =
 {
         [ACCREG_ins]    = {0, (uintptr_t) &(ins)},
-        [ACCREG_cycles] = {0, (uintptr_t) &(cycles)},
+        [ACCREG_cycles] = {0, (uintptr_t) &(cycles)}
 };
 
 void codegen_accumulate(int acc_reg, int delta)
 {
         acc_regs[acc_reg].count += delta;
+
+	if (delta != 0) {
+		addbyte(0x81); /*ADD $acc_regs[c].count,acc_regs[c].dest*/
+		addbyte(0x05);
+		addlong((uint32_t) (uintptr_t) &(acycs));
+		addlong((uintptr_t) delta);
+	}
 }
 
 void codegen_accumulate_flush(void)
@@ -38,6 +45,8 @@ void codegen_accumulate_flush(void)
 
                 acc_regs[c].count = 0;
         }
+
+	acycs = 0;
 }
 
 void codegen_accumulate_reset()

src/codegen_new/codegen_accumulate.c

@@ -20,6 +20,10 @@ static struct
 void codegen_accumulate(int acc_reg, int delta)
 {
         acc_regs[acc_reg].count += delta;
+
+	if (delta != 0) {
+		uop_ADD_IMM(ir, IREG_acycs, IREG_acycs, delta);
+	}
 }
 
 void codegen_accumulate_flush(ir_data_t *ir)

src/codegen_new/codegen_reg.c

@@ -180,6 +180,8 @@ struct
 	
 	[IREG_temp0d] = {REG_DOUBLE, (void *)40, REG_FP, REG_VOLATILE},
 	[IREG_temp1d] = {REG_DOUBLE, (void *)48, REG_FP, REG_VOLATILE},
+
+	[IREG_acycs]  = {REG_DWORD, &acycs,        	       REG_INTEGER, REG_PERMANENT}
 };
 
 void codegen_reg_mark_as_required()

src/codegen_new/codegen_reg.h

@@ -133,7 +133,9 @@ enum
         IREG_GS_limit_high = 86,
         IREG_SS_limit_high = 87,
 
-	IREG_COUNT = 88,
+	IREG_acycs = 88,
+
+	IREG_COUNT = 89,
 	
 	IREG_INVALID = 255,
 	

src/cpu/386_dynarec.c

@@ -276,12 +276,17 @@ static void prefetch_flush()
 static int cycles_main = 0, cycles_old = 0;
 static uint64_t tsc_old = 0;
 
+int acycs = 0;
+
 void update_tsc(void)
 {
     int cycdiff;
     uint64_t delta;
 
-    cycdiff = cycles_old - cycles;
+    if (CACHE_ON())
+	cycdiff = acycs;
+    else
+	cycdiff = cycles_old - cycles;
     delta = tsc - tsc_old;
     if (delta > 0) {
 	/* TSC has changed, this means interim timer processing has happened,

src/cpu/cpu.c

@@ -362,6 +362,8 @@ cpu_set(void)
 	cpu_effective = cpu;
         cpu_s = &machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective];
 
+	acycs = 0;
+
 	cpu_alt_reset = 0;
 	unmask_a20_in_smm = 0;
 

src/cpu/cpu.h

@@ -503,6 +503,8 @@ extern int	timing_misaligned;
 extern int	in_sys, unmask_a20_in_smm;
 extern uint32_t	old_rammask;
 
+extern int	acycs;
+
 extern uint16_t	cpu_fast_off_count, cpu_fast_off_val;
 extern uint32_t	cpu_fast_off_flags;
 

src/sio/sio_82091aa.c

@@ -147,6 +147,8 @@ i82091aa_write(uint16_t port, uint8_t val, void *priv)
 	return;
     } else if (dev->cur_reg < 0x51)
 	valxor = val ^ *reg;
+    else if (dev->cur_reg >= 0x51)
+	return;
 
     switch(dev->cur_reg) {
 	case 0x02: