A slight reorganization of the source tree and fixed a warning in disk/mo.c.
This commit is contained in:
OBattler
485
src/sio/sio_acc3221.c
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485
src/sio/sio_acc3221.c
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@@ -0,0 +1,485 @@
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the ACC 3221-SP Super I/O Chip.
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*
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*
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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*
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* Copyright 2019 Sarah Walker.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/io.h>
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#include <86box/timer.h>
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#include <86box/device.h>
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#include <86box/pci.h>
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#include <86box/lpt.h>
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#include <86box/serial.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/sio.h>
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typedef struct acc3221_t
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{
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int reg_idx;
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uint8_t regs[256];
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fdc_t * fdc;
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serial_t * uart[2];
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} acc3221_t;
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/* Configuration Register Index, BE (R/W):
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Bit Function
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7 PIRQ 5 polarity.
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1 = active high, default
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0 = active low
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6 PIRQ 7 polarity.
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1 = active high, default
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0 = active low
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5 Primary Parallel Port Extended Mode
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0 = Compatible mode, default
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1 = Extended/Bidirectional mode.
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4 Primary Parallel Port Disable
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1 = Disable, 0 = Enable
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Power Up Default is set by pin 120
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(3221-DP)/pin 96 (3221-SP)
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3 Primary Parallel Port Power Down
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1 = Power Down, default = 0
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2** Secondary Parallel Port Extended
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Mode
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0 = Compatible mode, default
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1 = Extended/Bidirectional mode.
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1** Secondary Parallel Port Disable
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1 = Disable, 0 = Enable
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Power Up Default is set by pin 77
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(3221-DP)
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0** Secondary Parallel Port Power Down
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1 = Power Down
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0 = Enable, default
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Note: Power Up not applicable to 3221-EP. */
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#define REG_BE_LPT1_DISABLE (3 << 3)
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#define REG_BE_LPT2_DISABLE (3 << 0) /* 3221-DP/EP only */
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/* Configuration Register Index, BF (R/W):
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Bit Function
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7-0 The 8 most significant address bits of
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the primary parallel port (A9-2)
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Default 9E (LPT2, at 278-27B) */
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/* Configuration Register Index, DA (R/W)**:
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Bit Function
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7-0 The 8 most significant address bits of
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the secondary parallel port (A9-2)
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Default DE (LPT1, at 378-37B) */
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/* Configuration Register Index, DB (R/W):
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Bit Function
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7 SIRQ4 polarity.
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1 = active high; default
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0 = active low
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6 SIRQ3 polarity.
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1 = active high; default
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0 = active low
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5 SXTAL clock off. 1 = SCLK off,
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0 = SCKL on, default
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4 Primary serial port disable
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1 = Disable, 0 = Enable
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Power Up default is set by pin 116
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(3221-DP)/pin 93 (3221-SP)
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3 Primary serial port power down
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1 = Power down, 0 = Enable
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Power Up default is set by pin 116
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(3221-DP)/pin 93 (3221-SP)
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2 Reserved
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1 Secondary serial port disable
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1 = Disable, 0 = Enable
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Power Up default is set by pin 121
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(3221-DP)/pin 97 (3221-SP)
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0 Secondary serial port power down
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1 = Power down, 0 = Enable
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Power Up default is set by pin 121
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(3221-DP)/pin 97 (3221-SP)
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Note: Power Up not applicable to 3221-EP. */
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#define REG_DB_SERIAL1_DISABLE (3 << 3)
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#define REG_DB_SERIAL2_DISABLE (3 << 0)
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/* Configuration Register Index, DC (R/W):
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Bit Function
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7-1 The MSB of the Primary Serial Port
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Address (bits A9-3).
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Default = 7F (COM1, at 3F8-3FF).
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0 When this bit is set to 1, bit A2 of
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primary parallel port is decoded.
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Default is 0. */
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/* Configuration Register Index, DD (R/W):
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Bit Function
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7-1 The MSB of the Secondary Serial Port
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Address (bits A9-3).
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Default = 5F (COM2, at 2F8-2FF).
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0** When this bit is set to 1, bit A2 of
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secondary parallel port is decoded.
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Default is 0. */
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/* Configuration Register Index, DE (R/W):
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Bit Function
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7-6 SIRQ3 source
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b7 b6
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0 0 Disabled, tri-stated
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0 1 Disabled, tri-stated**
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1 0 Primary serial port
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1 1 Secondary serial port,
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default
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5-4 SIRQ4 source
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b5 b4
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0 0 Disabled, tri-stated
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0 1 Disabled, tri-stated**
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1 0 Primary serial port,
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default
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1 1 Secondary serial port
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3-2** PIRQ7 source
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b3 b2
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0 0 Diabled, tri-stated,
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default
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0 1 Primary serial port
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1 0 Primary parallel port
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1 1 Secondary parallel
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port
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Note: Bits 3-2 are reserved in 3221-SP.
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1-0 PIRQ5 source
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b1 b0
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0 0 Disabled, tri-stated
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0 1 Secondary serial port
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1 0 Primary parallel port,
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default
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1 1 Secondary parallel
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port** */
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#define REG_DE_SIRQ3_SOURCE (3 << 6)
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#define REG_DE_SIRQ3_SERIAL1 (1 << 6)
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#define REG_DE_SIRQ3_SERIAL2 (3 << 6)
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#define REG_DE_SIRQ4_SOURCE (3 << 4)
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#define REG_DE_SIRQ4_SERIAL1 (1 << 4)
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#define REG_DE_SIRQ4_SERIAL2 (3 << 4)
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#define REG_DE_PIRQ7_SOURCE (3 << 2)
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#define REG_DE_PIRQ7_SERIAL1 (1 << 2)
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#define REG_DE_PIRQ7_LPT1 (2 << 2)
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#define REG_DE_PIRQ7_LPT2 (3 << 2)
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#define REG_DE_PIRQ5_SOURCE (3 << 0)
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#define REG_DE_PIRQ5_SERIAL2 (1 << 0)
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#define REG_DE_PIRQ5_LPT1 (2 << 0)
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#define REG_DE_PIRQ5_LPT2 (3 << 0)
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/* Configuration Register Index, DF (R/W)**:
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Bit Function
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7-6 Reserved
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5 RTC interface disable
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1 = /RTCCS disabled
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0 = /RTCCS enabled, default
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4 Disable Modem Select
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1 = Moden CS disabled, default
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0 = Modem CS enabled
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3-2
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b3 b2
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1 1 Reserved
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1 0 Modem port address
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= 3E8-3EF (default)
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0 1 Modem port address:
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2F8-2FF
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0 0 Modem port address:
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3F8-3FF
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1-0
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b1 b0
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1 1 Reserved
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1 0 Mode 2, EISA Mode
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0 1 Mode 1, AT BUS,
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0 0 Mode 0, Two parallel
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ports, default */
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/* Configuration Register Index, FA (R/W)**:
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Bit Function
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7 General purpose I/O register, Bit 7
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6 General purpose I/O register, Bit 6
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5 General purpose I/O register, Bit 5
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4 General purpose I/O register, Bit 4
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3 General purpose I/O register, Bit 3
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2 General purpose I/O register, Bit 2
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1 General purpose I/O register, Bit 1
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0 General purpose I/O register, Bit 0 */
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/* Configuration Register Index, FB (R/W)**:
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Bit Function
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7 Reserved
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6** 0/2 EXG (Read Only)
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In mode 1 and mode 2
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operation, when the third
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floppy drive is installed, pin
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EXTFDD should be pulled
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high to enable the third floppy
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drive or be pulled low to
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disable the third floppy drive.
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1 = Third floppy drive enabled
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0 = Third floppy drive disabled
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5** EXTFDD (Read Only)
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In mode 1 and mode 2
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operation, when the third
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floppy drive is installed and
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pin 0/2 EXG is pulled high,
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the third floppy drive becomes
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the bootable drive (drive 0).
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When pi 0/2 EXG is pulled low,
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the third floppy drive acts as
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drive 2.
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1 = Third floppy drive as drive 0 (bootable)
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0 = Third floppy drive as drive 2
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4** MS
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In mode 1 and mode 2, t his bit is to
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control the output pin MS to support a
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special 3 1/2", 1.2M drive. When this
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bit is set to high (1), the MS pin sends
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a low signal. When this bit is set to
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low (0), the MS pin sends a high
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signal to support a 3 1/2", 1.2M drive.
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3 FDC, Clock disable
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0 = enable, default
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1 = disable
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2 Reserved
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1 FDC disable
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0 = enable, 1= disable
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Power Upd efault set by pin 117 (3221-
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DP)/pin 94 (3221-SP)
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0 FDC address
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0 = Primary, default
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1 = Secondary
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Note: Bits 6-4 are reserved in 3221-SP. */
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#define REG_FB_FDC_DISABLE (1 << 1)
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/* Configuration Register Index, FB (R/W)**:
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Bit Function
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7** Disable general chip select 1
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1 = disable, default
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0 = enable
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6** Disable general chip select 2
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1 = disable, default
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0 = enable
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5** Enable SA2 decoding for general chip
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select 1
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1 = enable
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0 = disable, default
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4** Enable SA2 decoding for general chip
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select 2
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1 = enable
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0 = disable, default
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3 Reserved
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2 IDE XT selected
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0 = IDE AT interface, default
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1 = IDE XT interface
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1 IDE disable, 1 = IDE disable
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0 = IDE enable
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Power Up default set by pin 13 (3221-
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DP)/pin 13 (3221-SP)
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0 Secondary IDE
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1 = secondary
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0 = primary, default
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Note: Bits 6-4 are reserved in 3221-SP. */
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#define REG_FE_IDE_DISABLE (1 << 1)
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static void
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acc3221_lpt_handle(acc3221_t *dev)
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{
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lpt1_remove();
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if (!(dev->regs[0xbe] & REG_BE_LPT1_DISABLE))
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lpt1_init(dev->regs[0xbf] << 2);
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}
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static void
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acc3221_serial1_handler(acc3221_t *dev)
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{
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uint16_t com_addr = 0;
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serial_remove(dev->uart[0]);
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if (!(dev->regs[0xdb] & REG_DB_SERIAL1_DISABLE)) {
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com_addr = ((dev->regs[0xdc] & 0xfe) << 2);
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if ((dev->regs[0xde] & REG_DE_SIRQ3_SOURCE) == REG_DE_SIRQ3_SERIAL1)
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serial_setup(dev->uart[0], com_addr, 3);
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else if ((dev->regs[0xde] & REG_DE_SIRQ4_SOURCE) == REG_DE_SIRQ4_SERIAL1)
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serial_setup(dev->uart[0], com_addr, 4);
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}
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}
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static void
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acc3221_serial2_handler(acc3221_t *dev)
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{
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uint16_t com_addr = 0;
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serial_remove(dev->uart[1]);
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if (!(dev->regs[0xdb] & REG_DB_SERIAL2_DISABLE)) {
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com_addr = ((dev->regs[0xdd] & 0xfe) << 2);
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if ((dev->regs[0xde] & REG_DE_SIRQ3_SOURCE) == REG_DE_SIRQ3_SERIAL2)
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serial_setup(dev->uart[1], com_addr, 3);
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else if ((dev->regs[0xde] & REG_DE_SIRQ4_SOURCE) == REG_DE_SIRQ4_SERIAL2)
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serial_setup(dev->uart[1], com_addr, 4);
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else if ((dev->regs[0xde] & REG_DE_PIRQ5_SOURCE) == REG_DE_PIRQ5_SERIAL2)
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serial_setup(dev->uart[1], com_addr, 5);
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}
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}
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static void
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acc3221_write(uint16_t addr, uint8_t val, void *p)
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{
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acc3221_t *dev = (acc3221_t *)p;
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uint8_t old;
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if (!(addr & 1))
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dev->reg_idx = val;
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else {
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old = dev->regs[dev->reg_idx];
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dev->regs[dev->reg_idx] = val;
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switch (dev->reg_idx) {
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case 0xbe:
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if ((old ^ val) & REG_BE_LPT1_DISABLE)
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acc3221_lpt_handle(dev);
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break;
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case 0xbf:
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if (old != val)
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acc3221_lpt_handle(dev);
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break;
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case 0xdb:
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if ((old ^ val) & REG_DB_SERIAL2_DISABLE)
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acc3221_serial2_handler(dev);
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if ((old ^ val) & REG_DB_SERIAL1_DISABLE)
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acc3221_serial1_handler(dev);
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break;
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case 0xdc:
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if (old != val)
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acc3221_serial1_handler(dev);
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break;
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case 0xdd:
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if (old != val)
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acc3221_serial2_handler(dev);
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break;
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case 0xde:
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if ((old ^ val) & (REG_DE_SIRQ3_SOURCE | REG_DE_SIRQ4_SOURCE)) {
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acc3221_serial2_handler(dev);
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acc3221_serial1_handler(dev);
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}
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break;
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case 0xfb:
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if ((old ^ val) & REG_FB_FDC_DISABLE) {
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fdc_remove(dev->fdc);
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if (!(dev->regs[0xfb] & REG_FB_FDC_DISABLE))
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fdc_set_base(dev->fdc, 0x03f0);
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}
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break;
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case 0xfe:
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if ((old ^ val) & REG_FE_IDE_DISABLE) {
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ide_pri_disable();
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if (!(dev->regs[0xfe] & REG_FE_IDE_DISABLE))
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ide_pri_enable();
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}
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break;
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}
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}
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}
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static uint8_t
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acc3221_read(uint16_t addr, void *p)
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{
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acc3221_t *dev = (acc3221_t *)p;
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if (!(addr & 1))
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return dev->reg_idx;
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if (dev->reg_idx < 0xbc)
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return 0xff;
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return dev->regs[dev->reg_idx];
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}
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static void
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acc3221_reset(acc3221_t *dev)
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{
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serial_remove(dev->uart[0]);
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serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ);
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serial_remove(dev->uart[1]);
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serial_setup(dev->uart[1], SERIAL2_ADDR, SERIAL2_IRQ);
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lpt1_remove();
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lpt1_init(0x378);
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lpt1_irq(7);
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fdc_reset(dev->fdc);
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}
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static void
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acc3221_close(void *priv)
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{
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acc3221_t *dev = (acc3221_t *) priv;
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free(dev);
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}
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static void *
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acc3221_init(const device_t *info)
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{
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acc3221_t *dev = (acc3221_t *) malloc(sizeof(acc3221_t));
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memset(dev, 0, sizeof(acc3221_t));
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dev->fdc = device_add(&fdc_at_device);
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dev->uart[0] = device_add_inst(&ns16450_device, 1);
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dev->uart[1] = device_add_inst(&ns16450_device, 2);
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io_sethandler(0x00f2, 0x0002, acc3221_read, NULL, NULL, acc3221_write, NULL, NULL, dev);
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acc3221_reset(dev);
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return dev;
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}
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const device_t acc3221_device = {
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"ACC 3221-SP Super I/O",
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0,
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0,
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acc3221_init, acc3221_close, NULL,
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NULL, NULL, NULL,
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NULL
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};
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