From 9cce85008abfe770937e0eacd4b71198bc9be6a2 Mon Sep 17 00:00:00 2001 From: TC1995 Date: Tue, 31 Mar 2020 00:46:47 +0200 Subject: [PATCH] Reworked the CS8230 chipset using the 86box device model. --- src/chipset/cs8230.c | 150 +++++++++++++++++++++++-------------------- 1 file changed, 80 insertions(+), 70 deletions(-) diff --git a/src/chipset/cs8230.c b/src/chipset/cs8230.c index 04f7817e4..bb13b353e 100644 --- a/src/chipset/cs8230.c +++ b/src/chipset/cs8230.c @@ -30,17 +30,16 @@ #include <86box/chipset.h> -static struct +typedef struct { - int idx; - uint8_t regs[256]; -} cs8230; + int idx; + uint8_t regs[256]; +} cs8230_t; -static void shadow_control(uint32_t addr, uint32_t size, int state) +static void +shadow_control(uint32_t addr, uint32_t size, int state) { -// pclog("shadow_control: addr=%08x size=%04x state=%02x\n", addr, size, state); - switch (state) - { + switch (state) { case 0x00: mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); break; @@ -58,88 +57,99 @@ static void shadow_control(uint32_t addr, uint32_t size, int state) } -static void rethink_shadow_mappings(void) +static void +rethink_shadow_mappings(cs8230_t *cs8230) { - int c; - - for (c = 0; c < 4*8; c++) /*Addresses 40000-bffff in 16k blocks*/ - { - if (cs8230.regs[0xa + (c >> 3)] & (1 << (c & 7))) - mem_set_mem_state(0x40000 + c*0x4000, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); /*IO channel*/ - else - mem_set_mem_state(0x40000 + c*0x4000, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); /*System board*/ - } - for (c = 0; c < 2*8; c++) /*Addresses c0000-fffff in 16k blocks. System board ROM can be mapped here*/ - { - if (cs8230.regs[0xe + (c >> 3)] & (1 << (c & 7))) - mem_set_mem_state(0xc0000 + c*0x4000, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); /*IO channel*/ - else - shadow_control(0xc0000 + c*0x4000, 0x4000, (cs8230.regs[9] >> (3-(c >> 2))) & 0x11); - } + int c; + + for (c = 0; c < 4*8; c++) { /*Addresses 40000-bffff in 16k blocks*/ + if (cs8230->regs[0xa + (c >> 3)] & (1 << (c & 7))) + mem_set_mem_state(0x40000 + c*0x4000, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); /*IO channel*/ + else + mem_set_mem_state(0x40000 + c*0x4000, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); /*System board*/ + } + for (c = 0; c < 2*8; c++) { /*Addresses c0000-fffff in 16k blocks. System board ROM can be mapped here*/ + if (cs8230->regs[0xe + (c >> 3)] & (1 << (c & 7))) + mem_set_mem_state(0xc0000 + c*0x4000, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); /*IO channel*/ + else + shadow_control(0xc0000 + c*0x4000, 0x4000, (cs8230->regs[9] >> (3-(c >> 2))) & 0x11); + } } -static uint8_t cs8230_read(uint16_t port, void *p) +static uint8_t +cs8230_read(uint16_t port, void *p) { + cs8230_t *cs8230 = (cs8230_t *)p; uint8_t ret = 0xff; - - if (port & 1) - { - switch (cs8230.idx) - { - case 0x04: /*82C301 ID/version*/ - ret = cs8230.regs[cs8230.idx] & ~0xe3; - break; + + if (port & 1) { + switch (cs8230->idx) { + case 0x04: /*82C301 ID/version*/ + ret = cs8230->regs[cs8230->idx] & ~0xe3; + break; case 0x08: /*82C302 ID/Version*/ - ret = cs8230.regs[cs8230.idx] & ~0xe0; - break; + ret = cs8230->regs[cs8230->idx] & ~0xe0; + break; - case 0x05: case 0x06: /*82C301 registers*/ - case 0x09: case 0x0a: case 0x0b: case 0x0c: /*82C302 registers*/ - case 0x0d: case 0x0e: case 0x0f: - case 0x10: case 0x11: case 0x12: case 0x13: - case 0x28: case 0x29: case 0x2a: - ret = cs8230.regs[cs8230.idx]; - break; - } - } - - return ret; + case 0x05: case 0x06: /*82C301 registers*/ + case 0x09: case 0x0a: case 0x0b: case 0x0c: /*82C302 registers*/ + case 0x0d: case 0x0e: case 0x0f: + case 0x10: case 0x11: case 0x12: case 0x13: + case 0x28: case 0x29: case 0x2a: + ret = cs8230->regs[cs8230->idx]; + break; + } + } + + return ret; } -static void cs8230_write(uint16_t port, uint8_t val, void *p) +static void +cs8230_write(uint16_t port, uint8_t val, void *p) { - if (!(port & 1)) - cs8230.idx = val; - else - { -// pclog("cs8230_write: reg=%02x val=%02x\n", cs8230.idx, val); - cs8230.regs[cs8230.idx] = val; - switch (cs8230.idx) - { - case 0x09: /*RAM/ROM Configuration in boot area*/ - case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: /*Address maps*/ -// rethink_shadow_mappings(); - break; - } - } + cs8230_t *cs8230 = (cs8230_t *)p; + + if (!(port & 1)) + cs8230->idx = val; + else { + cs8230->regs[cs8230->idx] = val; + switch (cs8230->idx) { + case 0x09: /*RAM/ROM Configuration in boot area*/ + case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: /*Address maps*/ + rethink_shadow_mappings(cs8230); + break; + } + } } -static void * cs8230_init(const device_t *info) +static void +cs8230_close(void *priv) { - memset(&cs8230, 0, sizeof(cs8230)); - - io_sethandler(0x0022, 0x0002, - cs8230_read, NULL, NULL, - cs8230_write, NULL, NULL, - NULL); + cs8230_t *cs8230 = (cs8230_t *)priv; + + free(cs8230); +} + +static void +*cs8230_init(const device_t *info) +{ + cs8230_t *cs8230 = (cs8230_t *)malloc(sizeof(cs8230_t)); + memset(cs8230, 0, sizeof(cs8230_t)); + + io_sethandler(0x0022, 0x0002, + cs8230_read, NULL, NULL, + cs8230_write, NULL, NULL, + cs8230); + + return cs8230; } const device_t cs8230_device = { "C&T CS8230 (386/AT)", 0, 0, - cs8230_init, NULL, NULL, + cs8230_init, cs8230_close, NULL, NULL, NULL, NULL, NULL }; \ No newline at end of file