From ee315970a1bfaa978b095f84905b5dc5d49ea957 Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 9 Aug 2021 07:19:12 +0200 Subject: [PATCH 1/5] Correct implementation of the VIA write-only NVR register 0D bit that is read from power management PCI register 42, fixes the FIC VA-503A. --- src/chipset/via_pipc.c | 5 ++--- src/nvr_at.c | 5 +++++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/chipset/via_pipc.c b/src/chipset/via_pipc.c index f62775dc7..5b86c8d59 100644 --- a/src/chipset/via_pipc.c +++ b/src/chipset/via_pipc.c @@ -1122,9 +1122,8 @@ pipc_write(int func, int addr, uint8_t val, void *priv) break; case 0x42: - dev->power_regs[addr] &= ~0x2f; - dev->power_regs[addr] |= val & 0x2f; - acpi_set_irq_line(dev->acpi, dev->power_regs[addr]); + dev->power_regs[addr] = (dev->power_regs[addr] & 0xf0) | (val & 0x0f); + acpi_set_irq_line(dev->acpi, dev->power_regs[addr] & 0x0f); break; case 0x54: diff --git a/src/nvr_at.c b/src/nvr_at.c index bf188dbbf..ff1c6fcb0 100644 --- a/src/nvr_at.c +++ b/src/nvr_at.c @@ -589,6 +589,9 @@ nvr_reg_write(uint16_t reg, uint8_t val, void *priv) break; case RTC_REGD: /* R/O */ + /* This is needed for VIA, where writing to this register changes a write-only + bit whose value is read from power management register 42. */ + nvr->regs[RTC_REGD] = val & 0x80; break; case 0x2e: @@ -796,6 +799,8 @@ nvr_reset(nvr_t *nvr) nvr->regs[RTC_YEAR] = RTC_BCD(80); if (local->cent != 0xFF) nvr->regs[local->cent] = RTC_BCD(19); + + nvr->regs[RTC_REGD] = REGD_VRT; } /* Process after loading from file. */ From 7190a776aea3706291ca62db4535778bdaf0d5ba Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 9 Aug 2021 07:52:57 +0200 Subject: [PATCH 2/5] Some AT KBC fixes, fixes the QDI Excellent II. --- src/device/keyboard_at.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/device/keyboard_at.c b/src/device/keyboard_at.c index 581f55f30..1c44880a3 100644 --- a/src/device/keyboard_at.c +++ b/src/device/keyboard_at.c @@ -1118,12 +1118,15 @@ write_cmd(atkbd_t *dev, uint8_t val) if ((kbc_ven == KBC_VEN_AMI) || ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_NOREF)) { keyboard_mode &= ~CCB_PCMODE; - /* Update the output port to mirror the KBD DIS and AUX DIS bits, if active. */ - write_output(dev, dev->output_port); kbd_log("ATkbc: mouse interrupt is now %s\n", (val & 0x02) ? "enabled" : "disabled"); } + if ((kbc_ven == KBC_VEN_AMI) || ((dev->flags & KBC_TYPE_MASK) < KBC_TYPE_PS2_NOREF)) { + /* Update the output port to mirror the KBD DIS and AUX DIS bits, if active. */ + write_output(dev, dev->output_port); + } + kbd_log("Command byte now: %02X (%02X)\n", dev->mem[0], val); dev->status = (dev->status & ~STAT_SYSFLAG) | (val & STAT_SYSFLAG); @@ -1740,7 +1743,7 @@ kbd_write(uint16_t port, uint8_t val, void *priv) case 0xd2: /* write to keyboard output buffer */ kbd_log("ATkbc: write to keyboard output buffer\n"); - add_data_kbd_direct(dev, val); + add_to_kbc_queue_front(dev, val, 0, 0x00); break; case 0xd3: /* write to mouse output buffer */ From 0d5c5f361a60369ad09e8da7d81beb6034e6474f Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 9 Aug 2021 09:51:58 +0200 Subject: [PATCH 3/5] Added a separate CPU_STPC CPU type with RDTSC, fixes the ITOX STAR. --- src/cpu/386_ops.h | 91 +++++++++++++++++++++++++++++++++++++++++++++ src/cpu/cpu.c | 14 ++++++- src/cpu/cpu.h | 1 + src/cpu/cpu_table.c | 6 +-- src/cpu/x86_ops.h | 2 + 5 files changed, 109 insertions(+), 5 deletions(-) diff --git a/src/cpu/386_ops.h b/src/cpu/386_ops.h index bc6f56324..5b472298b 100644 --- a/src/cpu/386_ops.h +++ b/src/cpu/386_ops.h @@ -725,6 +725,97 @@ const OpFn OP_TABLE(c486_0f)[1024] = /*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, }; +const OpFn OP_TABLE(stpc_0f)[1024] = +{ + /*16-bit data, 16-bit addr*/ +/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/ +/*00*/ op0F00_a16, op0F01_w_a16, opLAR_w_a16, opLSL_w_a16, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*30*/ ILLEGAL, opRDTSC, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a16, opWRSHR_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, + +/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSVDC_a16, opRSDC_a16, opSVLDT_a16, opRSLDT_a16, opSVTS_a16, opRSTS_a16, opSMINT, ILLEGAL, + +/*80*/ opJO_w, opJNO_w, opJB_w, opJNB_w, opJE_w, opJNE_w, opJBE_w, opJNBE_w, opJS_w, opJNS_w, opJP_w, opJNP_w, opJL_w, opJNL_w, opJLE_w, opJNLE_w, +/*90*/ opSETO_a16, opSETNO_a16, opSETB_a16, opSETNB_a16, opSETE_a16, opSETNE_a16, opSETBE_a16, opSETNBE_a16, opSETS_a16, opSETNS_a16, opSETP_a16, opSETNP_a16, opSETL_a16, opSETNL_a16, opSETLE_a16, opSETNLE_a16, +/*a0*/ opPUSH_FS_w, opPOP_FS_w, opCPUID, opBT_w_r_a16, opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL, ILLEGAL, opPUSH_GS_w, opPOP_GS_w, opRSM, opBTS_w_r_a16, opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL, opIMUL_w_w_a16, +/*b0*/ opCMPXCHG_b_a16,opCMPXCHG_w_a16,opLSS_w_a16, opBTR_w_r_a16, opLFS_w_a16, opLGS_w_a16, opMOVZX_w_b_a16,opMOVZX_w_w_a16,ILLEGAL, ILLEGAL, opBA_w_a16, opBTC_w_r_a16, opBSF_w_a16, opBSR_w_a16, opMOVSX_w_b_a16,ILLEGAL, + +/*c0*/ opXADD_b_a16, opXADD_w_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opBSWAP_EAX, opBSWAP_ECX, opBSWAP_EDX, opBSWAP_EBX, opBSWAP_ESP, opBSWAP_EBP, opBSWAP_ESI, opBSWAP_EDI, +/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, + + /*32-bit data, 16-bit addr*/ +/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/ +/*00*/ op0F00_a16, op0F01_l_a16, opLAR_l_a16, opLSL_l_a16, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*30*/ ILLEGAL, opRDTSC, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a16, opWRSHR_a16, opSVDC_a16, opRSDC_a16, opSVLDT_a16, opRSLDT_a16, opSVTS_a16, opRSTS_a16, opSMINT, ILLEGAL, + +/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, + +/*80*/ opJO_l, opJNO_l, opJB_l, opJNB_l, opJE_l, opJNE_l, opJBE_l, opJNBE_l, opJS_l, opJNS_l, opJP_l, opJNP_l, opJL_l, opJNL_l, opJLE_l, opJNLE_l, +/*90*/ opSETO_a16, opSETNO_a16, opSETB_a16, opSETNB_a16, opSETE_a16, opSETNE_a16, opSETBE_a16, opSETNBE_a16, opSETS_a16, opSETNS_a16, opSETP_a16, opSETNP_a16, opSETL_a16, opSETNL_a16, opSETLE_a16, opSETNLE_a16, +/*a0*/ opPUSH_FS_l, opPOP_FS_l, opCPUID, opBT_l_r_a16, opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL, ILLEGAL, opPUSH_GS_l, opPOP_GS_l, opRSM, opBTS_l_r_a16, opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL, opIMUL_l_l_a16, +/*b0*/ opCMPXCHG_b_a16,opCMPXCHG_l_a16,opLSS_l_a16, opBTR_l_r_a16, opLFS_l_a16, opLGS_l_a16, opMOVZX_l_b_a16,opMOVZX_l_w_a16,ILLEGAL, ILLEGAL, opBA_l_a16, opBTC_l_r_a16, opBSF_l_a16, opBSR_l_a16, opMOVSX_l_b_a16,opMOVSX_l_w_a16, + +/*c0*/ opXADD_b_a16, opXADD_l_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opBSWAP_EAX, opBSWAP_ECX, opBSWAP_EDX, opBSWAP_EBX, opBSWAP_ESP, opBSWAP_EBP, opBSWAP_ESI, opBSWAP_EDI, +/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, + + /*16-bit data, 32-bit addr*/ +/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/ +/*00*/ op0F00_a32, op0F01_w_a32, opLAR_w_a32, opLSL_w_a32, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*30*/ ILLEGAL, opRDTSC, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a32, opWRSHR_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, + +/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSVDC_a32, opRSDC_a32, opSVLDT_a32, opRSLDT_a32, opSVTS_a32, opRSTS_a32, opSMINT, ILLEGAL, + +/*80*/ opJO_w, opJNO_w, opJB_w, opJNB_w, opJE_w, opJNE_w, opJBE_w, opJNBE_w, opJS_w, opJNS_w, opJP_w, opJNP_w, opJL_w, opJNL_w, opJLE_w, opJNLE_w, +/*90*/ opSETO_a32, opSETNO_a32, opSETB_a32, opSETNB_a32, opSETE_a32, opSETNE_a32, opSETBE_a32, opSETNBE_a32, opSETS_a32, opSETNS_a32, opSETP_a32, opSETNP_a32, opSETL_a32, opSETNL_a32, opSETLE_a32, opSETNLE_a32, +/*a0*/ opPUSH_FS_w, opPOP_FS_w, opCPUID, opBT_w_r_a32, opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL, ILLEGAL, opPUSH_GS_w, opPOP_GS_w, opRSM, opBTS_w_r_a32, opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL, opIMUL_w_w_a32, +/*b0*/ opCMPXCHG_b_a32,opCMPXCHG_w_a32,opLSS_w_a32, opBTR_w_r_a32, opLFS_w_a32, opLGS_w_a32, opMOVZX_w_b_a32,opMOVZX_w_w_a32,ILLEGAL, ILLEGAL, opBA_w_a32, opBTC_w_r_a32, opBSF_w_a32, opBSR_w_a32, opMOVSX_w_b_a32,ILLEGAL, + +/*c0*/ opXADD_b_a32, opXADD_w_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opBSWAP_EAX, opBSWAP_ECX, opBSWAP_EDX, opBSWAP_EBX, opBSWAP_ESP, opBSWAP_EBP, opBSWAP_ESI, opBSWAP_EDI, +/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, + + /*32-bit data, 32-bit addr*/ +/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/ +/*00*/ op0F00_a32, op0F01_l_a32, opLAR_l_a32, opLSL_l_a32, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*30*/ ILLEGAL, opRDTSC, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a32, opWRSHR_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, + +/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSVDC_a16, opRSDC_a16, opSVLDT_a16, opRSLDT_a16, opSVTS_a16, opRSTS_a16, opSMINT, ILLEGAL, + +/*80*/ opJO_l, opJNO_l, opJB_l, opJNB_l, opJE_l, opJNE_l, opJBE_l, opJNBE_l, opJS_l, opJNS_l, opJP_l, opJNP_l, opJL_l, opJNL_l, opJLE_l, opJNLE_l, +/*90*/ opSETO_a32, opSETNO_a32, opSETB_a32, opSETNB_a32, opSETE_a32, opSETNE_a32, opSETBE_a32, opSETNBE_a32, opSETS_a32, opSETNS_a32, opSETP_a32, opSETNP_a32, opSETL_a32, opSETNL_a32, opSETLE_a32, opSETNLE_a32, +/*a0*/ opPUSH_FS_l, opPOP_FS_l, opCPUID, opBT_l_r_a32, opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL, ILLEGAL, opPUSH_GS_l, opPOP_GS_l, opRSM, opBTS_l_r_a32, opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL, opIMUL_l_l_a32, +/*b0*/ opCMPXCHG_b_a32,opCMPXCHG_l_a32,opLSS_l_a32, opBTR_l_r_a32, opLFS_l_a32, opLGS_l_a32, opMOVZX_l_b_a32,opMOVZX_l_w_a32,ILLEGAL, ILLEGAL, opBA_l_a32, opBTC_l_r_a32, opBSF_l_a32, opBSR_l_a32, opMOVSX_l_b_a32,opMOVSX_l_w_a32, + +/*c0*/ opXADD_b_a32, opXADD_l_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opBSWAP_EAX, opBSWAP_ECX, opBSWAP_EDX, opBSWAP_EBX, opBSWAP_ESP, opBSWAP_EBP, opBSWAP_ESI, opBSWAP_EDI, +/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, +}; + const OpFn OP_TABLE(ibm486_0f)[1024] = { /*16-bit data, 16-bit addr*/ diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c index 290c14a86..b8709254a 100644 --- a/src/cpu/cpu.c +++ b/src/cpu/cpu.c @@ -809,10 +809,17 @@ cpu_set(void) case CPU_Cx486S: case CPU_Cx486DX: + case CPU_STPC: #ifdef USE_DYNAREC - x86_setopcodes(ops_386, ops_c486_0f, dynarec_ops_386, dynarec_ops_c486_0f); + if (cpu_s->cpu_type == CPU_STPC) + x86_setopcodes(ops_386, ops_stpc_0f, dynarec_ops_386, dynarec_ops_stpc_0f); + else + x86_setopcodes(ops_386, ops_c486_0f, dynarec_ops_386, dynarec_ops_c486_0f); #else - x86_setopcodes(ops_386, ops_c486_0f); + if (cpu_s->cpu_type == CPU_STPC) + x86_setopcodes(ops_386, ops_stpc_0f); + else + x86_setopcodes(ops_386, ops_c486_0f); #endif timing_rr = 1; /* register dest - register src */ @@ -846,6 +853,9 @@ cpu_set(void) timing_jmp_pm_gate = 37; timing_misaligned = 3; + + if (cpu_s->cpu_type == CPU_STPC) + cpu_features = CPU_FEATURE_RDTSC; break; case CPU_Cx5x86: diff --git a/src/cpu/cpu.h b/src/cpu/cpu.h index 2aecdf13e..e4bf676bb 100644 --- a/src/cpu/cpu.h +++ b/src/cpu/cpu.h @@ -54,6 +54,7 @@ enum { CPU_Am486DX, CPU_Am486DXL, CPU_Cx486DX, + CPU_STPC, CPU_i486SX_SLENH, CPU_i486DX_SLENH, CPU_ENH_Am486DX, diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 57aa3f7ca..707c9299b 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -576,8 +576,8 @@ const cpu_family_t cpu_families[] = { .name = "STPC-DX", .internal_name = "stpc_dx", .cpus = (const CPU[]) { - {"66", CPU_Cx486DX, fpus_internal, 66666666, 1.0, 3300, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"75", CPU_Cx486DX, fpus_internal, 75000000, 1.0, 3300, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"66", CPU_STPC, fpus_internal, 66666666, 1.0, 3300, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"75", CPU_STPC, fpus_internal, 75000000, 1.0, 3300, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, {"", 0} } }, { @@ -586,7 +586,7 @@ const cpu_family_t cpu_families[] = { .name = "STPC-DX2", .internal_name = "stpc_dx2", .cpus = (const CPU[]) { - {"133", CPU_Cx486DX, fpus_internal, 133333333, 2.0, 3300, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"133", CPU_STPC, fpus_internal, 133333333, 2.0, 3300, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, {"", 0} } }, { diff --git a/src/cpu/x86_ops.h b/src/cpu/x86_ops.h index dc0d62782..2c8812570 100644 --- a/src/cpu/x86_ops.h +++ b/src/cpu/x86_ops.h @@ -80,6 +80,7 @@ extern const OpFn dynarec_ops_386_0f[1024]; extern const OpFn dynarec_ops_486_0f[1024]; extern const OpFn dynarec_ops_c486_0f[1024]; +extern const OpFn dynarec_ops_stpc_0f[1024]; extern const OpFn dynarec_ops_ibm486_0f[1024]; extern const OpFn dynarec_ops_winchip_0f[1024]; @@ -178,6 +179,7 @@ extern const OpFn ops_386_0f[1024]; extern const OpFn ops_486_0f[1024]; extern const OpFn ops_c486_0f[1024]; +extern const OpFn ops_stpc_0f[1024]; extern const OpFn ops_ibm486_0f[1024]; extern const OpFn ops_winchip_0f[1024]; From f0e84f7f13d27d1ebca25df2411d2ebb2bf01568 Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 9 Aug 2021 16:10:55 +0200 Subject: [PATCH 4/5] More fixes, fixes CMOS Setup on the Acrosses AR-B4179. --- src/chipset/stpc.c | 2 +- src/cpu/386_common.c | 1 + src/cpu/cpu.c | 7 ++++--- src/cpu/cpu_table.c | 2 +- 4 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/chipset/stpc.c b/src/chipset/stpc.c index 441ae487b..6541837cb 100644 --- a/src/chipset/stpc.c +++ b/src/chipset/stpc.c @@ -150,7 +150,7 @@ stpc_recalcmapping(stpc_t *dev) } } - flushmmucache(); + flushmmucache_nopc(); } diff --git a/src/cpu/386_common.c b/src/cpu/386_common.c index fbb67df1c..099e6d72e 100644 --- a/src/cpu/386_common.c +++ b/src/cpu/386_common.c @@ -306,6 +306,7 @@ enum SMMRAM_Fields_AMD_K { }; +#define ENABLE_386_COMMON_LOG 1 #ifdef ENABLE_386_COMMON_LOG int x386_common_do_log = ENABLE_386_COMMON_LOG; diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c index b8709254a..5da0778ab 100644 --- a/src/cpu/cpu.c +++ b/src/cpu/cpu.c @@ -375,7 +375,7 @@ cpu_set(void) is_am486dxl = (cpu_s->cpu_type == CPU_Am486DXL); cpu_isintel = !strcmp(cpu_f->manufacturer, "Intel"); - cpu_iscyrix = !strcmp(cpu_f->manufacturer, "Cyrix"); + cpu_iscyrix = !strcmp(cpu_f->manufacturer, "Cyrix") || !strcmp(cpu_f->manufacturer, "ST"); /* SL-Enhanced Intel 486s have the same SMM save state table layout as Pentiums, and the WinChip datasheet claims those are Pentium-compatible as well. AMD Am486DXL/DXL2 also has compatible SMM, or would if not for it's different SMBase*/ @@ -385,7 +385,8 @@ cpu_set(void) is_k6 = (cpu_s->cpu_type >= CPU_K6) && !strcmp(cpu_f->manufacturer, "AMD"); /* The Samuel 2 datasheet claims it's Celeron-compatible. */ is_p6 = (cpu_isintel && (cpu_s->cpu_type >= CPU_PENTIUMPRO)) || !strcmp(cpu_f->manufacturer, "VIA"); - is_cxsmm = !strcmp(cpu_f->manufacturer, "Cyrix") && (cpu_s->cpu_type >= CPU_Cx486S); + is_cxsmm = (!strcmp(cpu_f->manufacturer, "Cyrix") || !strcmp(cpu_f->manufacturer, "ST")) && + (cpu_s->cpu_type >= CPU_Cx486S); hasfpu = (fpu_type != FPU_NONE); hascache = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC) || @@ -2962,7 +2963,7 @@ cpu_read(uint16_t addr, void *priv) if ((cyrix_addr & 0xf0) == 0xc0) return 0xff; - if (cyrix_addr == 0x20 && cpu_s->cpu_type == CPU_Cx5x86) + if (cyrix_addr == 0x20 && (cpu_s->cpu_type == CPU_Cx5x86)) return 0xff; } diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 707c9299b..e40d64400 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -586,7 +586,7 @@ const cpu_family_t cpu_families[] = { .name = "STPC-DX2", .internal_name = "stpc_dx2", .cpus = (const CPU[]) { - {"133", CPU_STPC, fpus_internal, 133333333, 2.0, 3300, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"133", CPU_STPC, fpus_internal, 133333333, 2.0, 3300, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, {"", 0} } }, { From 03d91af98cdb14611cb159146addac72bcafb391 Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 10 Aug 2021 15:37:15 +0200 Subject: [PATCH 5/5] Some Flash fixes for the Acrosser AR-B1479. --- src/include/86box/flash.h | 1 + src/machine/m_at_386dx_486.c | 6 +- src/mem/sst_flash.c | 125 +++++++++++++++++++++++++++-------- 3 files changed, 100 insertions(+), 32 deletions(-) diff --git a/src/include/86box/flash.h b/src/include/86box/flash.h index 43274e367..d16814b75 100644 --- a/src/include/86box/flash.h +++ b/src/include/86box/flash.h @@ -22,6 +22,7 @@ extern const device_t intel_flash_bxb_device; extern const device_t sst_flash_29ee010_device; extern const device_t sst_flash_29ee020_device; +extern const device_t winbond_flash_w29c020_device; extern const device_t sst_flash_39sf010_device; extern const device_t sst_flash_39sf020_device; extern const device_t sst_flash_39sf040_device; \ No newline at end of file diff --git a/src/machine/m_at_386dx_486.c b/src/machine/m_at_386dx_486.c index aebfa45ee..d7b880fdb 100644 --- a/src/machine/m_at_386dx_486.c +++ b/src/machine/m_at_386dx_486.c @@ -97,7 +97,7 @@ machine_at_sis401_common_init(const machine_t *model) device_add(&keyboard_at_ami_device); if (fdc_type == FDC_INTERNAL) - device_add(&fdc_at_device); + device_add(&fdc_at_device); } @@ -227,7 +227,7 @@ machine_at_spc6000a_init(const machine_t *model) device_add(&cs8230_device); if (fdc_type == FDC_INTERNAL) - device_add(&fdc_at_device); + device_add(&fdc_at_device); device_add(&keyboard_at_samsung_device); @@ -1310,7 +1310,7 @@ machine_at_arb1479_init(const machine_t *model) device_add(&w83977f_device); device_add(&keyboard_ps2_ami_pci_device); device_add(&stpc_consumer2_device); - device_add(&sst_flash_29ee020_device); + device_add(&sst_flash_39sf020_device); return ret; } diff --git a/src/mem/sst_flash.c b/src/mem/sst_flash.c index 1a0bb0550..8d0645f07 100644 --- a/src/mem/sst_flash.c +++ b/src/mem/sst_flash.c @@ -35,7 +35,8 @@ typedef struct sst_t { - uint8_t id, is_39, page_bytes, sdp; + uint8_t manufacturer, id, has_bbp, is_39, + page_bytes, sdp, bbp_first_8k, bbp_last_8k; int command_state, id_mode, dirty; @@ -60,6 +61,7 @@ static char flash_path[1024]; #define SST_CHIP_ERASE 0x10 /* Both 29 and 39, 6th cycle */ #define SST_SDP_DISABLE 0x20 /* Only 29, Software data protect disable and write - treat as write */ #define SST_SECTOR_ERASE 0x30 /* Only 39, 6th cycle */ +#define W_BOOT_BLOCK_PROT 0x40 /* Only W29C020 */ #define SST_SET_ID_MODE_ALT 0x60 /* Only 29, 6th cycle */ #define SST_ERASE 0x80 /* Both 29 and 39 */ /* With data 60h on 6th cycle, it's alt. ID */ @@ -68,21 +70,36 @@ static char flash_path[1024]; #define SST_CLEAR_ID_MODE 0xf0 /* Both 29 and 39 */ /* 1st cycle variant only on 39 */ -#define SST_ID_MANUFACTURER 0xbf /* SST Manufacturer's ID */ -#define SST_ID_SST29EE010 0x07 -#define SST_ID_SST29LE_VE010 0x08 -#define SST_ID_SST29EE020 0x10 -#define SST_ID_SST29LE_VE020 0x12 -#define SST_ID_SST39SF512 0xb4 -#define SST_ID_SST39SF010 0xb5 -#define SST_ID_SST39SF020 0xb6 -#define SST_ID_SST39SF040 0xb7 +#define SST 0xbf /* SST Manufacturer's ID */ +#define SST29EE010 0x0700 +#define SST29LE_VE010 0x0800 +#define SST29EE020 0x1000 +#define SST29LE_VE020 0x1200 +#define SST39SF512 0xb400 +#define SST39SF010 0xb500 +#define SST39SF020 0xb600 +#define SST39SF040 0xb700 + +#define WINBOND 0xda /* Winbond Manufacturer's ID */ +#define W29C020 0x4500 + +#define SIZE_512K 0x010000 +#define SIZE_1M 0x020000 +#define SIZE_2M 0x040000 +#define SIZE_4M 0x080000 static void sst_sector_erase(sst_t *dev, uint32_t addr) { - memset(&dev->array[addr & (dev->mask & ~0xfff)], 0xff, 4096); + uint32_t base = addr & (dev->mask & ~0xfff); + + if ((base < 0x2000) && (dev->bbp_first_8k & 0x01)) + return; + else if ((base >= (dev->size - 0x2000)) && (dev->bbp_last_8k & 0x01)) + return; + + memset(&dev->array[base], 0xff, 4096); dev->dirty = 1; } @@ -90,9 +107,19 @@ sst_sector_erase(sst_t *dev, uint32_t addr) static void sst_new_command(sst_t *dev, uint32_t addr, uint8_t val) { + uint32_t base = 0x00000, size = dev->size; + if (dev->command_state == 5) switch (val) { case SST_CHIP_ERASE: - memset(dev->array, 0xff, 0x20000); + if (dev->bbp_first_8k & 0x01) { + base += 0x2000; + size -= 0x2000; + } + + if (dev->bbp_last_8k & 0x01) + size -= 0x2000; + + memset(&(dev->array[base]), 0xff, size); dev->command_state = 0; break; @@ -138,6 +165,10 @@ sst_new_command(sst_t *dev, uint32_t addr, uint8_t val) dev->command_state = 6; break; + case W_BOOT_BLOCK_PROT: + dev->command_state = dev->has_bbp ? 8 : 0; + break; + case SST_CLEAR_ID_MODE: dev->id_mode = 0; dev->command_state = 0; @@ -160,6 +191,11 @@ sst_page_write(void *priv) dev->page_base = dev->last_addr & dev->page_mask; for (i = 0; i < 128; i++) { if (dev->page_dirty[i]) { + if (((dev->page_base + i) < 0x2000) && (dev->bbp_first_8k & 0x01)) + continue; + else if (((dev->page_base + i) >= (dev->size - 0x2000)) && (dev->bbp_last_8k & 0x01)) + continue; + dev->array[dev->page_base + i] = dev->page_buffer[i]; dev->dirty |= 1; } @@ -175,12 +211,24 @@ static uint8_t sst_read_id(uint32_t addr, void *p) { sst_t *dev = (sst_t *) p; - uint8_t ret = 0xff; + uint8_t ret = 0x00; if ((addr & 0xffff) == 0) - ret = SST_ID_MANUFACTURER; /* SST */ + ret = dev->manufacturer; else if ((addr & 0xffff) == 1) ret = dev->id; +#ifdef UNKNOWN_FLASH + else if ((addr & 0xffff) == 0x100) + ret = 0x1c; + else if ((addr & 0xffff) == 0x101) + ret = 0x92; +#endif + else if (dev->has_bbp) { + if (addr == 0x00002) + ret = dev->bbp_first_8k; + else if (addr == 0x3fff2) + ret = dev->bbp_last_8k; + } return ret; } @@ -249,8 +297,9 @@ sst_write(uint32_t addr, uint8_t val, void *p) case 6: /* Page Load Cycle (29) / Data Write Cycle (39SF) */ if (dev->is_39) { - dev->array[addr & dev->mask] = val; dev->command_state = 0; + + dev->array[addr & dev->mask] = val; dev->dirty = 1; } else { dev->command_state++; @@ -261,6 +310,13 @@ sst_write(uint32_t addr, uint8_t val, void *p) if (!dev->is_39) sst_buf_write(dev, addr, val); break; + case 8: + if ((addr == 0x00000) && (val == 0x00)) + dev->bbp_first_8k = 0xff; + else if ((addr == 0x3ffff) && (val == 0xff)) + dev->bbp_last_8k = 0xff; + dev->command_state = 0; + break; } } @@ -367,20 +423,19 @@ sst_init(const device_t *info) dev->array = (uint8_t *) malloc(biosmask + 1); memset(dev->array, 0xff, biosmask + 1); - dev->id = info->local; - dev->is_39 = (dev->id >= SST_ID_SST39SF512); + dev->manufacturer = info->local & 0xff; + dev->id = (info->local >> 8) & 0xff; + dev->has_bbp = (dev->manufacturer == WINBOND) && ((info->local & 0xff00) >= W29C020); + dev->is_39 = (dev->manufacturer == SST) && ((info->local & 0xff00) >= SST39SF512); - if (dev->id == SST_ID_SST39SF512) + dev->size = info->local & 0xffff0000; + if ((dev->size == 0x20000) && (strstr(machine_get_internal_name_ex(machine), "xi8088")) && !xi8088_bios_128kb()) dev->size = 0x10000; - else if ((dev->id == SST_ID_SST29EE020) || (dev->id == SST_ID_SST29LE_VE020) || (dev->id == SST_ID_SST39SF020)) - dev->size = 0x40000; - else if (dev->id == SST_ID_SST39SF040) - dev->size = 0x80000; - else - dev->size = ((dev->id == SST_ID_SST39SF010) && (strstr(machine_get_internal_name_ex(machine), "xi8088")) && !xi8088_bios_128kb()) ? 0x10000 : 0x20000; + dev->mask = dev->size - 1; dev->page_mask = dev->mask & 0xffffff80; /* Filter out A0-A6. */ dev->sdp = 1; + dev->bbp_first_8k = dev->bbp_last_8k = 0xfe; sst_add_mappings(dev); @@ -422,7 +477,7 @@ const device_t sst_flash_29ee010_device = { "SST 29EE010 Flash BIOS", 0, - SST_ID_SST29EE010, + SST | SST29EE010 | SIZE_1M, sst_init, sst_close, NULL, @@ -434,7 +489,19 @@ const device_t sst_flash_29ee020_device = { "SST 29EE020 Flash BIOS", 0, - SST_ID_SST29EE020, + SST | SST29EE020 | SIZE_2M, + sst_init, + sst_close, + NULL, + { NULL }, NULL, NULL, NULL +}; + + +const device_t winbond_flash_w29c020_device = +{ + "Winbond W29C020 Flash BIOS", + 0, + WINBOND | W29C020 | SIZE_2M, sst_init, sst_close, NULL, @@ -446,7 +513,7 @@ const device_t sst_flash_39sf010_device = { "SST 39SF010 Flash BIOS", 0, - SST_ID_SST39SF010, + SST | SST39SF010 | SIZE_1M, sst_init, sst_close, NULL, @@ -458,7 +525,7 @@ const device_t sst_flash_39sf020_device = { "SST 39SF020 Flash BIOS", 0, - SST_ID_SST39SF020, + SST | SST39SF020 | SIZE_2M, sst_init, sst_close, NULL, @@ -469,7 +536,7 @@ const device_t sst_flash_39sf040_device = { "SST 39SF040 Flash BIOS", 0, - SST_ID_SST39SF040, + SST | SST39SF040 | SIZE_4M, sst_init, sst_close, NULL,