Fixed the Cirrus banking issue for good (really)

A bit controversial regarding extra_banks but this should be enough to fix everything in the banks of the CL-GD54xx (up to 5480).

src/video/vid_cl54xx.c

@@ -816,7 +816,7 @@ gd54xx_out(uint16_t addr, uint8_t val, void *priv)
                             svga->seqregs[svga->seqaddr] &= 0x0f;
                         if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5429)
                             svga->set_reset_disabled = svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA;
-                        gd54xx_recalc_banking(gd54xx);
+
                         gd54xx_set_svga_fast(gd54xx);
                         svga_recalctimings(svga);
                         break;
@@ -1642,8 +1642,6 @@ gd54xx_recalc_banking(gd54xx_t *gd54xx)
         } else
             svga->extra_banks[1] = svga->extra_banks[0] + 0x8000;
     }
-
-    svga->write_bank = svga->read_bank = svga->extra_banks[0];
 }
 
 static void
@@ -1977,11 +1975,16 @@ gd54xx_recalctimings(svga_t *svga)
         svga->htotal += ((svga->crtc[0x1c] >> 3) & 0x07);
 
     if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) { /*Text mode*/
-        if (svga->seqregs[1] & 8) {
+        if (svga->seqregs[1] & 8)
             svga->render = svga_render_text_40;
-        } else
+        else
             svga->render = svga_render_text_80;
     }
+
+    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA)) {
+        svga->extra_banks[0] = 0;
+        svga->extra_banks[1] = 0x8000;
+    }
 }
 
 static void
@@ -2192,13 +2195,8 @@ gd54xx_write(uint32_t addr, uint8_t val, void *priv)
         return;
     }
 
-    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) || !(svga->gdcreg[5] & 0x40)) {
+    addr &= svga->banked_mask;
-        svga_write(addr, val, svga);
-        return;
-    }
-
     addr = (addr & 0x7fff) + svga->extra_banks[(addr >> 15) & 1];
-
     svga_write_linear(addr, val, svga);
 }
 
@@ -2214,11 +2212,7 @@ gd54xx_writew(uint32_t addr, uint16_t val, void *priv)
         return;
     }
 
-    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) || !(svga->gdcreg[5] & 0x40)) {
+    addr &= svga->banked_mask;
-        svga_writew(addr, val, svga);
-        return;
-    }
-
     addr = (addr & 0x7fff) + svga->extra_banks[(addr >> 15) & 1];
 
     if (svga->writemode < 4)
@@ -2243,11 +2237,7 @@ gd54xx_writel(uint32_t addr, uint32_t val, void *priv)
         return;
     }
 
-    if ((svga->seqregs[0x07] & 0x01) == 0) {
+    addr &= svga->banked_mask;
-        svga_writel(addr, val, svga);
-        return;
-    }
-
     addr = (addr & 0x7fff) + svga->extra_banks[(addr >> 15) & 1];
 
     if (svga->writemode < 4)
@@ -2769,12 +2759,10 @@ gd54xx_read(uint32_t addr, void *priv)
     gd54xx_t *gd54xx = (gd54xx_t *) priv;
     svga_t   *svga   = &gd54xx->svga;
 
-    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) || !(svga->gdcreg[5] & 0x40))
-        return svga_read(addr, svga);
-
     if (gd54xx->countminusone && gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED))
         return gd54xx_mem_sys_dest_read(gd54xx, 0);
 
+    addr &= svga->banked_mask;
     addr = (addr & 0x7fff) + svga->extra_banks[(addr >> 15) & 1];
     return svga_read_linear(addr, svga);
 }
@@ -2786,15 +2774,13 @@ gd54xx_readw(uint32_t addr, void *priv)
     svga_t   *svga   = &gd54xx->svga;
     uint16_t  ret;
 
-    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) || !(svga->gdcreg[5] & 0x40))
-        return svga_readw(addr, svga);
-
     if (gd54xx->countminusone && gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
         ret = gd54xx_read(addr, priv);
         ret |= gd54xx_read(addr + 1, priv) << 8;
         return ret;
     }
 
+    addr &= svga->banked_mask;
     addr = (addr & 0x7fff) + svga->extra_banks[(addr >> 15) & 1];
     return svga_readw_linear(addr, svga);
 }
@@ -2806,9 +2792,6 @@ gd54xx_readl(uint32_t addr, void *priv)
     svga_t   *svga   = &gd54xx->svga;
     uint32_t  ret;
 
-    if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) || !(svga->gdcreg[5] & 0x40))
-        return svga_readl(addr, svga);
-
     if (gd54xx->countminusone && gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
         ret = gd54xx_read(addr, priv);
         ret |= gd54xx_read(addr + 1, priv) << 8;
@@ -2817,6 +2800,7 @@ gd54xx_readl(uint32_t addr, void *priv)
         return ret;
     }
 
+    addr &= svga->banked_mask;
     addr = (addr & 0x7fff) + svga->extra_banks[(addr >> 15) & 1];
     return svga_readl_linear(addr, svga);
 }

src/video/vid_svga.c

@@ -1406,15 +1406,10 @@ svga_decode_addr(svga_t *svga, uint32_t addr, int write)
     }
 
     if (memory_map_mode <= 1) {
-        if (svga->adv_flags & FLAG_EXTRA_BANKS) {
+        if (write)
-            if ((svga->gdcreg[5] & 0x40) || svga->packed_chain4)
+            addr += svga->write_bank;
-                addr = (addr & 0x17fff) + svga->extra_banks[(addr >> 15) & 1];
+        else
-        } else {
+            addr += svga->read_bank;
-            if (write)
-                addr += svga->write_bank;
-            else
-                addr += svga->read_bank;
-        }
     }
 
     return addr;