From df5c1a1a46a992bece32ef8ce090911324b052cb Mon Sep 17 00:00:00 2001 From: TC1995 Date: Tue, 19 Jul 2022 16:32:23 +0200 Subject: [PATCH] ISA PS/2: Clean-ups and converted into a typedef struct. MCA PS/2: Added Model 60 (8-slot version of 50 with the same bios) and Model 65sx (essentially the same as 55sx but with a new bios and a secondary nvram a la 70-80 but limited to 2KB of size instead of 8KB). MCA PS/2: Made the i486 cpu selection on only on Type 3 MCA models (70-80) and not Type 2 anymore, therefore the latter is limited to 386DX cpu's only. --- src/include/86box/machine.h | 2 + src/include/86box/nvr_ps2.h | 1 + src/machine/m_ps2_isa.c | 283 +++++++++++++++++++----------------- src/machine/m_ps2_mca.c | 100 ++++++++++--- src/machine/machine_table.c | 14 +- src/nvr_ps2.c | 35 ++++- 6 files changed, 266 insertions(+), 169 deletions(-) diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h index 8456b4dc8..449942915 100644 --- a/src/include/86box/machine.h +++ b/src/include/86box/machine.h @@ -777,7 +777,9 @@ extern int machine_ps2_m30_286_init(const machine_t *); /* m_ps2_mca.c */ extern int machine_ps2_model_50_init(const machine_t *); +extern int machine_ps2_model_60_init(const machine_t *); extern int machine_ps2_model_55sx_init(const machine_t *); +extern int machine_ps2_model_65sx_init(const machine_t *); extern int machine_ps2_model_70_type3_init(const machine_t *); extern int machine_ps2_model_80_init(const machine_t *); extern int machine_ps2_model_80_axx_init(const machine_t *); diff --git a/src/include/86box/nvr_ps2.h b/src/include/86box/nvr_ps2.h index 7cb37a625..fe3f141e2 100644 --- a/src/include/86box/nvr_ps2.h +++ b/src/include/86box/nvr_ps2.h @@ -40,6 +40,7 @@ extern const device_t ps2_nvr_device; +extern const device_t ps2_nvr_55ls_device; #endif /*EMU_NVRPS2_H*/ diff --git a/src/machine/m_ps2_isa.c b/src/machine/m_ps2_isa.c index c39c4eb92..6e26b159d 100644 --- a/src/machine/m_ps2_isa.c +++ b/src/machine/m_ps2_isa.c @@ -1,5 +1,6 @@ #include #include +#include #include #include #include <86box/86box.h> @@ -25,145 +26,175 @@ #include <86box/machine.h> -static uint8_t ps2_91, ps2_94, ps2_102, ps2_103, ps2_104, ps2_105, ps2_190; -static serial_t *ps2_uart; +typedef struct { + int model; + int cpu_type; + + uint8_t ps2_91, + ps2_92, + ps2_94, + ps2_102, + ps2_103, + ps2_104, + ps2_105, + ps2_190; + + serial_t *uart; +} ps2_isa_t; -static struct +static void +ps2_write(uint16_t port, uint8_t val, void *priv) { - uint8_t status, int_status; - uint8_t attention, ctrl; -} ps2_hd; + ps2_isa_t *ps2 = (ps2_isa_t *)priv; + switch (port) { + case 0x0094: + ps2->ps2_94 = val; + break; -static uint8_t ps2_read(uint16_t port, void *p) -{ - uint8_t temp; + case 0x0102: + if (!(ps2->ps2_94 & 0x80)) { + lpt1_remove(); + serial_remove(ps2->uart); + if (val & 0x04) { + if (val & 0x08) + serial_setup(ps2->uart, COM1_ADDR, COM1_IRQ); + else + serial_setup(ps2->uart, COM2_ADDR, COM2_IRQ); + } + if (val & 0x10) { + switch ((val >> 5) & 3) { + case 0: + lpt1_init(LPT_MDA_ADDR); + break; + case 1: + lpt1_init(LPT1_ADDR); + break; + case 2: + lpt1_init(LPT2_ADDR); + break; + } + } + ps2->ps2_102 = val; + } + break; - switch (port) - { - case 0x91: - temp = ps2_91; - ps2_91 = 0; - return temp; - case 0x94: - return ps2_94; - case 0x102: - return ps2_102 | 8; - case 0x103: - return ps2_103; - case 0x104: - return ps2_104; - case 0x105: - return ps2_105; - case 0x190: - return ps2_190; + case 0x0103: + ps2->ps2_103 = val; + break; -#ifdef FIXME - case 0x322: - temp = ps2_hd.status; - break; - case 0x324: - temp = ps2_hd.int_status; - ps2_hd.int_status &= ~0x02; - break; -#endif + case 0x0104: + ps2->ps2_104 = val; + break; - default: - temp = 0xff; - break; - } + case 0x0105: + ps2->ps2_105 = val; + break; - return temp; + case 0x0190: + ps2->ps2_190 = val; + break; + } } -static void ps2_write(uint16_t port, uint8_t val, void *p) +static uint8_t +ps2_read(uint16_t port, void *priv) { - switch (port) - { - case 0x94: - ps2_94 = val; - break; - case 0x102: - if (!(ps2_94 & 0x80)) { - lpt1_remove(); - serial_remove(ps2_uart); - if (val & 0x04) { - if (val & 0x08) - serial_setup(ps2_uart, COM1_ADDR, COM1_IRQ); - else - serial_setup(ps2_uart, COM2_ADDR, COM2_IRQ); - } - if (val & 0x10) { - switch ((val >> 5) & 3) - { - case 0: - lpt1_init(LPT_MDA_ADDR); - break; - case 1: - lpt1_init(LPT1_ADDR); - break; - case 2: - lpt1_init(LPT2_ADDR); - break; - } - } - ps2_102 = val; - } - break; + ps2_isa_t *ps2 = (ps2_isa_t *)priv; + uint8_t temp = 0xff; - case 0x103: - ps2_103 = val; - break; - case 0x104: - ps2_104 = val; - break; - case 0x105: - ps2_105 = val; - break; - case 0x190: - ps2_190 = val; - break; + switch (port) { + case 0x0091: + temp = ps2->ps2_91; + ps2->ps2_91 = 0; + break; -#ifdef FIXME - case 0x322: - ps2_hd.ctrl = val; - if (val & 0x80) - ps2_hd.status |= 0x02; - break; - case 0x324: - ps2_hd.attention = val & 0xf0; - if (ps2_hd.attention) - ps2_hd.status = 0x14; - break; -#endif - } + case 0x0094: + temp = ps2->ps2_94; + break; + + case 0x0102: + temp = ps2->ps2_102 | 0x08; + break; + + case 0x0103: + temp = ps2->ps2_103; + break; + + case 0x0104: + temp = ps2->ps2_104; + break; + + case 0x0105: + temp = ps2->ps2_105; + break; + + case 0x0190: + temp = ps2->ps2_190; + break; + } + + return temp; } - -static void ps2board_init(void) +static void +ps2_isa_setup(int model, int cpu_type) { - io_sethandler(0x0091, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL); - io_sethandler(0x0094, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL); - io_sethandler(0x0102, 0x0004, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL); - io_sethandler(0x0190, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL); -#ifdef FIXME - io_sethandler(0x0320, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL); - io_sethandler(0x0322, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL); - io_sethandler(0x0324, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL); -#endif + ps2_isa_t *ps2; + void *priv; + + ps2 = (ps2_isa_t *)malloc(sizeof(ps2_isa_t)); + memset(ps2, 0x00, sizeof(ps2_isa_t)); + ps2->model = model; + ps2->cpu_type = cpu_type; + + + io_sethandler(0x0091, 1, + ps2_read, NULL, NULL, ps2_write, NULL, NULL, ps2); + io_sethandler(0x0094, 1, + ps2_read, NULL, NULL, ps2_write, NULL, NULL, ps2); + io_sethandler(0x0102, 4, + ps2_read, NULL, NULL, ps2_write, NULL, NULL, ps2); + io_sethandler(0x0190, 1, + ps2_read, NULL, NULL, ps2_write, NULL, NULL, ps2); + + ps2->uart = device_add_inst(&ns16450_device, 1); + + lpt1_remove(); + lpt1_init(LPT_MDA_ADDR); device_add(&port_92_device); - ps2_190 = 0; + mem_remap_top(384); - ps2_uart = device_add_inst(&ns16450_device, 1); + device_add(&ps_nvr_device); - lpt1_init(LPT_MDA_ADDR); + device_add(&fdc_at_ps1_device); - memset(&ps2_hd, 0, sizeof(ps2_hd)); + /* Enable the builtin HDC. */ + if (hdc_current == 1) { + priv = device_add(&ps1_hdc_device); + ps1_hdc_inform(priv, &ps2->ps2_91); + } + + device_add(&ps1vga_device); } +static void +ps2_isa_common_init(const machine_t *model) +{ + machine_common_init(model); + + refresh_at_enable = 1; + pit_ctr_set_out_func(&pit->counters[1], pit_refresh_timer_at); + + dma16_init(); + pic2_init(); + + device_add(&keyboard_ps2_device); + device_add(&port_6x_ps2_device); +} int machine_ps2_m30_286_init(const machine_t *model) @@ -178,28 +209,10 @@ machine_ps2_m30_286_init(const machine_t *model) if (bios_only || !ret) return ret; - machine_common_init(model); + ps2_isa_common_init(model); - mem_remap_top(384); - - device_add(&fdc_at_ps1_device); - - refresh_at_enable = 1; - pit_ctr_set_out_func(&pit->counters[1], pit_refresh_timer_at); - dma16_init(); - device_add(&keyboard_ps2_device); - device_add(&port_6x_ps2_device); - device_add(&ps_nvr_device); - pic2_init(); - ps2board_init(); - device_add(&ps1vga_device); - - /* Enable the builtin HDC. */ - if (hdc_current == 1) { - priv = device_add(&ps1_hdc_device); - - ps1_hdc_inform(priv, &ps2_91); - } + ps2_isa_setup(30, 286); return ret; } + diff --git a/src/machine/m_ps2_mca.c b/src/machine/m_ps2_mca.c index 094487d37..c0296fb2a 100644 --- a/src/machine/m_ps2_mca.c +++ b/src/machine/m_ps2_mca.c @@ -253,9 +253,9 @@ static uint8_t model_50_read(uint16_t port) switch (port) { case 0x100: - return 0xff; + return ps2.planar_id & 0xff; case 0x101: - return 0xfb; + return ps2.planar_id >> 8; case 0x102: return ps2.option[0]; case 0x103: @@ -277,9 +277,9 @@ static uint8_t model_55sx_read(uint16_t port) switch (port) { case 0x100: - return 0xff; + return ps2.planar_id & 0xff; case 0x101: - return 0xfb; + return ps2.planar_id >> 8; case 0x102: return ps2.option[0]; case 0x103: @@ -325,9 +325,9 @@ static uint8_t model_80_read(uint16_t port) switch (port) { case 0x100: - return 0xff; + return ps2.planar_id & 0xff; case 0x101: - return 0xfd; + return ps2.planar_id >> 8; case 0x102: return ps2.option[0]; case 0x103: @@ -829,17 +829,17 @@ static void ps2_mca_write(uint16_t port, uint8_t val, void *p) static void ps2_mca_board_common_init() { - io_sethandler(0x0091, 0x0001, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL); - io_sethandler(0x0094, 0x0001, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL); - io_sethandler(0x0096, 0x0001, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL); - io_sethandler(0x0100, 0x0008, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL); + io_sethandler(0x0091, 0x0001, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL); + io_sethandler(0x0094, 0x0001, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL); + io_sethandler(0x0096, 0x0001, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL); + io_sethandler(0x0100, 0x0008, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL); device_add(&port_6x_ps2_device); - device_add(&port_92_device); + device_add(&port_92_device); - ps2.setup = 0xff; + ps2.setup = 0xff; - lpt1_init(LPT_MDA_ADDR); + lpt1_init(LPT_MDA_ADDR); } static uint8_t ps2_mem_expansion_read(int port, void *p) @@ -951,12 +951,12 @@ static void ps2_mca_mem_d071_init(int start_mb) } -static void ps2_mca_board_model_50_init() +static void ps2_mca_board_model_50_init(int slots) { ps2_mca_board_common_init(); mem_remap_top(384); - mca_init(4); + mca_init(slots); device_add(&keyboard_ps2_mca_2_device); ps2.planar_read = model_50_read; @@ -972,7 +972,7 @@ static void ps2_mca_board_model_50_init() device_add(&ps1vga_mca_device); } -static void ps2_mca_board_model_55sx_init() +static void ps2_mca_board_model_55sx_init(int has_sec_nvram, int slots) { ps2_mca_board_common_init(); @@ -1015,14 +1015,20 @@ static void ps2_mca_board_model_55sx_init() break; } - mca_init(4); + mca_init(slots); device_add(&keyboard_ps2_mca_device); + if (has_sec_nvram == 1) + device_add(&ps2_nvr_55ls_device); + else if (has_sec_nvram == 2) { + device_add(&ps2_nvr_device); + } + ps2.planar_read = model_55sx_read; ps2.planar_write = model_55sx_write; - if (gfxcard == VID_INTERNAL) - device_add(&ps1vga_mca_device); + if (gfxcard == VID_INTERNAL) + device_add(&ps1vga_mca_device); model_55sx_mem_recalc(); } @@ -1383,7 +1389,31 @@ machine_ps2_model_50_init(const machine_t *model) machine_ps2_common_init(model); - ps2_mca_board_model_50_init(); + ps2.planar_id = 0xfbff; + ps2_mca_board_model_50_init(4); + + return ret; +} + +int +machine_ps2_model_60_init(const machine_t *model) +{ + int ret; + + ret = bios_load_interleaved("roms/machines/ibmps2_m50/90x7420.zm13", + "roms/machines/ibmps2_m50/90x7429.zm18", + 0x000f0000, 131072, 0); + ret &= bios_load_aux_interleaved("roms/machines/ibmps2_m50/90x7423.zm14", + "roms/machines/ibmps2_m50/90x7426.zm16", + 0x000e0000, 65536, 0); + + if (bios_only || !ret) + return ret; + + machine_ps2_common_init(model); + + ps2.planar_id = 0xf7ff; + ps2_mca_board_model_50_init(8); return ret; } @@ -1403,12 +1433,33 @@ machine_ps2_model_55sx_init(const machine_t *model) machine_ps2_common_init(model); - ps2_mca_board_model_55sx_init(); + ps2.planar_id = 0xfffb; + ps2_mca_board_model_55sx_init(0, 4); return ret; } +int +machine_ps2_model_65sx_init(const machine_t *model) +{ + int ret; + + ret = bios_load_interleaved("roms/machines/ibmps2_m65sx/64F3608.BIN", + "roms/machines/ibmps2_m65sx/64F3611.BIN", + 0x000e0000, 131072, 0); + + if (bios_only || !ret) + return ret; + + machine_ps2_common_init(model); + + ps2.planar_id = 0xe3ff; + ps2_mca_board_model_55sx_init(1, 8); + + return ret; +} + int machine_ps2_model_70_type3_init(const machine_t *model) { @@ -1443,9 +1494,10 @@ machine_ps2_model_80_init(const machine_t *model) if (bios_only || !ret) return ret; - machine_ps2_common_init(model); + machine_ps2_common_init(model); - ps2_mca_board_model_80_type2_init(0); + ps2.planar_id = 0xfdff; + ps2_mca_board_model_80_type2_init(0); return ret; } @@ -1470,3 +1522,5 @@ machine_ps2_model_80_axx_init(const machine_t *model) return ret; } + + diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 7a0873f20..96f70ee65 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -312,6 +312,8 @@ const machine_t machines[] = { /* 286 machines that utilize the MCA bus */ /* Has IBM PS/2 Type 2 KBC firmware. */ { "[MCA] IBM PS/2 model 50", "ibmps2_m50", MACHINE_TYPE_286, MACHINE_CHIPSET_PROPRIETARY, machine_ps2_model_50_init, 0, 0, MACHINE_AVAILABLE, 0 , CPU_PKG_286 | CPU_PKG_486SLC_IBM, CPU_BLOCK_NONE, 10000000, 0, 0, 0, 0, 0, MACHINE_PS2_MCA, MACHINE_VIDEO, 1024, 10240, 1024, 63, NULL, NULL }, + /* Has IBM PS/2 Type 2 KBC firmware. */ + { "[MCA] IBM PS/2 model 60", "ibmps2_m60", MACHINE_TYPE_286, MACHINE_CHIPSET_PROPRIETARY, machine_ps2_model_60_init, 0, 0, MACHINE_AVAILABLE, 0 , CPU_PKG_286 | CPU_PKG_486SLC_IBM, CPU_BLOCK_NONE, 10000000, 0, 0, 0, 0, 0, MACHINE_PS2_MCA, MACHINE_VIDEO, 1024, 10240, 1024, 63, NULL, NULL }, /* 386SX machines */ /* ISA slots available because an official IBM expansion for that existed. */ @@ -373,6 +375,8 @@ const machine_t machines[] = { /* 386SX machines which utilize the MCA bus */ /* Has IBM PS/2 Type 1 KBC firmware. */ { "[MCA] IBM PS/2 model 55SX", "ibmps2_m55sx", MACHINE_TYPE_386SX, MACHINE_CHIPSET_PROPRIETARY, machine_ps2_model_55sx_init, 0, 0, MACHINE_AVAILABLE, 0 , CPU_PKG_386SX, CPU_BLOCK_NONE, 0, 0, 0, 0, 0, 0, MACHINE_PS2_MCA, MACHINE_VIDEO, 1024, 8192, 1024, 63, NULL, NULL }, + /* Has IBM PS/2 Type 1 KBC firmware. */ + { "[MCA] IBM PS/2 model 65SX", "ibmps2_m65sx", MACHINE_TYPE_386SX, MACHINE_CHIPSET_PROPRIETARY, machine_ps2_model_65sx_init, 0, 0, MACHINE_AVAILABLE, 0 , CPU_PKG_386SX, CPU_BLOCK_NONE, 0, 0, 0, 0, 0, 0, MACHINE_PS2_MCA, MACHINE_VIDEO, 1024, 8192, 1024, 63, NULL, NULL }, /* 486SLC machines */ /* 486SLC machines with just the ISA slot */ @@ -397,11 +401,7 @@ const machine_t machines[] = { /* 386DX machines which utilize the MCA bus */ /* Has IBM PS/2 Type 1 KBC firmware. */ - { "[MCA] IBM PS/2 model 70 (type 3)", "ibmps2_m70_type3", MACHINE_TYPE_386DX, MACHINE_CHIPSET_PROPRIETARY, machine_ps2_model_70_type3_init, 0, 0, MACHINE_AVAILABLE, 0 , CPU_PKG_386DX | CPU_PKG_486BL, CPU_BLOCK_NONE, 0, 0, 0, 0, 0, 0, MACHINE_PS2_MCA, MACHINE_VIDEO, 2048, 65536, 2048, 63, NULL, NULL }, - /* Has IBM PS/2 Type 1 KBC firmware. */ - { "[MCA] IBM PS/2 model 80 (type 2)", "ibmps2_m80", MACHINE_TYPE_386DX, MACHINE_CHIPSET_PROPRIETARY, machine_ps2_model_80_init, 0, 0, MACHINE_AVAILABLE, 0 , CPU_PKG_386DX | CPU_PKG_486BL | CPU_PKG_SOCKET1, CPU_BLOCK_NONE, 0, 0, 0, 0, 0, 0, MACHINE_PS2_MCA, MACHINE_VIDEO, 1024, 65536, 1024, 63, NULL, NULL }, - /* Has IBM PS/2 Type 1 KBC firmware. */ - { "[MCA] IBM PS/2 model 80 (type 3)", "ibmps2_m80_type3", MACHINE_TYPE_386DX, MACHINE_CHIPSET_PROPRIETARY, machine_ps2_model_80_axx_init, 0, 0, MACHINE_AVAILABLE, 0 , CPU_PKG_386DX | CPU_PKG_486BL | CPU_PKG_SOCKET1, CPU_BLOCK_NONE, 0, 0, 0, 0, 0, 0, MACHINE_PS2_MCA, MACHINE_VIDEO, 2048, 65536, 2048, 63, NULL, NULL }, + { "[MCA] IBM PS/2 model 80 (type 2)", "ibmps2_m80", MACHINE_TYPE_386DX, MACHINE_CHIPSET_PROPRIETARY, machine_ps2_model_80_init, 0, 0, MACHINE_AVAILABLE, 0 , CPU_PKG_386DX | CPU_PKG_486BL, CPU_BLOCK_NONE, 0, 0, 0, 0, 0, 0, MACHINE_PS2_MCA, MACHINE_VIDEO, 1024, 65536, 1024, 63, NULL, NULL }, /* 386DX/486 machines */ /* The BIOS sends commands C9 without a parameter and D5, both of which are @@ -411,6 +411,10 @@ const machine_t machines[] = { { "[OPTi 495] DataExpert SX495", "ami495", MACHINE_TYPE_386DX_486, MACHINE_CHIPSET_OPTI_495, machine_at_opti495_ami_init, 0, 0, MACHINE_AVAILABLE, 0 , CPU_PKG_386DX | CPU_PKG_SOCKET1, CPU_BLOCK_NONE, 0, 0, 0, 0, 0, 0, MACHINE_VLB, MACHINE_IDE, 1024, 32768, 1024, 127, NULL, NULL }, /* Has AMIKey F KBC firmware (it's just the MR BIOS for the above machine). */ { "[OPTi 495] DataExpert SX495 (MR BIOS)", "mr495", MACHINE_TYPE_386DX_486, MACHINE_CHIPSET_OPTI_495, machine_at_opti495_mr_init, 0, 0, MACHINE_AVAILABLE, 0 , CPU_PKG_386DX | CPU_PKG_SOCKET1, CPU_BLOCK_NONE, 0, 0, 0, 0, 0, 0, MACHINE_VLB, MACHINE_IDE, 1024, 32768, 1024, 127, NULL, NULL }, + /* Has IBM PS/2 Type 1 KBC firmware. */ + { "[MCA] IBM PS/2 model 70 (type 3)", "ibmps2_m70_type3", MACHINE_TYPE_386DX_486, MACHINE_CHIPSET_PROPRIETARY, machine_ps2_model_70_type3_init, 0, 0, MACHINE_AVAILABLE, 0 , CPU_PKG_386DX | CPU_PKG_486BL | CPU_PKG_SOCKET1, CPU_BLOCK_NONE, 0, 0, 0, 0, 0, 0, MACHINE_PS2_MCA, MACHINE_VIDEO, 2048, 65536, 2048, 63, NULL, NULL }, + /* Has IBM PS/2 Type 1 KBC firmware. */ + { "[MCA] IBM PS/2 model 80 (type 3)", "ibmps2_m80_type3", MACHINE_TYPE_386DX_486, MACHINE_CHIPSET_PROPRIETARY, machine_ps2_model_80_axx_init, 0, 0, MACHINE_AVAILABLE, 0 , CPU_PKG_386DX | CPU_PKG_486BL | CPU_PKG_SOCKET1, CPU_BLOCK_NONE, 0, 0, 0, 0, 0, 0, MACHINE_PS2_MCA, MACHINE_VIDEO, 2048, 65536, 2048, 63, NULL, NULL }, /* 486 machines - Socket 1 */ /* Has JetKey 5 KBC Firmware which looks like it is a clone of AMIKey type F. diff --git a/src/nvr_ps2.c b/src/nvr_ps2.c index cd6f47af7..e82eff150 100644 --- a/src/nvr_ps2.c +++ b/src/nvr_ps2.c @@ -53,7 +53,8 @@ typedef struct { int addr; - uint8_t ram[8192]; + uint8_t *ram; + int size; char *fn; } ps2_nvr_t; @@ -114,6 +115,11 @@ ps2_nvr_init(const device_t *info) nvr = (ps2_nvr_t *)malloc(sizeof(ps2_nvr_t)); memset(nvr, 0x00, sizeof(ps2_nvr_t)); + if (info->local) + nvr->size = 2048; + else + nvr->size = 8192; + /* Set up the NVR file's name. */ c = strlen(machine_get_internal_name()) + 9; nvr->fn = (char *)malloc(c + 1); @@ -124,9 +130,10 @@ ps2_nvr_init(const device_t *info) f = nvr_fopen(nvr->fn, "rb"); - memset(nvr->ram, 0xff, 8192); + nvr->ram = (uint8_t *)malloc(nvr->size); + memset(nvr->ram, 0xff, nvr->size); if (f != NULL) { - if (fread(nvr->ram, 1, 8192, f) != 8192) + if (fread(nvr->ram, 1, nvr->size, f) != nvr->size) fatal("ps2_nvr_init(): Error reading EEPROM data\n"); fclose(f); } @@ -144,16 +151,18 @@ ps2_nvr_close(void *priv) f = nvr_fopen(nvr->fn, "wb"); if (f != NULL) { - (void)fwrite(nvr->ram, 8192, 1, f); + (void)fwrite(nvr->ram, nvr->size, 1, f); fclose(f); } + if (nvr->ram != NULL) + free(nvr->ram); + free(nvr); } - const device_t ps2_nvr_device = { - .name = "PS/2 Secondary NVRAM", + .name = "PS/2 Secondary NVRAM for PS/2 Models 70-80", .internal_name = "ps2_nvr", .flags = 0, .local = 0, @@ -165,3 +174,17 @@ const device_t ps2_nvr_device = { .force_redraw = NULL, .config = NULL }; + +const device_t ps2_nvr_55ls_device = { + .name = "PS/2 Secondary NVRAM for PS/2 Models 55LS-65SX", + .internal_name = "ps2_nvr_55ls", + .flags = 0, + .local = 1, + .init = ps2_nvr_init, + .close = ps2_nvr_close, + .reset = NULL, + { .available = NULL }, + .speed_changed = NULL, + .force_redraw = NULL, + .config = NULL +};