i686 MSR's C1 to C4 are all implemented now.
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10
src/cpu.c
10
src/cpu.c
@@ -104,10 +104,10 @@ uint64_t mtrr_fix16k_a000_msr = 0;
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uint64_t mtrr_fix4k_msr[8] = {0, 0, 0, 0, 0, 0, 0, 0};
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uint64_t pat_msr = 0;
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uint64_t mtrr_deftype_msr = 0;
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uint64_t msr_ia32_pmc[4] = {0, 0, 0, 0};
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uint64_t ecx17_msr = 0;
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uint64_t ecx79_msr = 0;
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uint64_t ecx8x_msr[4] = {0, 0, 0, 0};
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uint64_t ecxc2_msr = 0;
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uint64_t ecx116_msr = 0;
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uint64_t ecx11x_msr[4] = {0, 0, 0, 0};
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uint64_t ecx11e_msr = 0;
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@@ -1989,6 +1989,10 @@ void cpu_RDMSR()
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EAX = ecx8x_msr[ECX - 0x88] & 0xffffffff;
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EDX = ecx8x_msr[ECX - 0x88] >> 32;
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break;
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case 0xC1 ... 0xC4:
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EAX = msr_ia32_pmc[ECX - 0xC1] & 0xffffffff;
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EDX = msr_ia32_pmc[ECX - 0xC1] >> 32;
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break;
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case 0xC2:
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EAX = ecxc2_msr & 0xffffffff;
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EDX = ecxc2_msr >> 32;
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@@ -2188,8 +2192,8 @@ void cpu_WRMSR()
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case 0x88 ... 0x8B:
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ecx8x_msr[ECX - 0x88] = EAX | ((uint64_t)EDX << 32);
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break;
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case 0xC2:
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ecxc2_msr = EAX | ((uint64_t)EDX << 32);
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case 0xC1 ... 0xC4:
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msr_ia32_pmc[ECX - 0xC1] = EAX | ((uint64_t)EDX << 32);
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break;
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case 0xFE:
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mtrr_cap_msr = EAX | ((uint64_t)EDX << 32);
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