From 5f3c976fbe9ab58dfa942ad80ba6e75a579c553d Mon Sep 17 00:00:00 2001 From: tiseno100 <58827426+tiseno100@users.noreply.github.com> Date: Sat, 12 Sep 2020 15:01:20 +0300 Subject: [PATCH 1/9] Some final touches on the Intel 82335 Most I could potentially implement are now complete - Added some commentary - switched some complex algorithms into definitions for the sake of the code being clean - Implemented the ROM size determination register just for some Shadow RAM sanity --- src/chipset/intel_82335.c | 46 ++++++++++++++++++++++++++++++--------- 1 file changed, 36 insertions(+), 10 deletions(-) diff --git a/src/chipset/intel_82335.c b/src/chipset/intel_82335.c index 7b1db6777..5d1485807 100644 --- a/src/chipset/intel_82335.c +++ b/src/chipset/intel_82335.c @@ -31,16 +31,25 @@ #include <86box/port_92.h> #include <86box/chipset.h> +/* Shadow capabilities */ #define disabled_shadow (MEM_READ_EXTANY | MEM_WRITE_EXTANY) #define rw_shadow (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) #define ro_shadow (MEM_READ_INTERNAL | MEM_WRITE_DISABLED) -#define extended_granuality_enabled (dev->regs[0x2c] & 0x01) +/* Granularity Register Enable & Recalc */ +#define extended_granularity_enabled (dev->regs[0x2c] & 0x01) +#define granularity_recalc ((dev->regs[0x2e] & (1 << (i+8))) ? ((dev->regs[0x2e] & (1 << i)) ? ro_shadow : rw_shadow) : disabled_shadow) + +/* R/W operator for the Video RAM region */ #define determine_video_ram_write_access ((dev->regs[0x22] & (0x08 << 8)) ? rw_shadow : ro_shadow) +/* Base System 512/640KB switch */ #define enable_top_128kb (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) #define disable_top_128kb (MEM_READ_DISABLED | MEM_WRITE_DISABLED) +/* ROM size determination */ +#define rom_size ((dev->regs[0x22] & (0x01 << 8)) ? 0xe0000 : 0xf0000) + typedef struct { @@ -71,10 +80,11 @@ static void intel_82335_write(uint16_t addr, uint16_t val, void *priv) { intel_82335_t *dev = (intel_82335_t *) priv; - uint32_t base, i; + uint32_t romsize = 0, base = 0, i = 0; dev->regs[addr] = val; + /* Unlock/Lock configuration registers */ dev->cfg_locked = (dev->regs[0x22] & (0x80 << 8)); if(!dev->cfg_locked) @@ -83,23 +93,39 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv) intel_82335_log("Register %02x: Write %04x\n", addr, val); switch (addr) { - case 0x22: - if (!extended_granuality_enabled) + case 0x22: /* Memory Controller */ + + /* Check if the ROM chips are 256 or 512Kbit (Just for Shadowing sanity) */ + romsize = rom_size; + + if (!extended_granularity_enabled) { + shadowbios = (dev->regs[0x22] & 0x01); + shadowbios_write = (dev->regs[0x22] & 0x01); + + /* Base System 512/640KB set */ mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? enable_top_128kb : disable_top_128kb); + + /* Video RAM shadow*/ mem_set_mem_state_both(0xa0000, 0x20000, (dev->regs[0x22] & (0x04 << 8)) ? determine_video_ram_write_access : disabled_shadow); + + /* Option ROM shadow */ mem_set_mem_state_both(0xc0000, 0x20000, (dev->regs[0x22] & (0x02 << 8)) ? rw_shadow : disabled_shadow); + + /* System ROM shadow */ mem_set_mem_state_both(0xe0000, 0x20000, (dev->regs[0x22] & 0x01) ? rw_shadow : disabled_shadow); } break; - case 0x2e: - if(extended_granuality_enabled) + case 0x2e: /* Extended Granularity (Enabled if Bit 0 in Register 2Ch is set) */ + if(extended_granularity_enabled) { for(i=0; i<8; i++) { base = 0xc0000 + (i << 15); - mem_set_mem_state_both(base, 0x8000, (dev->regs[0x2e] & (1 << (i+8))) ? ((dev->regs[0x2e] & (1 << i)) ? ro_shadow : rw_shadow) : disabled_shadow); + shadowbios = (dev->regs[0x2e] & (1 << (i+8))) && (base == romsize); + shadowbios_write = (dev->regs[0x2e] & (1 << i)) && (base == romsize); + mem_set_mem_state_both(base, 0x8000, granularity_recalc); } break; } @@ -114,7 +140,7 @@ intel_82335_read(uint16_t addr, void *priv) { intel_82335_t *dev = (intel_82335_t *) priv; - intel_82335_log("Register %02x: Reading\n", addr); + intel_82335_log("Register %02x: Read %04x\n", addr, dev->regs[addr]); return dev->regs[addr]; @@ -153,10 +179,10 @@ intel_82335_init(const device_t *info) io_sethandler(0x0028, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev); io_sethandler(0x002a, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev); - /* Granuality Enable */ + /* granularity Enable */ io_sethandler(0x002c, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev); - /* Extended Granuality */ + /* Extended granularity */ io_sethandler(0x002e, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev); return dev; From 07cd6e09942324d1d01e569b6a195a8bd77b26e9 Mon Sep 17 00:00:00 2001 From: tiseno100 <58827426+tiseno100@users.noreply.github.com> Date: Sat, 12 Sep 2020 15:02:52 +0300 Subject: [PATCH 2/9] A tiny change on the commentary --- src/chipset/intel_82335.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/chipset/intel_82335.c b/src/chipset/intel_82335.c index 5d1485807..23ad69f22 100644 --- a/src/chipset/intel_82335.c +++ b/src/chipset/intel_82335.c @@ -179,7 +179,7 @@ intel_82335_init(const device_t *info) io_sethandler(0x0028, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev); io_sethandler(0x002a, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev); - /* granularity Enable */ + /* Granularity Enable */ io_sethandler(0x002c, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev); /* Extended granularity */ From 1dd64678f72aac8187c66879c0d3c245bebbc1a3 Mon Sep 17 00:00:00 2001 From: tiseno100 <58827426+tiseno100@users.noreply.github.com> Date: Sun, 13 Sep 2020 16:23:09 +0300 Subject: [PATCH 3/9] Cap definition names --- src/chipset/intel_82335.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/src/chipset/intel_82335.c b/src/chipset/intel_82335.c index 23ad69f22..c892bcd08 100644 --- a/src/chipset/intel_82335.c +++ b/src/chipset/intel_82335.c @@ -32,23 +32,23 @@ #include <86box/chipset.h> /* Shadow capabilities */ -#define disabled_shadow (MEM_READ_EXTANY | MEM_WRITE_EXTANY) -#define rw_shadow (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) -#define ro_shadow (MEM_READ_INTERNAL | MEM_WRITE_DISABLED) +#define DISABLED_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY) +#define RW_SHADOW (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) +#define RO_SHADOW (MEM_READ_INTERNAL | MEM_WRITE_DISABLED) /* Granularity Register Enable & Recalc */ -#define extended_granularity_enabled (dev->regs[0x2c] & 0x01) -#define granularity_recalc ((dev->regs[0x2e] & (1 << (i+8))) ? ((dev->regs[0x2e] & (1 << i)) ? ro_shadow : rw_shadow) : disabled_shadow) +#define EXTENDED_GRANULARITY_ENABLED (dev->regs[0x2c] & 0x01) +#define GRANULARITY_RECALC ((dev->regs[0x2e] & (1 << (i+8))) ? ((dev->regs[0x2e] & (1 << i)) ? RO_SHADOW : RW_SHADOW) : DISABLED_SHADOW) /* R/W operator for the Video RAM region */ -#define determine_video_ram_write_access ((dev->regs[0x22] & (0x08 << 8)) ? rw_shadow : ro_shadow) +#define DETERMINE_VIDEO_RAM_WRITE_ACCESS ((dev->regs[0x22] & (0x08 << 8)) ? RW_SHADOW : RO_SHADOW) /* Base System 512/640KB switch */ -#define enable_top_128kb (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) -#define disable_top_128kb (MEM_READ_DISABLED | MEM_WRITE_DISABLED) +#define ENABLE_TOP_128KB (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) +#define DISABLE_TOP_128KB (MEM_READ_DISABLED | MEM_WRITE_DISABLED) /* ROM size determination */ -#define rom_size ((dev->regs[0x22] & (0x01 << 8)) ? 0xe0000 : 0xf0000) +#define ROM_SIZE ((dev->regs[0x22] & (0x01 << 8)) ? 0xe0000 : 0xf0000) typedef struct { @@ -96,36 +96,36 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv) case 0x22: /* Memory Controller */ /* Check if the ROM chips are 256 or 512Kbit (Just for Shadowing sanity) */ - romsize = rom_size; + romsize = ROM_SIZE; - if (!extended_granularity_enabled) + if (!EXTENDED_GRANULARITY_ENABLED) { shadowbios = (dev->regs[0x22] & 0x01); shadowbios_write = (dev->regs[0x22] & 0x01); /* Base System 512/640KB set */ - mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? enable_top_128kb : disable_top_128kb); + mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? ENABLE_TOP_128KB : DISABLE_TOP_128KB); /* Video RAM shadow*/ - mem_set_mem_state_both(0xa0000, 0x20000, (dev->regs[0x22] & (0x04 << 8)) ? determine_video_ram_write_access : disabled_shadow); + mem_set_mem_state_both(0xa0000, 0x20000, (dev->regs[0x22] & (0x04 << 8)) ? DETERMINE_VIDEO_RAM_WRITE_ACCESS : DISABLED_SHADOW); /* Option ROM shadow */ - mem_set_mem_state_both(0xc0000, 0x20000, (dev->regs[0x22] & (0x02 << 8)) ? rw_shadow : disabled_shadow); + mem_set_mem_state_both(0xc0000, 0x20000, (dev->regs[0x22] & (0x02 << 8)) ? RW_SHADOW : DISABLED_SHADOW); /* System ROM shadow */ - mem_set_mem_state_both(0xe0000, 0x20000, (dev->regs[0x22] & 0x01) ? rw_shadow : disabled_shadow); + mem_set_mem_state_both(0xe0000, 0x20000, (dev->regs[0x22] & 0x01) ? RW_SHADOW : DISABLED_SHADOW); } break; case 0x2e: /* Extended Granularity (Enabled if Bit 0 in Register 2Ch is set) */ - if(extended_granularity_enabled) + if(EXTENDED_GRANULARITY_ENABLED) { for(i=0; i<8; i++) { base = 0xc0000 + (i << 15); shadowbios = (dev->regs[0x2e] & (1 << (i+8))) && (base == romsize); shadowbios_write = (dev->regs[0x2e] & (1 << i)) && (base == romsize); - mem_set_mem_state_both(base, 0x8000, granularity_recalc); + mem_set_mem_state_both(base, 0x8000, GRANULARITY_RECALC); } break; } From 270b58585485e127c03e63ca1382c8a9bfccd53a Mon Sep 17 00:00:00 2001 From: tiseno100 <58827426+tiseno100@users.noreply.github.com> Date: Mon, 14 Sep 2020 13:18:29 +0300 Subject: [PATCH 4/9] Fixed some shadow issues on the Intel 82335 The lock register determines also if Shadowing is RW or RO. --- src/chipset/intel_82335.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/src/chipset/intel_82335.c b/src/chipset/intel_82335.c index c892bcd08..cabdadcd2 100644 --- a/src/chipset/intel_82335.c +++ b/src/chipset/intel_82335.c @@ -31,8 +31,11 @@ #include <86box/port_92.h> #include <86box/chipset.h> +#define ENABLE_INTEL_82335_LOG 1 + /* Shadow capabilities */ #define DISABLED_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY) +#define ENABLED_SHADOW ((LOCK_STATUS) ? RO_SHADOW : RW_SHADOW) #define RW_SHADOW (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) #define RO_SHADOW (MEM_READ_INTERNAL | MEM_WRITE_DISABLED) @@ -45,11 +48,14 @@ /* Base System 512/640KB switch */ #define ENABLE_TOP_128KB (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) -#define DISABLE_TOP_128KB (MEM_READ_DISABLED | MEM_WRITE_DISABLED) +#define DISABLE_TOP_128KB (MEM_READ_EXTANY | MEM_WRITE_EXTANY) /* ROM size determination */ #define ROM_SIZE ((dev->regs[0x22] & (0x01 << 8)) ? 0xe0000 : 0xf0000) +/* Lock status */ +#define LOCK_STATUS (dev->regs[0x22] & (0x80 << 8)) + typedef struct { @@ -84,9 +90,6 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv) dev->regs[addr] = val; - /* Unlock/Lock configuration registers */ - dev->cfg_locked = (dev->regs[0x22] & (0x80 << 8)); - if(!dev->cfg_locked) { @@ -110,10 +113,10 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv) mem_set_mem_state_both(0xa0000, 0x20000, (dev->regs[0x22] & (0x04 << 8)) ? DETERMINE_VIDEO_RAM_WRITE_ACCESS : DISABLED_SHADOW); /* Option ROM shadow */ - mem_set_mem_state_both(0xc0000, 0x20000, (dev->regs[0x22] & (0x02 << 8)) ? RW_SHADOW : DISABLED_SHADOW); + mem_set_mem_state_both(0xc0000, 0x20000, (dev->regs[0x22] & (0x02 << 8)) ? ENABLED_SHADOW : DISABLED_SHADOW); /* System ROM shadow */ - mem_set_mem_state_both(0xe0000, 0x20000, (dev->regs[0x22] & 0x01) ? RW_SHADOW : DISABLED_SHADOW); + mem_set_mem_state_both(0xe0000, 0x20000, (dev->regs[0x22] & 0x01) ? ENABLED_SHADOW : DISABLED_SHADOW); } break; @@ -132,6 +135,9 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv) } } + /* Unlock/Lock configuration registers */ + dev->cfg_locked = LOCK_STATUS; + } @@ -182,7 +188,7 @@ intel_82335_init(const device_t *info) /* Granularity Enable */ io_sethandler(0x002c, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev); - /* Extended granularity */ + /* Extended Granularity */ io_sethandler(0x002e, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev); return dev; From a364b10a51cc8125f1e344026bff322a0cb3b7d0 Mon Sep 17 00:00:00 2001 From: tiseno100 <58827426+tiseno100@users.noreply.github.com> Date: Mon, 14 Sep 2020 13:20:19 +0300 Subject: [PATCH 5/9] Disabled logging once again -_- --- src/chipset/intel_82335.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/chipset/intel_82335.c b/src/chipset/intel_82335.c index cabdadcd2..b0fe93b4c 100644 --- a/src/chipset/intel_82335.c +++ b/src/chipset/intel_82335.c @@ -31,8 +31,6 @@ #include <86box/port_92.h> #include <86box/chipset.h> -#define ENABLE_INTEL_82335_LOG 1 - /* Shadow capabilities */ #define DISABLED_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY) #define ENABLED_SHADOW ((LOCK_STATUS) ? RO_SHADOW : RW_SHADOW) From e5de57cffb75f0d9b6f980e5a551cfdf9d5739de Mon Sep 17 00:00:00 2001 From: tiseno100 <58827426+tiseno100@users.noreply.github.com> Date: Mon, 14 Sep 2020 13:24:34 +0300 Subject: [PATCH 6/9] Removed Port 92h off the Intel 82335 The chipset doesn't seem to use it. --- src/chipset/intel_82335.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/chipset/intel_82335.c b/src/chipset/intel_82335.c index b0fe93b4c..7b19bf9db 100644 --- a/src/chipset/intel_82335.c +++ b/src/chipset/intel_82335.c @@ -28,7 +28,6 @@ #include <86box/mem.h> #include <86box/fdd.h> #include <86box/fdc.h> -#include <86box/port_92.h> #include <86box/chipset.h> /* Shadow capabilities */ @@ -165,7 +164,6 @@ intel_82335_init(const device_t *info) intel_82335_t *dev = (intel_82335_t *) malloc(sizeof(intel_82335_t)); memset(dev, 0, sizeof(intel_82335_t)); - device_add(&port_92_device); memset(dev->regs, 0, sizeof(dev->regs)); dev->regs[0x28] = 0xf9; From 8464883e224bcec62641e76b00d5d097cf75ae2c Mon Sep 17 00:00:00 2001 From: tiseno100 <58827426+tiseno100@users.noreply.github.com> Date: Wed, 16 Sep 2020 17:52:09 +0300 Subject: [PATCH 7/9] Brute set configuration on the Intel 82335 Fixes the ADI 386SX freezing while booting an OS when shadowing is on. --- src/chipset/intel_82335.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/chipset/intel_82335.c b/src/chipset/intel_82335.c index 7b19bf9db..661454232 100644 --- a/src/chipset/intel_82335.c +++ b/src/chipset/intel_82335.c @@ -134,7 +134,6 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv) /* Unlock/Lock configuration registers */ dev->cfg_locked = LOCK_STATUS; - } @@ -164,11 +163,7 @@ intel_82335_init(const device_t *info) intel_82335_t *dev = (intel_82335_t *) malloc(sizeof(intel_82335_t)); memset(dev, 0, sizeof(intel_82335_t)); - memset(dev->regs, 0, sizeof(dev->regs)); - - dev->regs[0x28] = 0xf9; - - dev->cfg_locked = 1; + dev->cfg_locked = 0; /* Memory Configuration */ io_sethandler(0x0022, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev); @@ -187,6 +182,12 @@ intel_82335_init(const device_t *info) /* Extended Granularity */ io_sethandler(0x002e, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev); + /* Default Programming(Fixes Shadowing failures on the ADI 386SX) */ + for(uint16_t i=0x0022; i<0x002f; i=i+0x0002) + intel_82335_write(i, 0x0000, dev); + + intel_82335_write(0x0028, 0x00f9, dev); + return dev; } From 280e69fb0cf059e9bc52d2e273f4595e221da9c3 Mon Sep 17 00:00:00 2001 From: tiseno100 <58827426+tiseno100@users.noreply.github.com> Date: Wed, 16 Sep 2020 17:59:33 +0300 Subject: [PATCH 8/9] Revert changes. Keep the humane methods of initialization on the Intel 82335. The issue with the ADI was caused by the incorrect lock status on early initialization. --- src/chipset/intel_82335.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/chipset/intel_82335.c b/src/chipset/intel_82335.c index 661454232..f8b145bb8 100644 --- a/src/chipset/intel_82335.c +++ b/src/chipset/intel_82335.c @@ -163,6 +163,10 @@ intel_82335_init(const device_t *info) intel_82335_t *dev = (intel_82335_t *) malloc(sizeof(intel_82335_t)); memset(dev, 0, sizeof(intel_82335_t)); + memset(dev->regs, 0, sizeof(dev->regs)); + + dev->regs[0x28] = 0xf9; + dev->cfg_locked = 0; /* Memory Configuration */ @@ -182,12 +186,6 @@ intel_82335_init(const device_t *info) /* Extended Granularity */ io_sethandler(0x002e, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev); - /* Default Programming(Fixes Shadowing failures on the ADI 386SX) */ - for(uint16_t i=0x0022; i<0x002f; i=i+0x0002) - intel_82335_write(i, 0x0000, dev); - - intel_82335_write(0x0028, 0x00f9, dev); - return dev; } From 99b60d642231f260e7a5034a375e209f755a8987 Mon Sep 17 00:00:00 2001 From: tiseno100 <58827426+tiseno100@users.noreply.github.com> Date: Thu, 17 Sep 2020 18:57:52 +0300 Subject: [PATCH 9/9] Delete mcr.c There's no need for that anymore. --- src/chipset/mcr.c | 38 -------------------------------------- 1 file changed, 38 deletions(-) delete mode 100644 src/chipset/mcr.c diff --git a/src/chipset/mcr.c b/src/chipset/mcr.c deleted file mode 100644 index ec1931882..000000000 --- a/src/chipset/mcr.c +++ /dev/null @@ -1,38 +0,0 @@ -/*INTEL 82355 MCR emulation - This chip was used as part of many 386 chipsets - It controls memory addressing and shadowing*/ -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/mem.h> - - -int nextreg6; -uint8_t mcr22; -int mcrlock,mcrfirst; - - -void resetmcr(void) -{ - mcrlock=0; - mcrfirst=1; - shadowbios=0; -} - -void writemcr(uint16_t addr, uint8_t val) -{ - switch (addr) - { - case 0x22: - if (val==6 && mcr22==6) nextreg6=1; - else nextreg6=0; - break; - case 0x23: - if (nextreg6) shadowbios=!val; - break; - } - mcr22=val; -} -