diff --git a/src/chipset/amd640.c b/src/chipset/amd640.c deleted file mode 100644 index 4cb8625f1..000000000 --- a/src/chipset/amd640.c +++ /dev/null @@ -1,230 +0,0 @@ -/* -* -* 86Box: A hypervisor and IBM PC system emulator that specializes in -* running old operating systems and software designed for IBM -* PC systems and compatibles from 1981 through fairly recent -* system designs based on the PCI bus. -* -* -* -* Basic AMD 640 North Bridge emulation -* -* Looks similar to the VIA VP2 -* while it's southbridge(AMD-645) is just a 586B [TODO: Probs write it if it has differences] -* -* Copyright(C) 2020 Tiseno100 -* -*/ - - -#include -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/mem.h> -#include <86box/io.h> -#include <86box/rom.h> -#include <86box/pci.h> -#include <86box/device.h> -#include <86box/keyboard.h> -#include <86box/chipset.h> - -typedef struct amd640_t { - uint8_t regs[256]; -} amd640_t; - -static void -amd640_map(uint32_t addr, uint32_t size, int state) -{ - switch (state & 3) { - case 0: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - break; - case 1: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - break; - case 2: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); - break; - case 3: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - break; - } - - flushmmucache_nopc(); -} - -static void -amd640_write(int func, int addr, uint8_t val, void *priv) -{ - amd640_t *dev = (amd640_t *) priv; - - /* Read-Only Registers */ - switch(addr){ - case 0x00: case 0x01: case 0x08: case 0x09: - case 0x0a: case 0x0b: case 0x0c: case 0x0e: - case 0x0f: - return; - } - - switch(addr){ - - /* Command */ - case 0x04: - dev->regs[0x04] = (dev->regs[0x04] & ~0x40) | (val & 0x40); - - /* Status */ - case 0x07: - dev->regs[0x07] &= ~(val & 0xb0); - break; - - /* Shadow RAM registers */ - case 0x61: - if ((dev->regs[0x61] ^ val) & 0x03) - amd640_map(0xc0000, 0x04000, val & 0x03); - if ((dev->regs[0x61] ^ val) & 0x0c) - amd640_map(0xc4000, 0x04000, (val & 0x0c) >> 2); - if ((dev->regs[0x61] ^ val) & 0x30) - amd640_map(0xc8000, 0x04000, (val & 0x30) >> 4); - if ((dev->regs[0x61] ^ val) & 0xc0) - amd640_map(0xcc000, 0x04000, (val & 0xc0) >> 6); - dev->regs[0x61] = val; - return; - - case 0x62: - if ((dev->regs[0x62] ^ val) & 0x03) - amd640_map(0xd0000, 0x04000, val & 0x03); - if ((dev->regs[0x62] ^ val) & 0x0c) - amd640_map(0xd4000, 0x04000, (val & 0x0c) >> 2); - if ((dev->regs[0x62] ^ val) & 0x30) - amd640_map(0xd8000, 0x04000, (val & 0x30) >> 4); - if ((dev->regs[0x62] ^ val) & 0xc0) - amd640_map(0xdc000, 0x04000, (val & 0xc0) >> 6); - dev->regs[0x62] = val; - return; - - case 0x63: - if ((dev->regs[0x63] ^ val) & 0x30) { - amd640_map(0xf0000, 0x10000, (val & 0x30) >> 4); - shadowbios = (((val & 0x30) >> 4) & 0x02); - } - if ((dev->regs[0x63] ^ val) & 0xc0) - amd640_map(0xe0000, 0x10000, (val & 0xc0) >> 6); - dev->regs[0x63] = val; - return; - - case 0x65: /* DRAM Control Register #1 */ - dev->regs[0x65] = (dev->regs[0x65] & ~0x20) | (val & 0x20); - - case 0x66: /* DRAM Control Register #2 */ - dev->regs[0x66] = (dev->regs[0x66] & ~0x05) | (val & 0x05); - - case 0x67: /* 32-Bit DRAM Width Control Register */ - dev->regs[0x67] = (dev->regs[0x67] & ~0xc0) | (val & 0xc0); - - case 0x68: /* Reserved (But referenced by the BIOS?) */ - dev->regs[0x68] = (dev->regs[0x68] & ~0x40) | (val & 0x40); - - case 0x6d: /* DRAM Drive Strength Control Register */ - dev->regs[0x6d] = (dev->regs[0x6d] & ~0x6f) | (val & 0x6f); - - case 0x70: /* PCI Buffer Control Register */ - dev->regs[0x70] = (dev->regs[0x70] & ~0x01) | (val & 0x01); - - case 0x71: /* Processor-to-PCI Control Register #1 */ - dev->regs[0x71] = (dev->regs[0x71] & ~0x4e) | (val & 0x4e); - - case 0x73: /* PCI Initiator Control Register #1 */ - dev->regs[0x73] = (dev->regs[0x73] & ~0x0c) | (val & 0x0c); - - case 0x75: /* PCI Arbitration Control Register #1 */ - dev->regs[0x75] = (dev->regs[0x75] & ~0xc7) | (val & 0xc7); - - default: - dev->regs[addr] = val; - break; - } -} - -static uint8_t -amd640_read(int func, int addr, void *priv) -{ - amd640_t *dev = (amd640_t *) priv; - uint8_t ret = 0xff; - - if(func == 0){ - ret = dev->regs[addr]; - } - - return ret; -} - -static void -amd640_reset(void *priv) -{ - amd640_write(0, 0x63, amd640_read(0, 0x63, priv) & 0xcf, priv); -} - - -static void * -amd640_init(const device_t *info) -{ - amd640_t *dev = (amd640_t *) malloc(sizeof(amd640_t)); - - pci_add_card(PCI_ADD_NORTHBRIDGE, amd640_read, amd640_write, dev); - - dev->regs[0x00] = 0x06; /* AMD */ - dev->regs[0x01] = 0x11; - - dev->regs[0x02] = 0x95; /* 640 */ - dev->regs[0x03] = 0x15; - - dev->regs[0x04] = 7; /* Command */ - - dev->regs[0x06] = 0xa0; /* Status */ - dev->regs[0x07] = 2; - - dev->regs[0x08] = 0x02; /* Revision ID: 0x02 = D, 0x03 = E, 0x04 = F */ - - dev->regs[0x0b] = 6; /* Base Class Code */ - - dev->regs[0x52] = 2; /* Non-Cacheable control */ - - dev->regs[0x58] = 0x40; /* DRAM Configuration register 1 */ - dev->regs[0x59] = 5; /* DRAM Configuration register 2 */ - - /* DRAM Bank Endings */ - dev->regs[0x5a] = 1; - dev->regs[0x5b] = 1; - dev->regs[0x5c] = 1; - dev->regs[0x5d] = 1; - dev->regs[0x5e] = 1; - dev->regs[0x5f] = 1; - - dev->regs[0x64] = 0xab; - - return dev; -} - -static void -amd640_close(void *priv) -{ - amd640_t *dev = (amd640_t *) priv; - - free(dev); -} - -const device_t amd640_device = { - "AMD-640 System Controller", - DEVICE_PCI, - 0, - amd640_init, - amd640_close, - amd640_reset, - NULL, - NULL, - NULL, - NULL -}; \ No newline at end of file diff --git a/src/chipset/via_apollo.c b/src/chipset/via_apollo.c index 79b57b8c5..37e14f4cd 100644 --- a/src/chipset/via_apollo.c +++ b/src/chipset/via_apollo.c @@ -35,6 +35,8 @@ #include <86box/chipset.h> #include <86box/spd.h> +#define VIA_585 0x05850000 +#define VIA_595 0x05950000 #define VIA_597 0x05970100 #define VIA_598 0x05980000 #define VIA_691 0x06910000 @@ -96,7 +98,11 @@ via_apollo_setup(via_apollo_t *dev) dev->pci_conf[0x04] = 6; dev->pci_conf[0x05] = 0; + if ((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x06] = 0xa0; + else dev->pci_conf[0x06] = 0x90; + dev->pci_conf[0x07] = 0x02; dev->pci_conf[0x08] = dev->id >> 8; @@ -107,21 +113,34 @@ via_apollo_setup(via_apollo_t *dev) dev->pci_conf[0x0d] = 0; dev->pci_conf[0x0e] = 0; dev->pci_conf[0x0f] = 0; + + if (dev->id >= VIA_597) + { dev->pci_conf[0x10] = 0x08; dev->pci_conf[0x34] = 0xa0; + } - if ((dev->id >= VIA_694)) + if ((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x52] = 0x02; + else if (dev->id >= VIA_694) dev->pci_conf[0x52] = (dev->id == VIA_694) ? 0x90 : 0x10; - if ((dev->id >= VIA_693A)) + if(dev->id >= VIA_693A) dev->pci_conf[0x53] = 0x10; if (dev->id == VIA_691) { dev->pci_conf[0x56] = 0x01; dev->pci_conf[0x57] = 0x01; } + if (dev->id >= VIA_693A) dev->pci_conf[0x58] = 0x40; + else if (dev->id >= VIA_585) + dev->pci_conf[0x58] = 0x05; + + if ((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x59] = 0x02; + dev->pci_conf[0x5a] = 0x01; dev->pci_conf[0x5b] = 0x01; dev->pci_conf[0x5c] = 0x01; @@ -129,13 +148,18 @@ via_apollo_setup(via_apollo_t *dev) dev->pci_conf[0x5e] = 0x01; dev->pci_conf[0x5f] = 0x01; - dev->pci_conf[0x64] = 0xec; + dev->pci_conf[0x64] = ((dev->id >= VIA_585) || (dev->id < VIA_597)) ? 0xab : 0xec; + if (dev->id >= VIA_597) + { dev->pci_conf[0x65] = 0xec; dev->pci_conf[0x66] = 0xec; - if (dev->id >= VIA_691) + } + if (dev->id >= VIA_691) dev->pci_conf[0x67] = 0xec; /* DRAM Timing for Banks 6,7. */ dev->pci_conf[0x6b] = 0x01; + if(dev->id >= VIA_597) + { dev->pci_conf[0xa0] = 0x02; dev->pci_conf[0xa2] = 0x10; dev->pci_conf[0xa4] = 0x03; @@ -151,6 +175,7 @@ via_apollo_setup(via_apollo_t *dev) dev->pci_conf[0xb0] = 0x80; /* The datasheet refers it as 8xh */ dev->pci_conf[0xb1] = 0x63; } + } } @@ -158,7 +183,7 @@ static void via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) { via_apollo_t *dev = (via_apollo_t *) priv; - + pclog("%02x: %02x\n", addr, val); if (func) return; @@ -180,6 +205,14 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) case 0x04: dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x40) | (val & 0x40); break; + + case 0x05: + if((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x05] = (dev->pci_conf[0x05] & ~0x03) | (val & 0x03); + else + dev->pci_conf[0x05] = val; + break; + case 0x07: dev->pci_conf[0x07] &= ~(val & 0xb0); break; @@ -194,6 +227,12 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) dev->pci_conf[0x75] = (dev->pci_conf[0x75] & ~0x30) | ((val & 0x06) << 3); break; + case 0x0f: + if((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x0f] = (dev->pci_conf[0x0f] & ~0xcf) | (val & 0x0cf); + else + dev->pci_conf[0x0f] = val; + break; case 0x12: /* Graphics Aperture Base */ dev->pci_conf[0x12] = (val & 0xf0); break; @@ -206,7 +245,9 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xd3) | (val & 0xd3); else if (dev->id >= VIA_693A) dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xd1) | (val & 0xd1); - else if (dev->id == VIA_691) + else if (dev->id == VIA_595) + dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xfb) | (val & 0xfb); + else if ((dev->id == VIA_585) || (dev->id == VIA_691)) dev->pci_conf[0x50] = val; else dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xf8) | (val & 0xf8); @@ -218,6 +259,8 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0xd9) | (val & 0xd9); else if (dev->id >= VIA_691) dev->pci_conf[0x51] = val; + else if ((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0x2b) | (val & 0x2b); else dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0xeb) | (val & 0xeb); break; @@ -236,12 +279,15 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) dev->pci_conf[0x53] = (dev->pci_conf[0x53] & ~0xfc) | (val & 0xfc); else if ((dev->id == VIA_691) || (dev->id == VIA_694)) dev->pci_conf[0x53] = val; - else if (dev->id == VIA_693A) + else if ((dev->id >= VIA_585) || (dev->id < VIA_597) || (dev->id == VIA_693A)) dev->pci_conf[0x53] = (dev->pci_conf[0x53] & ~0xf8) | (val & 0xf8); else dev->pci_conf[0x53] = (dev->pci_conf[0x53] & ~0xf0) | (val & 0xf0); break; case 0x54: + if(dev->id == VIA_585) + dev->pci_conf[0x54] = val; + else dev->pci_conf[0x54] = (dev->pci_conf[0x54] & ~0x07) | (val & 0x07); break; @@ -253,7 +299,7 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) break; case 0x58: - if ((dev->id == VIA_597) || ((dev->id >= VIA_693A) || (dev->id < VIA_8601))) + if ((dev->id >= VIA_585) || (dev->id < VIA_597) || (dev->id == VIA_597) || ((dev->id >= VIA_693A) || (dev->id < VIA_8601))) dev->pci_conf[0x58] = (dev->pci_conf[0x58] & ~0xee) | (val & 0xee); else dev->pci_conf[0x58] = val; @@ -263,6 +309,8 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) dev->pci_conf[0x59] = (dev->pci_conf[0x59] & ~0xee) | (val & 0xee); else if (dev->id == VIA_691) dev->pci_conf[0x59] = val; + else if ((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x59] = (dev->pci_conf[0x59] & ~0xe7) | (val & 0xe7); else dev->pci_conf[0x59] = (dev->pci_conf[0x59] & ~0xf0) | (val & 0xf0); break; @@ -316,7 +364,7 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */ apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3); /* Non-SMM: Code Invalid, Data Invalid */ break; - } else switch (val & 0x03) { + } else if(dev->id >= VIA_597) switch (val & 0x03) { case 0x00: default: /* Disable SMI Address Redirection (default) */ @@ -348,29 +396,74 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) apollo_smram_map(dev, 1, 0x00030000, 0x00020000, 1); apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); break; + } else switch(val & 0x03) { + case 0x00: + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 0); + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); + break; + case 0x01: + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); + break; + case 0x02: + apollo_smram_map(dev, 1, 0x00030000, 0x00020000, 1); + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3); + break; + case 0x03: + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 1); + apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 3); + apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3); + break; } break; + case 0x65: + if (dev->id == VIA_585) + dev->pci_conf[0x65] = (dev->pci_conf[0x65] & ~0xfd) | (val & 0xfd); + else if (dev->id == VIA_595) + dev->pci_conf[0x65] = (dev->pci_conf[0x65] & ~0xf9) | (val & 0xf9); + else + dev->pci_conf[0x65] = val; + break; + case 0x66: + if (dev->id == VIA_585) + dev->pci_conf[0x66] = (dev->pci_conf[0x66] & ~0xaf) | (val & 0xaf); + else if (dev->id == VIA_595) + dev->pci_conf[0x66] = (dev->pci_conf[0x66] & ~0x8f) | (val & 0x8f); + else + dev->pci_conf[0x66] = val; + break; case 0x68: + if(dev->id != VIA_595){ if (dev->id == VIA_597) dev->pci_conf[0x68] = (dev->pci_conf[0x6b] & ~0xfe) | (val & 0xfe); else if ((dev->id == VIA_598) || (dev->id == VIA_693A) || (dev->id == VIA_8601)) dev->pci_conf[0x68] = val; else if (dev->id == VIA_694) dev->pci_conf[0x68] = (dev->pci_conf[0x68] & ~0xdf) | (val & 0xdf); + else if (dev->id == VIA_585) + dev->pci_conf[0x68] = (dev->pci_conf[0x68] & ~0x08) | (val & 0x08); else dev->pci_conf[0x68] = (dev->pci_conf[0x6b] & ~0xfd) | (val & 0xfd); break; + } case 0x69: + if((dev->id != VIA_585) || (dev->id != VIA_595)){ if ((dev->id == VIA_693A) || (dev->id < VIA_8601)) dev->pci_conf[0x69] = (dev->pci_conf[0x69] & ~0xfe) | (val & 0xfe); else dev->pci_conf[0x69] = val; + } break; case 0x6b: if ((dev->id == VIA_693A) || (dev->id < VIA_8601)) dev->pci_conf[0x6b] = val; else if (dev->id == VIA_691) dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xcf) | (val & 0xcf); + else if (dev->id == VIA_595) + dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xc0) | (val & 0xc0); + else if (dev->id == VIA_585) + dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xc4) | (val & 0xc4); else dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xc1) | (val & 0xc1); break; @@ -379,6 +472,8 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) dev->pci_conf[0x6c] = (dev->pci_conf[0x6c] & ~0x1f) | (val & 0x1f); else if (dev->id == VIA_598) dev->pci_conf[0x6c] = (dev->pci_conf[0x6c] & ~0x7f) | (val & 0x7f); + else if (dev->id == VIA_585) + dev->pci_conf[0x6c] = (dev->pci_conf[0x6c] & ~0xef) | (val & 0xef); else dev->pci_conf[0x6c] = val; break; @@ -391,7 +486,7 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) dev->pci_conf[0x6d] = val; break; case 0x6e: - if(dev->id == VIA_694) + if((dev->id == VIA_595) || (dev->id == VIA_694)) dev->pci_conf[0x6e] = val; else dev->pci_conf[0x6e] = (dev->pci_conf[0x6e] & ~0xb7) | (val & 0xb7); @@ -402,18 +497,22 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) dev->pci_conf[0x70] = (dev->pci_conf[0x70] & ~0xdf) | (val & 0xdf); else if (dev->id == VIA_597) dev->pci_conf[0x70] = (dev->pci_conf[0x70] & ~0xf1) | (val & 0xf1); + else if ((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x70] = (dev->pci_conf[0x70] & ~0xe3) | (val & 0xe3); else dev->pci_conf[0x70] = val; break; case 0x71: - if(dev->id == VIA_694) + if((dev->id >= VIA_585) || (dev->id == VIA_694)) dev->pci_conf[0x71] = (dev->pci_conf[0x71] & ~0xdf) | (val & 0xdf); else dev->pci_conf[0x71] = val; break; case 0x73: - if ((dev->id >= VIA_693A)) + if (dev->id >= VIA_693A) dev->pci_conf[0x73] = (dev->pci_conf[0x73] & ~0x7f) | (val & 0x7f); + else if ((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x73] = (dev->pci_conf[0x73] & ~0xef) | (val & 0xef); else dev->pci_conf[0x73] = val; break; @@ -433,7 +532,9 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv) break; case 0x76: if (dev->id >= VIA_693A) - dev->pci_conf[0x75] = val; + dev->pci_conf[0x76] = val; + else if ((dev->id >= VIA_585) || (dev->id < VIA_597)) + dev->pci_conf[0x76] = (dev->pci_conf[0x76] & ~0xb0) | (val & 0xb0); else dev->pci_conf[0x76] = (dev->pci_conf[0x76] & ~0xf0) | (val & 0xf0); break; @@ -607,6 +708,33 @@ via_apollo_close(void *priv) free(dev); } +const device_t via_vpx_device = +{ + "VIA Apollo VPX", + DEVICE_PCI, + VIA_597, /*VT82C585*/ + via_apollo_init, + via_apollo_close, + via_apollo_reset, + NULL, + NULL, + NULL, + NULL +}; + +const device_t amd640_device = +{ + "AMD 640 System Controller", + DEVICE_PCI, + VIA_597, /*VT82C595*/ + via_apollo_init, + via_apollo_close, + via_apollo_reset, + NULL, + NULL, + NULL, + NULL +}; const device_t via_vp3_device = { diff --git a/src/chipset/via_vpx.c b/src/chipset/via_vpx.c deleted file mode 100644 index 87f7e94e6..000000000 --- a/src/chipset/via_vpx.c +++ /dev/null @@ -1,234 +0,0 @@ -/* -* -* 86Box A hypervisor and IBM PC system emulator that specializes in -* running old operating systems and software designed for IBM -* PC systems and compatibles from 1981 through fairly recent -* system designs based on the PCI bus. -* -* -* -* VIA Apollo VPX North Bridge emulation -* -* VT82C585VPX used in the FIC VA-502 board -* based on the model of VIA MVP3 by mooch & Sarah -* -* There's also a SOYO board using the ETEQ chipset which is a rebranded -* VPX + 586B but fails to save on CMOS properly. -* -* Authors: Sarah Walker, -* Copyright(C) 2020 Tiseno100 -* Copyright(C) 2020 Melissa Goad -* Copyright(C) 2020 Miran Grca -* -*/ - -#include -#include -#include -#include -#include -#include <86box/86box.h> -#include <86box/mem.h> -#include <86box/io.h> -#include <86box/rom.h> -#include <86box/pci.h> -#include <86box/device.h> -#include <86box/keyboard.h> -#include <86box/chipset.h> -#include <86box/spd.h> - -typedef struct via_vpx_t -{ - uint8_t pci_conf[256]; -} via_vpx_t; - -static void -vpx_map(uint32_t addr, uint32_t size, int state) -{ - switch (state & 3) { - case 0: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - break; - case 1: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - break; - case 2: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); - break; - case 3: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - break; - } - - flushmmucache_nopc(); -} - -static void -via_vpx_write(int func, int addr, uint8_t val, void *priv) -{ - -via_vpx_t *dev = (via_vpx_t *) priv; - - // Read-Only registers - switch(addr){ - case 0x00: case 0x01: case 0x02: case 0x03: - case 0x08: case 0x09: case 0x0a: case 0x0b: - case 0x0e: case 0x0f: - return; - } - - switch(addr){ - case 0x04: - // Bitfield 6: Parity Error Response - // Bitfield 8: SERR# Enable - // Bitfield 9: Fast Back-to-Back Cycle Enable - if(dev->pci_conf[0x04] && 0x40){ //Bitfield 6 - dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x40) | (val & 0x40); - } else if(dev->pci_conf[0x04] && 0x100){ //Bitfield 8 - dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x100) | (val & 0x100); - } else if(dev->pci_conf[0x04] && 0x200){ //Bitfield 9 - dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x200) | (val & 0x200); - } - break; - - case 0x07: // Status - dev->pci_conf[0x07] &= ~(val & 0xb0); - break; - - case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f: // Bank Ending - spd_write_drbs(dev->pci_conf, 0x5a, 0x5f, 4); - break; - - case 0x61: // Shadow RAM control 1 - if ((dev->pci_conf[0x61] ^ val) & 0x03) - vpx_map(0xc0000, 0x04000, val & 0x03); - if ((dev->pci_conf[0x61] ^ val) & 0x0c) - vpx_map(0xc4000, 0x04000, (val & 0x0c) >> 2); - if ((dev->pci_conf[0x61] ^ val) & 0x30) - vpx_map(0xc8000, 0x04000, (val & 0x30) >> 4); - if ((dev->pci_conf[0x61] ^ val) & 0xc0) - vpx_map(0xcc000, 0x04000, (val & 0xc0) >> 6); - dev->pci_conf[0x61] = val; - return; - - case 0x62: // Shadow RAM Control 2 - if ((dev->pci_conf[0x62] ^ val) & 0x03) - vpx_map(0xd0000, 0x04000, val & 0x03); - if ((dev->pci_conf[0x62] ^ val) & 0x0c) - vpx_map(0xd4000, 0x04000, (val & 0x0c) >> 2); - if ((dev->pci_conf[0x62] ^ val) & 0x30) - vpx_map(0xd8000, 0x04000, (val & 0x30) >> 4); - if ((dev->pci_conf[0x62] ^ val) & 0xc0) - vpx_map(0xdc000, 0x04000, (val & 0xc0) >> 6); - dev->pci_conf[0x62] = val; - return; - - case 0x63: // Shadow RAM Control 3 - if ((dev->pci_conf[0x63] ^ val) & 0x30) { - vpx_map(0xf0000, 0x10000, (val & 0x30) >> 4); - shadowbios = (((val & 0x30) >> 4) & 0x02); - } - if ((dev->pci_conf[0x63] ^ val) & 0xc0) - vpx_map(0xe0000, 0x10000, (val & 0xc0) >> 6); - dev->pci_conf[0x63] = val; - return; - - default: - dev->pci_conf[addr] = val; - break; - } -} - -static uint8_t -via_vpx_read(int func, int addr, void *priv) -{ - via_vpx_t *dev = (via_vpx_t *) priv; - uint8_t ret = 0xff; - - switch(func) { - case 0: - ret = dev->pci_conf[addr]; - break; - } - - return ret; -} - -static void -via_vpx_reset(void *priv) -{ - via_vpx_write(0, 0x63, via_vpx_read(0, 0x63, priv) & 0xcf, priv); -} - -static void * -via_vpx_init(const device_t *info) -{ - via_vpx_t *dev = (via_vpx_t *) malloc(sizeof(via_vpx_t)); - memset(dev, 0, sizeof(via_vpx_t)); - - pci_add_card(PCI_ADD_NORTHBRIDGE, via_vpx_read, via_vpx_write, dev); - - dev->pci_conf[0x00] = 0x06; // VIA - dev->pci_conf[0x01] = 0x11; - - dev->pci_conf[0x02] = 0x85; // VT82C585VPX - dev->pci_conf[0x03] = 0x05; - - dev->pci_conf[0x04] = 7; // Command - dev->pci_conf[0x05] = 0; - - dev->pci_conf[0x06] = 0xa0; // Status - dev->pci_conf[0x07] = 2; - - dev->pci_conf[0x08] = 0; // Silicon Rev. - - dev->pci_conf[0x09] = 0; // Program Interface - - dev->pci_conf[0x0a] = 0; // Sub Class Code - - dev->pci_conf[0x0b] = 6; // Base Class Code - - dev->pci_conf[0x0c] = 0; // reserved - - dev->pci_conf[0x0d] = 0; // Latency Timer - - dev->pci_conf[0x0e] = 0; // Header Type - - dev->pci_conf[0x0f] = 0; // Built-in Self test - - dev->pci_conf[0x58] = 0x40; // DRAM Configuration 1 - dev->pci_conf[0x59] = 0x05; // DRAM Configuration 2 - - dev->pci_conf[0x5a] = 1; // Bank 0 Ending - dev->pci_conf[0x5b] = 1; // Bank 1 Ending - dev->pci_conf[0x5c] = 1; // Bank 2 Ending - dev->pci_conf[0x5d] = 1; // Bank 3 Ending - dev->pci_conf[0x5e] = 1; // Bank 4 Ending - dev->pci_conf[0x5f] = 1; // Bank 5 Ending - - dev->pci_conf[0x60] = 0x3f; // DRAM type - dev->pci_conf[0x64] = 0xab; // DRAM reference timing - - return dev; -} - -static void -via_vpx_close(void *priv) -{ - via_vpx_t *dev = (via_vpx_t *) priv; - - free(dev); -} - -const device_t via_vpx_device = { - "VIA Apollo VPX", - DEVICE_PCI, - 0, - via_vpx_init, - via_vpx_close, - via_vpx_reset, - NULL, - NULL, - NULL, - NULL -}; \ No newline at end of file diff --git a/src/include/86box/flash.h b/src/include/86box/flash.h index d1efee32b..43274e367 100644 --- a/src/include/86box/flash.h +++ b/src/include/86box/flash.h @@ -24,3 +24,4 @@ extern const device_t sst_flash_29ee010_device; extern const device_t sst_flash_29ee020_device; extern const device_t sst_flash_39sf010_device; extern const device_t sst_flash_39sf020_device; +extern const device_t sst_flash_39sf040_device; \ No newline at end of file diff --git a/src/mem/intel_flash.c b/src/mem/intel_flash.c index d6a625ab7..9f4f50ea7 100644 --- a/src/mem/intel_flash.c +++ b/src/mem/intel_flash.c @@ -40,6 +40,8 @@ enum { BLOCK_MAIN1, BLOCK_MAIN2, + BLOCK_MAIN3, + BLOCK_MAIN4, BLOCK_DATA1, BLOCK_DATA2, BLOCK_BOOT, @@ -171,7 +173,9 @@ flash_write(uint32_t addr, uint8_t val, void *p) flash_t *dev = (flash_t *) p; int i; uint32_t bb_mask = biosmask & 0xffffe000; - if (biosmask == 0x3ffff) + if (biosmask == 0x7ffff) + bb_mask &= 0xffff8000; + else if (biosmask == 0x3ffff) bb_mask &= 0xffffc000; if (dev->flags & FLAG_INV_A16) @@ -220,7 +224,9 @@ flash_writew(uint32_t addr, uint16_t val, void *p) flash_t *dev = (flash_t *) p; int i; uint32_t bb_mask = biosmask & 0xffffe000; - if (biosmask == 0x3ffff) + if (biosmask == 0x7ffff) + bb_mask &= 0xffff8000; + else if (biosmask == 0x3ffff) bb_mask &= 0xffffc000; if (dev->flags & FLAG_INV_A16) @@ -280,16 +286,23 @@ intel_flash_add_mappings(flash_t *dev) uint32_t base, fbase; uint32_t sub = 0x20000; - if (biosmask == 0x3ffff) { + if (biosmask == 0x7ffff) { + sub = 0x80000; + max = 8; + } + else if (biosmask == 0x3ffff) { sub = 0x40000; max = 4; - } + } for (i = 0; i < max; i++) { - if (biosmask == 0x3ffff) + if (biosmask == 0x7ffff) + base = 0x80000 + (i << 16); + else if (biosmask == 0x3ffff) base = 0xc0000 + (i << 16); else base = 0xe0000 + (i << 16); + fbase = base & biosmask; if (dev->flags & FLAG_INV_A16) fbase ^= 0x10000; @@ -356,7 +369,57 @@ intel_flash_init(const device_t *info) dev->array = (uint8_t *) malloc(biosmask + 1); memset(dev->array, 0xff, biosmask + 1); - if (biosmask == 0x3ffff) { + switch(biosmask){ + case 0x7ffff: + + if (dev->flags & FLAG_WORD) + dev->flash_id = (dev->flags & FLAG_BXB) ? 0x4471 :0x4470; + else + dev->flash_id =(dev->flags & FLAG_BXB) ? 0x8A : 0x89; + + /* The block lengths are the same both flash types. */ + dev->block_len[BLOCK_MAIN1] = 0x20000; + dev->block_len[BLOCK_MAIN2] = 0x20000; + dev->block_len[BLOCK_MAIN3] = 0x20000; + dev->block_len[BLOCK_MAIN4] = 0x18000; + dev->block_len[BLOCK_DATA1] = 0x02000; + dev->block_len[BLOCK_DATA2] = 0x02000; + dev->block_len[BLOCK_BOOT] = 0x04000; + + if (dev->flags & FLAG_BXB) { /* 28F004BX-T/28F400BX-B */ + dev->block_start[BLOCK_BOOT] = 0x00000; /* MAIN BLOCK 1 */ + dev->block_end[BLOCK_BOOT] = 0x1ffff; + dev->block_start[BLOCK_DATA2] = 0x20000; /* MAIN BLOCK 2 */ + dev->block_end[BLOCK_DATA2] = 0x3ffff; + dev->block_start[BLOCK_DATA1] = 0x40000; /* MAIN BLOCK 3 */ + dev->block_end[BLOCK_DATA1] = 0x5ffff; + dev->block_start[BLOCK_MAIN4] = 0x60000; /* MAIN BLOCK 4 */ + dev->block_end[BLOCK_MAIN4] = 0x77fff; + dev->block_start[BLOCK_MAIN3] = 0x78000; /* DATA AREA 1 BLOCK */ + dev->block_end[BLOCK_MAIN3] = 0x79fff; + dev->block_start[BLOCK_MAIN2] = 0x7a000; /* DATA AREA 2 BLOCK */ + dev->block_end[BLOCK_MAIN2] = 0x7bfff; + dev->block_start[BLOCK_MAIN1] = 0x7c000; /* BOOT BLOCK */ + dev->block_end[BLOCK_MAIN1] = 0x7ffff; + } else { + dev->block_start[BLOCK_MAIN1] = 0x00000; /* MAIN BLOCK 1 */ + dev->block_end[BLOCK_MAIN1] = 0x1ffff; + dev->block_start[BLOCK_MAIN2] = 0x20000; /* MAIN BLOCK 2 */ + dev->block_end[BLOCK_MAIN2] = 0x3ffff; + dev->block_start[BLOCK_MAIN3] = 0x40000; /* MAIN BLOCK 3 */ + dev->block_end[BLOCK_MAIN3] = 0x5ffff; + dev->block_start[BLOCK_MAIN4] = 0x60000; /* MAIN BLOCK 4 */ + dev->block_end[BLOCK_MAIN4] = 0x77fff; + dev->block_start[BLOCK_DATA1] = 0x78000; /* DATA AREA 1 BLOCK */ + dev->block_end[BLOCK_DATA1] = 0x79fff; + dev->block_start[BLOCK_DATA2] = 0x7a000; /* DATA AREA 2 BLOCK */ + dev->block_end[BLOCK_DATA2] = 0x7bfff; + dev->block_start[BLOCK_BOOT] = 0x7c000; /* BOOT BLOCK */ + dev->block_end[BLOCK_BOOT] = 0x7ffff; + } + break; + + case 0x3ffff: if (dev->flags & FLAG_WORD) dev->flash_id = (dev->flags & FLAG_BXB) ? 0x2275 : 0x2274; else @@ -392,7 +455,9 @@ intel_flash_init(const device_t *info) dev->block_start[BLOCK_BOOT] = 0x3c000; /* BOOT BLOCK */ dev->block_end[BLOCK_BOOT] = 0x3ffff; } - } else { + break; + + default: dev->flash_id = (type & FLAG_BXB) ? 0x95 : 0x94; /* The block lengths are the same both flash types. */ @@ -425,7 +490,8 @@ intel_flash_init(const device_t *info) dev->block_start[BLOCK_BOOT] = 0x1e000; /* BOOT BLOCK */ dev->block_end[BLOCK_BOOT] = 0x1ffff; } - } + break; + } intel_flash_add_mappings(dev); @@ -437,6 +503,11 @@ intel_flash_init(const device_t *info) fread(&(dev->array[dev->block_start[BLOCK_MAIN1]]), dev->block_len[BLOCK_MAIN1], 1, f); if (dev->block_len[BLOCK_MAIN2]) fread(&(dev->array[dev->block_start[BLOCK_MAIN2]]), dev->block_len[BLOCK_MAIN2], 1, f); + else if (dev->block_len[BLOCK_MAIN3]) + fread(&(dev->array[dev->block_start[BLOCK_MAIN3]]), dev->block_len[BLOCK_MAIN3], 1, f); + else if (dev->block_len[BLOCK_MAIN4]) + fread(&(dev->array[dev->block_start[BLOCK_MAIN4]]), dev->block_len[BLOCK_MAIN4], 1, f); + fread(&(dev->array[dev->block_start[BLOCK_DATA1]]), dev->block_len[BLOCK_DATA1], 1, f); fread(&(dev->array[dev->block_start[BLOCK_DATA2]]), dev->block_len[BLOCK_DATA2], 1, f); fclose(f); @@ -459,6 +530,11 @@ intel_flash_close(void *p) fwrite(&(dev->array[dev->block_start[BLOCK_MAIN1]]), dev->block_len[BLOCK_MAIN1], 1, f); if (dev->block_len[BLOCK_MAIN2]) fwrite(&(dev->array[dev->block_start[BLOCK_MAIN2]]), dev->block_len[BLOCK_MAIN2], 1, f); + else if (dev->block_len[BLOCK_MAIN3]) + fwrite(&(dev->array[dev->block_start[BLOCK_MAIN3]]), dev->block_len[BLOCK_MAIN3], 1, f); + else if (dev->block_len[BLOCK_MAIN4]) + fwrite(&(dev->array[dev->block_start[BLOCK_MAIN4]]), dev->block_len[BLOCK_MAIN4], 1, f); + fwrite(&(dev->array[dev->block_start[BLOCK_DATA1]]), dev->block_len[BLOCK_DATA1], 1, f); fwrite(&(dev->array[dev->block_start[BLOCK_DATA2]]), dev->block_len[BLOCK_DATA2], 1, f); fclose(f); @@ -473,7 +549,7 @@ intel_flash_close(void *p) /* For AMI BIOS'es - Intel 28F001BXT with A16 pin inverted. */ const device_t intel_flash_bxt_ami_device = { - "Intel 28F001BXT/28F002BXT Flash BIOS", + "Intel 28F001BXT/28F002BXT/28F004BXT Flash BIOS", DEVICE_PCI, FLAG_INV_A16, intel_flash_init, @@ -485,7 +561,7 @@ const device_t intel_flash_bxt_ami_device = const device_t intel_flash_bxt_device = { - "Intel 28F001BXT/28F002BXT Flash BIOS", + "Intel 28F001BXT/28F002BXT/28F004BXT Flash BIOS", DEVICE_PCI, 0, intel_flash_init, intel_flash_close, @@ -496,7 +572,7 @@ const device_t intel_flash_bxt_device = const device_t intel_flash_bxb_device = { - "Intel 28F001BXB/28F002BXB Flash BIOS", + "Intel 28F001BXB/28F002BXB/28F004BXB Flash BIOS", DEVICE_PCI, FLAG_BXB, intel_flash_init, intel_flash_close, diff --git a/src/mem/sst_flash.c b/src/mem/sst_flash.c index 646412f94..1c73e8bd3 100644 --- a/src/mem/sst_flash.c +++ b/src/mem/sst_flash.c @@ -472,3 +472,14 @@ const device_t sst_flash_39sf020_device = NULL, NULL, NULL, NULL, NULL }; + +const device_t sst_flash_39sf040_device = +{ + "SST 39SF040 Flash BIOS", + 0, + SST_ID_SST39SF040, + sst_init, + sst_close, + NULL, + NULL, NULL, NULL, NULL +}; diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw index baf949c5c..921666ed0 100644 --- a/src/win/Makefile.mingw +++ b/src/win/Makefile.mingw @@ -663,8 +663,7 @@ CHIPSETOBJ := acc2168.o cs8230.o ali1429.o headland.o intel_82335.o cs4031.o \ intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \ neat.o opti495.o opti895.o opti5x7.o scamp.o scat.o via_vt82c49x.o via_vt82c505.o \ sis_85c310.o sis_85c4xx.o sis_85c496.o opti283.o opti291.o umc491.o \ - via_apollo.o via_vpx.o via_pipc.o wd76c10.o vl82c480.o \ - amd640.o + via_apollo.o via_pipc.o wd76c10.o vl82c480.o MCHOBJ := machine.o machine_table.o \ m_xt.o m_xt_compaq.o \