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Some clang-formatting in src/cpu

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This commit is contained in:
Jasmine Iwanek
2022-09-20 01:00:45 -04:00
parent b2fb6dbeec
commit b4673117fd
6 changed files with 5424 additions and 5271 deletions
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72
src/cpu/386.c
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@@ -25,14 +25,12 @@
#include <86box/gdbstub.h> #include <86box/gdbstub.h>
#include "386_common.h" #include "386_common.h"
#ifdef USE_NEW_DYNAREC #ifdef USE_NEW_DYNAREC
#include "codegen.h" # include "codegen.h"
#endif #endif
#undef CPU_BLOCK_END #undef CPU_BLOCK_END
#define CPU_BLOCK_END() #define CPU_BLOCK_END()
extern int codegen_flags_changed; extern int codegen_flags_changed;
int tempc, oldcpl, optype, inttype, oddeven = 0; int tempc, oldcpl, optype, inttype, oddeven = 0;
@@ -48,11 +46,9 @@ uint32_t backupregs[16];
x86seg _oldds; x86seg _oldds;
#ifdef ENABLE_386_LOG #ifdef ENABLE_386_LOG
int x386_do_log = ENABLE_386_LOG; int x386_do_log = ENABLE_386_LOG;
void void
x386_log(const char *fmt, ...) x386_log(const char *fmt, ...)
{ {
@@ -65,49 +61,54 @@ x386_log(const char *fmt, ...)
} }
} }
#else #else
#define x386_log(fmt, ...) # define x386_log(fmt, ...)
#endif #endif
#undef CPU_BLOCK_END #undef CPU_BLOCK_END
#define CPU_BLOCK_END() #define CPU_BLOCK_END()
#include "x86_flags.h" #include "x86_flags.h"
#define getbytef() ((uint8_t)(fetchdat)); cpu_state.pc++ #define getbytef() \
#define getwordf() ((uint16_t)(fetchdat)); cpu_state.pc+=2 ((uint8_t) (fetchdat)); \
#define getbyte2f() ((uint8_t)(fetchdat>>8)); cpu_state.pc++ cpu_state.pc++
#define getword2f() ((uint16_t)(fetchdat>>8)); cpu_state.pc+=2 #define getwordf() \
((uint16_t) (fetchdat)); \
cpu_state.pc += 2
#define getbyte2f() \
((uint8_t) (fetchdat >> 8)); \
cpu_state.pc++
#define getword2f() \
((uint16_t) (fetchdat >> 8)); \
cpu_state.pc += 2
#define OP_TABLE(name) ops_##name
#define OP_TABLE(name) ops_ ## name
#if 0 #if 0
#define CLOCK_CYCLES(c) \ # define CLOCK_CYCLES(c) \
{\ { \
if (fpu_cycles > 0) {\ if (fpu_cycles > 0) { \
fpu_cycles -= (c);\ fpu_cycles -= (c); \
if (fpu_cycles < 0) {\ if (fpu_cycles < 0) { \
cycles += fpu_cycles;\ cycles += fpu_cycles; \
}\ } \
} else {\ } else { \
cycles -= (c);\ cycles -= (c); \
}\ } \
} }
#define CLOCK_CYCLES_FPU(c) cycles -= (c) # define CLOCK_CYCLES_FPU(c) cycles -= (c)
#define CONCURRENCY_CYCLES(c) fpu_cycles = (c) # define CONCURRENCY_CYCLES(c) fpu_cycles = (c)
#else #else
#define CLOCK_CYCLES(c) cycles -= (c) # define CLOCK_CYCLES(c) cycles -= (c)
#define CLOCK_CYCLES_FPU(c) cycles -= (c) # define CLOCK_CYCLES_FPU(c) cycles -= (c)
#define CONCURRENCY_CYCLES(c) # define CONCURRENCY_CYCLES(c)
#endif #endif
#define CLOCK_CYCLES_ALWAYS(c) cycles -= (c) #define CLOCK_CYCLES_ALWAYS(c) cycles -= (c)
#include "x86_ops.h" #include "x86_ops.h"
void void
exec386(int cycs) exec386(int cycs)
{ {
@@ -118,7 +119,7 @@ exec386(int cycs)
cycles += cycs; cycles += cycs;
while (cycles > 0) { while (cycles > 0) {
cycle_period = (timer_target - (uint32_t)tsc) + 1; cycle_period = (timer_target - (uint32_t) tsc) + 1;
x86_was_reset = 0; x86_was_reset = 0;
cycdiff = 0; cycdiff = 0;
@@ -127,8 +128,8 @@ exec386(int cycs)
ins_cycles = cycles; ins_cycles = cycles;
#ifndef USE_NEW_DYNAREC #ifndef USE_NEW_DYNAREC
oldcs=CS; oldcs = CS;
oldcpl=CPL; oldcpl = CPL;
#endif #endif
cpu_state.oldpc = cpu_state.pc; cpu_state.oldpc = cpu_state.pc;
cpu_state.op32 = use32; cpu_state.op32 = use32;
@@ -162,7 +163,8 @@ exec386(int cycs)
#endif #endif
#ifndef USE_NEW_DYNAREC #ifndef USE_NEW_DYNAREC
if (!use32) cpu_state.pc &= 0xffff; if (!use32)
cpu_state.pc &= 0xffff;
#endif #endif
if (cpu_end_block_after_ins) if (cpu_end_block_after_ins)
@@ -197,8 +199,8 @@ exec386(int cycs)
else if (trap) { else if (trap) {
flags_rebuild(); flags_rebuild();
dr[6] |= 0x4000; dr[6] |= 0x4000;
if (msw&1) if (msw & 1)
pmodeint(1,0); pmodeint(1, 0);
else { else {
writememw(ss, (SP - 2) & 0xFFFF, cpu_state.flags); writememw(ss, (SP - 2) & 0xFFFF, cpu_state.flags);
writememw(ss, (SP - 4) & 0xFFFF, CS); writememw(ss, (SP - 4) & 0xFFFF, CS);

491
src/cpu/808x.c
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File diff suppressed because it is too large Load Diff

420
src/cpu/cpu.c
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@@ -49,7 +49,6 @@
#define CCR3_SMI_LOCK (1 << 0) #define CCR3_SMI_LOCK (1 << 0)
#define CCR3_NMI_EN (1 << 1) #define CCR3_NMI_EN (1 << 1)
enum { enum {
CPUID_FPU = (1 << 0), CPUID_FPU = (1 << 0),
CPUID_VME = (1 << 1), CPUID_VME = (1 << 1),
@@ -71,7 +70,6 @@ enum {
/*Addition flags returned by CPUID function 0x80000001*/ /*Addition flags returned by CPUID function 0x80000001*/
#define CPUID_3DNOW (1UL << 31UL) #define CPUID_3DNOW (1UL << 31UL)
/* Make sure this is as low as possible. */ /* Make sure this is as low as possible. */
cpu_state_t cpu_state; cpu_state_t cpu_state;
@@ -102,7 +100,7 @@ const OpFn *x86_opcodes, *x86_opcodes_0f,
*x86_opcodes_3DNOW; *x86_opcodes_3DNOW;
uint16_t cpu_fast_off_count, cpu_fast_off_val; uint16_t cpu_fast_off_count, cpu_fast_off_val;
uint16_t temp_seg_data[4] = {0, 0, 0, 0}; uint16_t temp_seg_data[4] = { 0, 0, 0, 0 };
int isa_cycles, cpu_inited, int isa_cycles, cpu_inited,
@@ -127,12 +125,12 @@ int isa_cycles, cpu_inited,
timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate, timing_misaligned; timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate, timing_misaligned;
uint32_t cpu_features, cpu_fast_off_flags; uint32_t cpu_features, cpu_fast_off_flags;
uint32_t _tr[8] = {0, 0, 0, 0, 0, 0, 0, 0}; uint32_t _tr[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
uint32_t cache_index = 0; uint32_t cache_index = 0;
uint8_t _cache[2048]; uint8_t _cache[2048];
uint64_t cpu_CR4_mask, tsc = 0; uint64_t cpu_CR4_mask, tsc = 0;
uint64_t pmc[2] = {0, 0}; uint64_t pmc[2] = { 0, 0 };
double cpu_dmulti; double cpu_dmulti;
@@ -147,20 +145,16 @@ uint8_t do_translate = 0, do_translate2 = 0;
void (*cpu_exec)(int cycs); void (*cpu_exec)(int cycs);
static uint8_t ccr0, ccr1, ccr2, ccr3, ccr4, ccr5, ccr6; static uint8_t ccr0, ccr1, ccr2, ccr3, ccr4, ccr5, ccr6;
static int cyrix_addr; static int cyrix_addr;
static void cpu_write(uint16_t addr, uint8_t val, void *priv); static void cpu_write(uint16_t addr, uint8_t val, void *priv);
static uint8_t cpu_read(uint16_t addr, void *priv); static uint8_t cpu_read(uint16_t addr, void *priv);
#ifdef ENABLE_CPU_LOG #ifdef ENABLE_CPU_LOG
int cpu_do_log = ENABLE_CPU_LOG; int cpu_do_log = ENABLE_CPU_LOG;
void void
cpu_log(const char *fmt, ...) cpu_log(const char *fmt, ...)
{ {
@@ -173,17 +167,15 @@ cpu_log(const char *fmt, ...)
} }
} }
#else #else
#define cpu_log(fmt, ...) # define cpu_log(fmt, ...)
#endif #endif
int int
cpu_has_feature(int feature) cpu_has_feature(int feature)
{ {
return cpu_features & feature; return cpu_features & feature;
} }
void void
cpu_dynamic_switch(int new_cpu) cpu_dynamic_switch(int new_cpu)
{ {
@@ -199,14 +191,12 @@ cpu_dynamic_switch(int new_cpu)
cpu = c; cpu = c;
} }
void void
cpu_set_edx(void) cpu_set_edx(void)
{ {
EDX = cpu_s->edx_reset; EDX = cpu_s->edx_reset;
} }
cpu_family_t * cpu_family_t *
cpu_get_family(const char *internal_name) cpu_get_family(const char *internal_name)
{ {
@@ -221,7 +211,6 @@ cpu_get_family(const char *internal_name)
return NULL; return NULL;
} }
uint8_t uint8_t
cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine) cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
{ {
@@ -295,11 +284,9 @@ cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
/* K6-2+ / K6-3+ */ /* K6-2+ / K6-3+ */
else if ((cpu_s->cpu_type == CPU_K6_2P) || (cpu_s->cpu_type == CPU_K6_3P)) else if ((cpu_s->cpu_type == CPU_K6_2P) || (cpu_s->cpu_type == CPU_K6_3P))
multi = 2.5; multi = 2.5;
else if (((cpu_s->cpu_type == CPU_WINCHIP) || (cpu_s->cpu_type == CPU_WINCHIP2)) && else if (((cpu_s->cpu_type == CPU_WINCHIP) || (cpu_s->cpu_type == CPU_WINCHIP2)) && (machine_s->cpu.min_multi > 2.0)) /* WinChip (2) */
(machine_s->cpu.min_multi > 2.0)) /* WinChip (2) */
multi = 2.5; multi = 2.5;
} } else if (multi == (7.0 / 3.0)) /* WinChip 2A - 2.33x */
else if (multi == (7.0 / 3.0)) /* WinChip 2A - 2.33x */
multi = 5.0; multi = 5.0;
else if (multi == (8.0 / 3.0)) /* WinChip 2A - 2.66x */ else if (multi == (8.0 / 3.0)) /* WinChip 2A - 2.66x */
multi = 5.5; multi = 5.5;
@@ -320,8 +307,7 @@ cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
multi = 4.5; multi = 4.5;
} else if ((cpu_s->cpu_type == CPU_Cx6x86) || (cpu_s->cpu_type == CPU_Cx6x86L)) /* 6x86(L) */ } else if ((cpu_s->cpu_type == CPU_Cx6x86) || (cpu_s->cpu_type == CPU_Cx6x86L)) /* 6x86(L) */
multi = 3.0; multi = 3.0;
} else if ((multi == 5.0) && ((cpu_s->cpu_type == CPU_WINCHIP) || (cpu_s->cpu_type == CPU_WINCHIP2)) && } else if ((multi == 5.0) && ((cpu_s->cpu_type == CPU_WINCHIP) || (cpu_s->cpu_type == CPU_WINCHIP2)) && (machine_s->cpu.min_multi > 5.0)) /* WinChip (2) */
(machine_s->cpu.min_multi > 5.0)) /* WinChip (2) */
multi = 5.5; multi = 5.5;
else if (multi == 6.0) /* K6-2(+) / K6-3(+) */ else if (multi == 6.0) /* K6-2(+) / K6-3(+) */
multi = 2.0; multi = 2.0;
@@ -338,7 +324,6 @@ cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
return 1; return 1;
} }
uint8_t uint8_t
cpu_family_is_eligible(const cpu_family_t *cpu_family, int machine) cpu_family_is_eligible(const cpu_family_t *cpu_family, int machine)
{ {
@@ -353,7 +338,6 @@ cpu_family_is_eligible(const cpu_family_t *cpu_family, int machine)
return 0; return 0;
} }
void void
cpu_set(void) cpu_set(void)
{ {
@@ -376,8 +360,7 @@ cpu_set(void)
is286 = (cpu_s->cpu_type >= CPU_286); is286 = (cpu_s->cpu_type >= CPU_286);
is386 = (cpu_s->cpu_type >= CPU_386SX); is386 = (cpu_s->cpu_type >= CPU_386SX);
israpidcad = (cpu_s->cpu_type == CPU_RAPIDCAD); israpidcad = (cpu_s->cpu_type == CPU_RAPIDCAD);
isibm486 = (cpu_s->cpu_type == CPU_IBM386SLC) || (cpu_s->cpu_type == CPU_IBM486SLC) || isibm486 = (cpu_s->cpu_type == CPU_IBM386SLC) || (cpu_s->cpu_type == CPU_IBM486SLC) || (cpu_s->cpu_type == CPU_IBM486BL);
(cpu_s->cpu_type == CPU_IBM486BL);
is486 = (cpu_s->cpu_type >= CPU_RAPIDCAD); is486 = (cpu_s->cpu_type >= CPU_RAPIDCAD);
is_am486 = (cpu_s->cpu_type == CPU_ENH_Am486DX); is_am486 = (cpu_s->cpu_type == CPU_ENH_Am486DX);
is_am486dxl = (cpu_s->cpu_type == CPU_Am486DXL); is_am486dxl = (cpu_s->cpu_type == CPU_Am486DXL);
@@ -389,24 +372,19 @@ cpu_set(void)
/* SL-Enhanced Intel 486s have the same SMM save state table layout as Pentiums, /* SL-Enhanced Intel 486s have the same SMM save state table layout as Pentiums,
and the WinChip datasheet claims those are Pentium-compatible as well. AMD Am486DXL/DXL2 also has compatible SMM, or would if not for it's different SMBase*/ and the WinChip datasheet claims those are Pentium-compatible as well. AMD Am486DXL/DXL2 also has compatible SMM, or would if not for it's different SMBase*/
is_pentium = (cpu_isintel && (cpu_s->cpu_type >= CPU_i486SX_SLENH) && (cpu_s->cpu_type < CPU_PENTIUMPRO)) || is_pentium = (cpu_isintel && (cpu_s->cpu_type >= CPU_i486SX_SLENH) && (cpu_s->cpu_type < CPU_PENTIUMPRO)) || !strcmp(cpu_f->manufacturer, "IDT") || (cpu_s->cpu_type == CPU_Am486DXL);
!strcmp(cpu_f->manufacturer, "IDT") || (cpu_s->cpu_type == CPU_Am486DXL);
is_k5 = !strcmp(cpu_f->manufacturer, "AMD") && (cpu_s->cpu_type > CPU_ENH_Am486DX) && (cpu_s->cpu_type < CPU_K6); is_k5 = !strcmp(cpu_f->manufacturer, "AMD") && (cpu_s->cpu_type > CPU_ENH_Am486DX) && (cpu_s->cpu_type < CPU_K6);
is_k6 = (cpu_s->cpu_type >= CPU_K6) && !strcmp(cpu_f->manufacturer, "AMD"); is_k6 = (cpu_s->cpu_type >= CPU_K6) && !strcmp(cpu_f->manufacturer, "AMD");
/* The Samuel 2 datasheet claims it's Celeron-compatible. */ /* The Samuel 2 datasheet claims it's Celeron-compatible. */
is_p6 = (cpu_isintel && (cpu_s->cpu_type >= CPU_PENTIUMPRO)) || !strcmp(cpu_f->manufacturer, "VIA"); is_p6 = (cpu_isintel && (cpu_s->cpu_type >= CPU_PENTIUMPRO)) || !strcmp(cpu_f->manufacturer, "VIA");
is_cxsmm = (!strcmp(cpu_f->manufacturer, "Cyrix") || !strcmp(cpu_f->manufacturer, "ST")) && is_cxsmm = (!strcmp(cpu_f->manufacturer, "Cyrix") || !strcmp(cpu_f->manufacturer, "ST")) && (cpu_s->cpu_type >= CPU_Cx486S);
(cpu_s->cpu_type >= CPU_Cx486S);
cpu_isintel = cpu_isintel || !strcmp(cpu_f->manufacturer, "AMD"); cpu_isintel = cpu_isintel || !strcmp(cpu_f->manufacturer, "AMD");
hasfpu = (fpu_type != FPU_NONE); hasfpu = (fpu_type != FPU_NONE);
hascache = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC) || hascache = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC) || (cpu_s->cpu_type == CPU_IBM486SLC) || (cpu_s->cpu_type == CPU_IBM486BL);
(cpu_s->cpu_type == CPU_IBM486SLC) || (cpu_s->cpu_type == CPU_IBM486BL);
cpu_16bitbus = (cpu_s->cpu_type == CPU_286) || (cpu_s->cpu_type == CPU_386SX) || cpu_16bitbus = (cpu_s->cpu_type == CPU_286) || (cpu_s->cpu_type == CPU_386SX) || (cpu_s->cpu_type == CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC) || (cpu_s->cpu_type == CPU_IBM486SLC);
(cpu_s->cpu_type == CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC) ||
(cpu_s->cpu_type == CPU_IBM486SLC);
cpu_64bitbus = (cpu_s->cpu_type >= CPU_WINCHIP); cpu_64bitbus = (cpu_s->cpu_type >= CPU_WINCHIP);
if (cpu_s->multi) if (cpu_s->multi)
@@ -1043,14 +1021,14 @@ cpu_set(void)
case CPU_CxGX1: case CPU_CxGX1:
case CPU_Cx6x86MX: case CPU_Cx6x86MX:
if (cpu_s->cpu_type == CPU_Cx6x86MX) { if (cpu_s->cpu_type == CPU_Cx6x86MX) {
#ifdef USE_DYNAREC # ifdef USE_DYNAREC
x86_dynarec_opcodes_da_a16 = dynarec_ops_fpu_686_da_a16; x86_dynarec_opcodes_da_a16 = dynarec_ops_fpu_686_da_a16;
x86_dynarec_opcodes_da_a32 = dynarec_ops_fpu_686_da_a32; x86_dynarec_opcodes_da_a32 = dynarec_ops_fpu_686_da_a32;
x86_dynarec_opcodes_db_a16 = dynarec_ops_fpu_686_db_a16; x86_dynarec_opcodes_db_a16 = dynarec_ops_fpu_686_db_a16;
x86_dynarec_opcodes_db_a32 = dynarec_ops_fpu_686_db_a32; x86_dynarec_opcodes_db_a32 = dynarec_ops_fpu_686_db_a32;
x86_dynarec_opcodes_df_a16 = dynarec_ops_fpu_686_df_a16; x86_dynarec_opcodes_df_a16 = dynarec_ops_fpu_686_df_a16;
x86_dynarec_opcodes_df_a32 = dynarec_ops_fpu_686_df_a32; x86_dynarec_opcodes_df_a32 = dynarec_ops_fpu_686_df_a32;
#endif # endif
x86_opcodes_da_a16 = ops_fpu_686_da_a16; x86_opcodes_da_a16 = ops_fpu_686_da_a16;
x86_opcodes_da_a32 = ops_fpu_686_da_a32; x86_opcodes_da_a32 = ops_fpu_686_da_a32;
x86_opcodes_db_a16 = ops_fpu_686_db_a16; x86_opcodes_db_a16 = ops_fpu_686_db_a16;
@@ -1059,7 +1037,7 @@ cpu_set(void)
x86_opcodes_df_a32 = ops_fpu_686_df_a32; x86_opcodes_df_a32 = ops_fpu_686_df_a32;
} }
#ifdef USE_DYNAREC # ifdef USE_DYNAREC
if (cpu_s->cpu_type == CPU_Cx6x86MX) if (cpu_s->cpu_type == CPU_Cx6x86MX)
x86_setopcodes(ops_386, ops_c6x86mx_0f, dynarec_ops_386, dynarec_ops_c6x86mx_0f); x86_setopcodes(ops_386, ops_c6x86mx_0f, dynarec_ops_386, dynarec_ops_c6x86mx_0f);
else if (cpu_s->cpu_type == CPU_Cx6x86L) else if (cpu_s->cpu_type == CPU_Cx6x86L)
@@ -1067,14 +1045,14 @@ cpu_set(void)
else else
x86_setopcodes(ops_386, ops_c6x86mx_0f, dynarec_ops_386, dynarec_ops_c6x86mx_0f); x86_setopcodes(ops_386, ops_c6x86mx_0f, dynarec_ops_386, dynarec_ops_c6x86mx_0f);
// x86_setopcodes(ops_386, ops_c6x86_0f, dynarec_ops_386, dynarec_ops_c6x86_0f); // x86_setopcodes(ops_386, ops_c6x86_0f, dynarec_ops_386, dynarec_ops_c6x86_0f);
#else # else
if (cpu_s->cpu_type == CPU_Cx6x86MX) if (cpu_s->cpu_type == CPU_Cx6x86MX)
x86_setopcodes(ops_386, ops_c6x86mx_0f); x86_setopcodes(ops_386, ops_c6x86mx_0f);
else if (cpu_s->cpu_type == CPU_Cx6x86L) else if (cpu_s->cpu_type == CPU_Cx6x86L)
x86_setopcodes(ops_386, ops_pentium_0f); x86_setopcodes(ops_386, ops_pentium_0f);
else else
x86_setopcodes(ops_386, ops_c6x86_0f); x86_setopcodes(ops_386, ops_c6x86_0f);
#endif # endif
timing_rr = 1; /* register dest - register src */ timing_rr = 1; /* register dest - register src */
timing_rm = 1; /* register dest - memory src */ timing_rm = 1; /* register dest - memory src */
@@ -1125,9 +1103,9 @@ cpu_set(void)
if (cpu_s->cpu_type >= CPU_CxGX1) if (cpu_s->cpu_type >= CPU_CxGX1)
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_PCE; cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_PCE;
#ifdef USE_DYNAREC # ifdef USE_DYNAREC
codegen_timing_set(&codegen_timing_686); codegen_timing_set(&codegen_timing_686);
#endif # endif
if ((cpu_s->cpu_type == CPU_Cx6x86L) || (cpu_s->cpu_type == CPU_Cx6x86MX)) if ((cpu_s->cpu_type == CPU_Cx6x86L) || (cpu_s->cpu_type == CPU_Cx6x86MX))
ccr4 = 0x80; ccr4 = 0x80;
@@ -1149,27 +1127,27 @@ cpu_set(void)
#ifdef USE_DYNAREC #ifdef USE_DYNAREC
if (cpu_s->cpu_type >= CPU_K6_2) if (cpu_s->cpu_type >= CPU_K6_2)
x86_setopcodes(ops_386, ops_k62_0f, dynarec_ops_386, dynarec_ops_k62_0f); x86_setopcodes(ops_386, ops_k62_0f, dynarec_ops_386, dynarec_ops_k62_0f);
#if defined(DEV_BRANCH) && defined(USE_AMD_K5) # if defined(DEV_BRANCH) && defined(USE_AMD_K5)
else if (cpu_s->cpu_type == CPU_K6) else if (cpu_s->cpu_type == CPU_K6)
x86_setopcodes(ops_386, ops_k6_0f, dynarec_ops_386, dynarec_ops_k6_0f); x86_setopcodes(ops_386, ops_k6_0f, dynarec_ops_386, dynarec_ops_k6_0f);
else else
x86_setopcodes(ops_386, ops_pentiummmx_0f, dynarec_ops_386, dynarec_ops_pentiummmx_0f); x86_setopcodes(ops_386, ops_pentiummmx_0f, dynarec_ops_386, dynarec_ops_pentiummmx_0f);
#else # else
else else
x86_setopcodes(ops_386, ops_k6_0f, dynarec_ops_386, dynarec_ops_k6_0f); x86_setopcodes(ops_386, ops_k6_0f, dynarec_ops_386, dynarec_ops_k6_0f);
#endif # endif
#else #else
if (cpu_s->cpu_type >= CPU_K6_2) if (cpu_s->cpu_type >= CPU_K6_2)
x86_setopcodes(ops_386, ops_k62_0f); x86_setopcodes(ops_386, ops_k62_0f);
#if defined(DEV_BRANCH) && defined(USE_AMD_K5) # if defined(DEV_BRANCH) && defined(USE_AMD_K5)
else if (cpu_s->cpu_type = CPU_K6) else if (cpu_s->cpu_type = CPU_K6)
x86_setopcodes(ops_386, ops_k6_0f); x86_setopcodes(ops_386, ops_k6_0f);
else else
x86_setopcodes(ops_386, ops_pentiummmx_0f); x86_setopcodes(ops_386, ops_pentiummmx_0f);
#else # else
else else
x86_setopcodes(ops_386, ops_k6_0f); x86_setopcodes(ops_386, ops_k6_0f);
#endif # endif
#endif #endif
timing_rr = 1; /* register dest - register src */ timing_rr = 1; /* register dest - register src */
@@ -1391,14 +1369,12 @@ cpu_set(void)
gdbstub_cpu_init(); gdbstub_cpu_init();
} }
void void
cpu_close(void) cpu_close(void)
{ {
cpu_inited = 0; cpu_inited = 0;
} }
void void
cpu_set_isa_speed(int speed) cpu_set_isa_speed(int speed)
{ {
@@ -1413,7 +1389,6 @@ cpu_set_isa_speed(int speed)
cpu_log("cpu_set_isa_speed(%d) = %d\n", speed, cpu_isa_speed); cpu_log("cpu_set_isa_speed(%d) = %d\n", speed, cpu_isa_speed);
} }
void void
cpu_set_pci_speed(int speed) cpu_set_pci_speed(int speed)
{ {
@@ -1439,7 +1414,6 @@ cpu_set_pci_speed(int speed)
cpu_log("cpu_set_pci_speed(%d) = %d\n", speed, cpu_pci_speed); cpu_log("cpu_set_pci_speed(%d) = %d\n", speed, cpu_pci_speed);
} }
void void
cpu_set_isa_pci_div(int div) cpu_set_isa_pci_div(int div)
{ {
@@ -1453,15 +1427,13 @@ cpu_set_isa_pci_div(int div)
cpu_set_isa_speed(0); cpu_set_isa_speed(0);
} }
void void
cpu_set_agp_speed(int speed) cpu_set_agp_speed(int speed)
{ {
if (speed) { if (speed) {
cpu_agp_speed = speed; cpu_agp_speed = speed;
pc_speed_changed(); pc_speed_changed();
} } else if (cpu_busspeed < 84000000)
else if (cpu_busspeed < 84000000)
cpu_agp_speed = cpu_busspeed; cpu_agp_speed = cpu_busspeed;
else if (cpu_busspeed < 120000000) else if (cpu_busspeed < 120000000)
cpu_agp_speed = cpu_busspeed / 1.5; cpu_agp_speed = cpu_busspeed / 1.5;
@@ -1474,7 +1446,6 @@ cpu_set_agp_speed(int speed)
cpu_log("cpu_set_agp_speed(%d) = %d\n", speed, cpu_agp_speed); cpu_log("cpu_set_agp_speed(%d) = %d\n", speed, cpu_agp_speed);
} }
char * char *
cpu_current_pc(char *bufp) cpu_current_pc(char *bufp)
{ {
@@ -1485,10 +1456,9 @@ cpu_current_pc(char *bufp)
sprintf(bufp, "%04X:%04X", CS, cpu_state.pc); sprintf(bufp, "%04X:%04X", CS, cpu_state.pc);
return(bufp); return (bufp);
} }
void void
cpu_CPUID(void) cpu_CPUID(void)
{ {
@@ -2056,7 +2026,6 @@ cpu_CPUID(void)
} }
} }
void void
cpu_ven_reset(void) cpu_ven_reset(void)
{ {
@@ -2087,7 +2056,6 @@ cpu_ven_reset(void)
} }
} }
void void
cpu_RDMSR(void) cpu_RDMSR(void)
{ {
@@ -2145,7 +2113,8 @@ cpu_RDMSR(void)
case CPU_CYRIX3S: case CPU_CYRIX3S:
EAX = EDX = 0; EAX = EDX = 0;
switch (ECX) { switch (ECX) {
case 0x00: case 0x01: case 0x00:
case 0x01:
break; break;
case 0x10: case 0x10:
EAX = tsc & 0xffffffff; EAX = tsc & 0xffffffff;
@@ -2184,10 +2153,22 @@ cpu_RDMSR(void)
EAX = msr.fcr2 & 0xffffffff; EAX = msr.fcr2 & 0xffffffff;
EDX = msr.fcr2 >> 32; EDX = msr.fcr2 >> 32;
break; break;
case 0x200: case 0x201: case 0x202: case 0x203: case 0x200:
case 0x204: case 0x205: case 0x206: case 0x207: case 0x201:
case 0x208: case 0x209: case 0x20a: case 0x20b: case 0x202:
case 0x20c: case 0x20d: case 0x20e: case 0x20f: case 0x203:
case 0x204:
case 0x205:
case 0x206:
case 0x207:
case 0x208:
case 0x209:
case 0x20a:
case 0x20b:
case 0x20c:
case 0x20d:
case 0x20e:
case 0x20f:
if (ECX & 1) { if (ECX & 1) {
EAX = msr.mtrr_physmask[(ECX - 0x200) >> 1] & 0xffffffff; EAX = msr.mtrr_physmask[(ECX - 0x200) >> 1] & 0xffffffff;
EDX = msr.mtrr_physmask[(ECX - 0x200) >> 1] >> 32; EDX = msr.mtrr_physmask[(ECX - 0x200) >> 1] >> 32;
@@ -2208,8 +2189,14 @@ cpu_RDMSR(void)
EAX = msr.mtrr_fix16k_a000 & 0xffffffff; EAX = msr.mtrr_fix16k_a000 & 0xffffffff;
EDX = msr.mtrr_fix16k_a000 >> 32; EDX = msr.mtrr_fix16k_a000 >> 32;
break; break;
case 0x268: case 0x269: case 0x26a: case 0x26b: case 0x268:
case 0x26c: case 0x26d: case 0x26e: case 0x26f: case 0x269:
case 0x26a:
case 0x26b:
case 0x26c:
case 0x26d:
case 0x26e:
case 0x26f:
EAX = msr.mtrr_fix4k[ECX - 0x268] & 0xffffffff; EAX = msr.mtrr_fix4k[ECX - 0x268] & 0xffffffff;
EDX = msr.mtrr_fix4k[ECX - 0x268] >> 32; EDX = msr.mtrr_fix4k[ECX - 0x268] >> 32;
break; break;
@@ -2315,7 +2302,8 @@ amd_k_invalid_rdmsr:
#endif #endif
EAX = EDX = 0; EAX = EDX = 0;
switch (ECX) { switch (ECX) {
case 0x00: case 0x01: case 0x00:
case 0x01:
break; break;
case 0x10: case 0x10:
EAX = tsc & 0xffffffff; EAX = tsc & 0xffffffff;
@@ -2330,7 +2318,8 @@ amd_k_invalid_rdmsr:
case CPU_PENTIUM2D: case CPU_PENTIUM2D:
EAX = EDX = 0; EAX = EDX = 0;
switch (ECX) { switch (ECX) {
case 0x00: case 0x01: case 0x00:
case 0x01:
break; break;
case 0x10: case 0x10:
EAX = tsc & 0xffffffff; EAX = tsc & 0xffffffff;
@@ -2388,12 +2377,21 @@ amd_k_invalid_rdmsr:
EAX = msr.ecx79 & 0xffffffff; EAX = msr.ecx79 & 0xffffffff;
EDX = msr.ecx79 >> 32; EDX = msr.ecx79 >> 32;
break; break;
case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x88:
case 0x89:
case 0x8a:
case 0x8b:
EAX = msr.ecx8x[ECX - 0x88] & 0xffffffff; EAX = msr.ecx8x[ECX - 0x88] & 0xffffffff;
EDX = msr.ecx8x[ECX - 0x88] >> 32; EDX = msr.ecx8x[ECX - 0x88] >> 32;
break; break;
case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc1:
case 0xc5: case 0xc6: case 0xc7: case 0xc8: case 0xc2:
case 0xc3:
case 0xc4:
case 0xc5:
case 0xc6:
case 0xc7:
case 0xc8:
EAX = msr.ia32_pmc[ECX - 0xC1] & 0xffffffff; EAX = msr.ia32_pmc[ECX - 0xC1] & 0xffffffff;
EDX = msr.ia32_pmc[ECX - 0xC1] >> 32; EDX = msr.ia32_pmc[ECX - 0xC1] >> 32;
break; break;
@@ -2405,7 +2403,10 @@ amd_k_invalid_rdmsr:
EAX = msr.ecx116 & 0xffffffff; EAX = msr.ecx116 & 0xffffffff;
EDX = msr.ecx116 >> 32; EDX = msr.ecx116 >> 32;
break; break;
case 0x118: case 0x119: case 0x11a: case 0x11b: case 0x118:
case 0x119:
case 0x11a:
case 0x11b:
EAX = msr.ecx11x[ECX - 0x118] & 0xffffffff; EAX = msr.ecx11x[ECX - 0x118] & 0xffffffff;
EDX = msr.ecx11x[ECX - 0x118] >> 32; EDX = msr.ecx11x[ECX - 0x118] >> 32;
break; break;
@@ -2457,10 +2458,22 @@ amd_k_invalid_rdmsr:
EAX = msr.ecx1e0 & 0xffffffff; EAX = msr.ecx1e0 & 0xffffffff;
EDX = msr.ecx1e0 >> 32; EDX = msr.ecx1e0 >> 32;
break; break;
case 0x200: case 0x201: case 0x202: case 0x203: case 0x200:
case 0x204: case 0x205: case 0x206: case 0x207: case 0x201:
case 0x208: case 0x209: case 0x20a: case 0x20b: case 0x202:
case 0x20c: case 0x20d: case 0x20e: case 0x20f: case 0x203:
case 0x204:
case 0x205:
case 0x206:
case 0x207:
case 0x208:
case 0x209:
case 0x20a:
case 0x20b:
case 0x20c:
case 0x20d:
case 0x20e:
case 0x20f:
if (ECX & 1) { if (ECX & 1) {
EAX = msr.mtrr_physmask[(ECX - 0x200) >> 1] & 0xffffffff; EAX = msr.mtrr_physmask[(ECX - 0x200) >> 1] & 0xffffffff;
EDX = msr.mtrr_physmask[(ECX - 0x200) >> 1] >> 32; EDX = msr.mtrr_physmask[(ECX - 0x200) >> 1] >> 32;
@@ -2481,8 +2494,14 @@ amd_k_invalid_rdmsr:
EAX = msr.mtrr_fix16k_a000 & 0xffffffff; EAX = msr.mtrr_fix16k_a000 & 0xffffffff;
EDX = msr.mtrr_fix16k_a000 >> 32; EDX = msr.mtrr_fix16k_a000 >> 32;
break; break;
case 0x268: case 0x269: case 0x26a: case 0x26b: case 0x268:
case 0x26c: case 0x26d: case 0x26e: case 0x26f: case 0x269:
case 0x26a:
case 0x26b:
case 0x26c:
case 0x26d:
case 0x26e:
case 0x26f:
EAX = msr.mtrr_fix4k[ECX - 0x268] & 0xffffffff; EAX = msr.mtrr_fix4k[ECX - 0x268] & 0xffffffff;
EDX = msr.mtrr_fix4k[ECX - 0x268] >> 32; EDX = msr.mtrr_fix4k[ECX - 0x268] >> 32;
break; break;
@@ -2494,14 +2513,24 @@ amd_k_invalid_rdmsr:
EAX = msr.mtrr_deftype & 0xffffffff; EAX = msr.mtrr_deftype & 0xffffffff;
EDX = msr.mtrr_deftype >> 32; EDX = msr.mtrr_deftype >> 32;
break; break;
case 0x400: case 0x404: case 0x408: case 0x40c: case 0x400:
case 0x404:
case 0x408:
case 0x40c:
case 0x410: case 0x410:
EAX = msr.mca_ctl[(ECX - 0x400) >> 2] & 0xffffffff; EAX = msr.mca_ctl[(ECX - 0x400) >> 2] & 0xffffffff;
EDX = msr.mca_ctl[(ECX - 0x400) >> 2] >> 32; EDX = msr.mca_ctl[(ECX - 0x400) >> 2] >> 32;
break; break;
case 0x401: case 0x402: case 0x405: case 0x406: case 0x401:
case 0x407: case 0x409: case 0x40d: case 0x40e: case 0x402:
case 0x411: case 0x412: case 0x405:
case 0x406:
case 0x407:
case 0x409:
case 0x40d:
case 0x40e:
case 0x411:
case 0x412:
break; break;
case 0x570: case 0x570:
EAX = msr.ecx570 & 0xffffffff; EAX = msr.ecx570 & 0xffffffff;
@@ -2535,7 +2564,6 @@ i686_invalid_rdmsr:
cpu_log("RDMSR %08X %08X%08X\n", ECX, EDX, EAX); cpu_log("RDMSR %08X %08X%08X\n", ECX, EDX, EAX);
} }
void void
cpu_WRMSR(void) cpu_WRMSR(void)
{ {
@@ -2572,7 +2600,7 @@ cpu_WRMSR(void)
msr.tr12 = EAX & 0x228; msr.tr12 = EAX & 0x228;
break; break;
case 0x10: case 0x10:
tsc = EAX | ((uint64_t)EDX << 32); tsc = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x11: case 0x11:
msr.cesr = EAX & 0xff00ff; msr.cesr = EAX & 0xff00ff;
@@ -2597,20 +2625,21 @@ cpu_WRMSR(void)
CPUID = cpu_s->cpuid_model; CPUID = cpu_s->cpuid_model;
break; break;
case 0x108: case 0x108:
msr.fcr2 = EAX | ((uint64_t)EDX << 32); msr.fcr2 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x109: case 0x109:
msr.fcr3 = EAX | ((uint64_t)EDX << 32); msr.fcr3 = EAX | ((uint64_t) EDX << 32);
break; break;
} }
break; break;
case CPU_CYRIX3S: case CPU_CYRIX3S:
switch (ECX) { switch (ECX) {
case 0x00: case 0x01: case 0x00:
case 0x01:
break; break;
case 0x10: case 0x10:
tsc = EAX | ((uint64_t)EDX << 32); tsc = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x1107: case 0x1107:
msr.fcr = EAX; msr.fcr = EAX;
@@ -2620,34 +2649,53 @@ cpu_WRMSR(void)
cpu_features &= ~CPU_FEATURE_CX8; cpu_features &= ~CPU_FEATURE_CX8;
break; break;
case 0x1108: case 0x1108:
msr.fcr2 = EAX | ((uint64_t)EDX << 32); msr.fcr2 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x1109: case 0x1109:
msr.fcr3 = EAX | ((uint64_t)EDX << 32); msr.fcr3 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x200: case 0x201: case 0x202: case 0x203: case 0x200:
case 0x204: case 0x205: case 0x206: case 0x207: case 0x201:
case 0x208: case 0x209: case 0x20a: case 0x20b: case 0x202:
case 0x20c: case 0x20d: case 0x20e: case 0x20f: case 0x203:
case 0x204:
case 0x205:
case 0x206:
case 0x207:
case 0x208:
case 0x209:
case 0x20a:
case 0x20b:
case 0x20c:
case 0x20d:
case 0x20e:
case 0x20f:
if (ECX & 1) if (ECX & 1)
msr.mtrr_physmask[(ECX - 0x200) >> 1] = EAX | ((uint64_t)EDX << 32); msr.mtrr_physmask[(ECX - 0x200) >> 1] = EAX | ((uint64_t) EDX << 32);
else else
msr.mtrr_physbase[(ECX - 0x200) >> 1] = EAX | ((uint64_t)EDX << 32); msr.mtrr_physbase[(ECX - 0x200) >> 1] = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x250: case 0x250:
msr.mtrr_fix64k_8000 = EAX | ((uint64_t)EDX << 32); msr.mtrr_fix64k_8000 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x258: case 0x258:
msr.mtrr_fix16k_8000 = EAX | ((uint64_t)EDX << 32); msr.mtrr_fix16k_8000 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x259: case 0x259:
msr.mtrr_fix16k_a000 = EAX | ((uint64_t)EDX << 32); msr.mtrr_fix16k_a000 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x268: case 0x269: case 0x26A: case 0x26B: case 0x26C: case 0x26D: case 0x26E: case 0x26F: case 0x268:
msr.mtrr_fix4k[ECX - 0x268] = EAX | ((uint64_t)EDX << 32); case 0x269:
case 0x26A:
case 0x26B:
case 0x26C:
case 0x26D:
case 0x26E:
case 0x26F:
msr.mtrr_fix4k[ECX - 0x268] = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x2ff: case 0x2ff:
msr.mtrr_deftype = EAX | ((uint64_t)EDX << 32); msr.mtrr_deftype = EAX | ((uint64_t) EDX << 32);
break; break;
} }
break; break;
@@ -2663,19 +2711,20 @@ cpu_WRMSR(void)
case CPU_K6_2P: case CPU_K6_2P:
case CPU_K6_3P: case CPU_K6_3P:
switch (ECX) { switch (ECX) {
case 0x00: case 0x01: case 0x00:
case 0x01:
break; break;
case 0x0e: case 0x0e:
msr.tr12 = EAX & 0x228; msr.tr12 = EAX & 0x228;
break; break;
case 0x10: case 0x10:
tsc = EAX | ((uint64_t)EDX << 32); tsc = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x83: case 0x83:
msr.ecx83 = EAX | ((uint64_t)EDX << 32); msr.ecx83 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0xc0000080: case 0xc0000080:
temp = EAX | ((uint64_t)EDX << 32); temp = EAX | ((uint64_t) EDX << 32);
if (temp & ~1ULL) if (temp & ~1ULL)
x86gpf(NULL, 0); x86gpf(NULL, 0);
else else
@@ -2685,40 +2734,40 @@ cpu_WRMSR(void)
if (cpu_s->cpu_type < CPU_K6_2) if (cpu_s->cpu_type < CPU_K6_2)
goto amd_k_invalid_wrmsr; goto amd_k_invalid_wrmsr;
msr.star = EAX | ((uint64_t)EDX << 32); msr.star = EAX | ((uint64_t) EDX << 32);
break; break;
case 0xc0000082: case 0xc0000082:
msr.amd_whcr = EAX | ((uint64_t)EDX << 32); msr.amd_whcr = EAX | ((uint64_t) EDX << 32);
break; break;
case 0xc0000085: case 0xc0000085:
if (cpu_s->cpu_type < CPU_K6_2C) if (cpu_s->cpu_type < CPU_K6_2C)
goto amd_k_invalid_wrmsr; goto amd_k_invalid_wrmsr;
msr.amd_uwccr = EAX | ((uint64_t)EDX << 32); msr.amd_uwccr = EAX | ((uint64_t) EDX << 32);
break; break;
case 0xc0000086: case 0xc0000086:
if (cpu_s->cpu_type < CPU_K6_2P) if (cpu_s->cpu_type < CPU_K6_2P)
goto amd_k_invalid_wrmsr; goto amd_k_invalid_wrmsr;
msr.amd_epmr = EAX | ((uint64_t)EDX << 32); msr.amd_epmr = EAX | ((uint64_t) EDX << 32);
break; break;
case 0xc0000087: case 0xc0000087:
if (cpu_s->cpu_type < CPU_K6_2C) if (cpu_s->cpu_type < CPU_K6_2C)
goto amd_k_invalid_wrmsr; goto amd_k_invalid_wrmsr;
msr.amd_psor = EAX | ((uint64_t)EDX << 32); msr.amd_psor = EAX | ((uint64_t) EDX << 32);
break; break;
case 0xc0000088: case 0xc0000088:
if (cpu_s->cpu_type < CPU_K6_2C) if (cpu_s->cpu_type < CPU_K6_2C)
goto amd_k_invalid_wrmsr; goto amd_k_invalid_wrmsr;
msr.amd_pfir = EAX | ((uint64_t)EDX << 32); msr.amd_pfir = EAX | ((uint64_t) EDX << 32);
break; break;
case 0xc0000089: case 0xc0000089:
if (cpu_s->cpu_type < CPU_K6_3) if (cpu_s->cpu_type < CPU_K6_3)
goto amd_k_invalid_wrmsr; goto amd_k_invalid_wrmsr;
msr.amd_l2aar = EAX | ((uint64_t)EDX << 32); msr.amd_l2aar = EAX | ((uint64_t) EDX << 32);
break; break;
default: default:
amd_k_invalid_wrmsr: amd_k_invalid_wrmsr:
@@ -2738,10 +2787,11 @@ amd_k_invalid_wrmsr:
#endif #endif
cpu_log("WRMSR: ECX = %08X, val = %08X%08X\n", ECX, EDX, EAX); cpu_log("WRMSR: ECX = %08X, val = %08X%08X\n", ECX, EDX, EAX);
switch (ECX) { switch (ECX) {
case 0x00: case 0x01: case 0x00:
case 0x01:
break; break;
case 0x10: case 0x10:
tsc = EAX | ((uint64_t)EDX << 32); tsc = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x8b: case 0x8b:
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86) #if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
@@ -2760,12 +2810,13 @@ amd_k_invalid_wrmsr:
case CPU_PENTIUM2: case CPU_PENTIUM2:
case CPU_PENTIUM2D: case CPU_PENTIUM2D:
switch (ECX) { switch (ECX) {
case 0x00: case 0x01: case 0x00:
case 0x01:
if (EAX || EDX) if (EAX || EDX)
x86gpf(NULL, 0); x86gpf(NULL, 0);
break; break;
case 0x10: case 0x10:
tsc = EAX | ((uint64_t)EDX << 32); tsc = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x1b: case 0x1b:
cpu_log("APIC_BASE write: %08X%08X\n", EDX, EAX); cpu_log("APIC_BASE write: %08X%08X\n", EDX, EAX);
@@ -2774,26 +2825,38 @@ amd_k_invalid_wrmsr:
case 0x2a: case 0x2a:
break; break;
case 0x79: case 0x79:
msr.ecx79 = EAX | ((uint64_t)EDX << 32); msr.ecx79 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x88:
msr.ecx8x[ECX - 0x88] = EAX | ((uint64_t)EDX << 32); case 0x89:
case 0x8a:
case 0x8b:
msr.ecx8x[ECX - 0x88] = EAX | ((uint64_t) EDX << 32);
break; break;
case 0xc1: case 0xc2: case 0xc3: case 0xc4: case 0xc1:
case 0xc5: case 0xc6: case 0xc7: case 0xc8: case 0xc2:
msr.ia32_pmc[ECX - 0xC1] = EAX | ((uint64_t)EDX << 32); case 0xc3:
case 0xc4:
case 0xc5:
case 0xc6:
case 0xc7:
case 0xc8:
msr.ia32_pmc[ECX - 0xC1] = EAX | ((uint64_t) EDX << 32);
break; break;
case 0xfe: case 0xfe:
msr.mtrr_cap = EAX | ((uint64_t)EDX << 32); msr.mtrr_cap = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x116: case 0x116:
msr.ecx116 = EAX | ((uint64_t)EDX << 32); msr.ecx116 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x118: case 0x119: case 0x11a: case 0x11b: case 0x118:
msr.ecx11x[ECX - 0x118] = EAX | ((uint64_t)EDX << 32); case 0x119:
case 0x11a:
case 0x11b:
msr.ecx11x[ECX - 0x118] = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x11e: case 0x11e:
msr.ecx11e = EAX | ((uint64_t)EDX << 32); msr.ecx11e = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x174: case 0x174:
if (cpu_s->cpu_type == CPU_PENTIUMPRO) if (cpu_s->cpu_type == CPU_PENTIUMPRO)
@@ -2820,69 +2883,97 @@ amd_k_invalid_wrmsr:
x86gpf(NULL, 0); x86gpf(NULL, 0);
break; break;
case 0x17b: case 0x17b:
msr.mcg_ctl = EAX | ((uint64_t)EDX << 32); msr.mcg_ctl = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x186: case 0x186:
msr.ecx186 = EAX | ((uint64_t)EDX << 32); msr.ecx186 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x187: case 0x187:
msr.ecx187 = EAX | ((uint64_t)EDX << 32); msr.ecx187 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x1e0: case 0x1e0:
msr.ecx1e0 = EAX | ((uint64_t)EDX << 32); msr.ecx1e0 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x200: case 0x201: case 0x202: case 0x203: case 0x200:
case 0x204: case 0x205: case 0x206: case 0x207: case 0x201:
case 0x208: case 0x209: case 0x20a: case 0x20b: case 0x202:
case 0x20c: case 0x20d: case 0x20e: case 0x20f: case 0x203:
case 0x204:
case 0x205:
case 0x206:
case 0x207:
case 0x208:
case 0x209:
case 0x20a:
case 0x20b:
case 0x20c:
case 0x20d:
case 0x20e:
case 0x20f:
if (ECX & 1) if (ECX & 1)
msr.mtrr_physmask[(ECX - 0x200) >> 1] = EAX | ((uint64_t)EDX << 32); msr.mtrr_physmask[(ECX - 0x200) >> 1] = EAX | ((uint64_t) EDX << 32);
else else
msr.mtrr_physbase[(ECX - 0x200) >> 1] = EAX | ((uint64_t)EDX << 32); msr.mtrr_physbase[(ECX - 0x200) >> 1] = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x250: case 0x250:
msr.mtrr_fix64k_8000 = EAX | ((uint64_t)EDX << 32); msr.mtrr_fix64k_8000 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x258: case 0x258:
msr.mtrr_fix16k_8000 = EAX | ((uint64_t)EDX << 32); msr.mtrr_fix16k_8000 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x259: case 0x259:
msr.mtrr_fix16k_a000 = EAX | ((uint64_t)EDX << 32); msr.mtrr_fix16k_a000 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x268: case 0x269: case 0x26a: case 0x26b: case 0x268:
case 0x26c: case 0x26d: case 0x26e: case 0x26f: case 0x269:
msr.mtrr_fix4k[ECX - 0x268] = EAX | ((uint64_t)EDX << 32); case 0x26a:
case 0x26b:
case 0x26c:
case 0x26d:
case 0x26e:
case 0x26f:
msr.mtrr_fix4k[ECX - 0x268] = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x277: case 0x277:
msr.pat = EAX | ((uint64_t)EDX << 32); msr.pat = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x2ff: case 0x2ff:
msr.mtrr_deftype = EAX | ((uint64_t)EDX << 32); msr.mtrr_deftype = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x400: case 0x404: case 0x408: case 0x40c: case 0x400:
case 0x404:
case 0x408:
case 0x40c:
case 0x410: case 0x410:
msr.mca_ctl[(ECX - 0x400) >> 2] = EAX | ((uint64_t)EDX << 32); msr.mca_ctl[(ECX - 0x400) >> 2] = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x401: case 0x402: case 0x405: case 0x406: case 0x401:
case 0x407: case 0x409: case 0x40d: case 0x40e: case 0x402:
case 0x411: case 0x412: case 0x405:
case 0x406:
case 0x407:
case 0x409:
case 0x40d:
case 0x40e:
case 0x411:
case 0x412:
if (EAX || EDX) if (EAX || EDX)
x86gpf(NULL, 0); x86gpf(NULL, 0);
break; break;
case 0x570: case 0x570:
msr.ecx570 = EAX | ((uint64_t)EDX << 32); msr.ecx570 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0x1002ff: case 0x1002ff:
msr.ecx1002ff = EAX | ((uint64_t)EDX << 32); msr.ecx1002ff = EAX | ((uint64_t) EDX << 32);
break; break;
case 0xf0f00250: case 0xf0f00250:
msr.ecxf0f00250 = EAX | ((uint64_t)EDX << 32); msr.ecxf0f00250 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0xf0f00258: case 0xf0f00258:
msr.ecxf0f00258 = EAX | ((uint64_t)EDX << 32); msr.ecxf0f00258 = EAX | ((uint64_t) EDX << 32);
break; break;
case 0xf0f00259: case 0xf0f00259:
msr.ecxf0f00259 = EAX | ((uint64_t)EDX << 32); msr.ecxf0f00259 = EAX | ((uint64_t) EDX << 32);
break; break;
default: default:
i686_invalid_wrmsr: i686_invalid_wrmsr:
@@ -2894,7 +2985,6 @@ i686_invalid_wrmsr:
} }
} }
static void static void
cpu_write(uint16_t addr, uint8_t val, void *priv) cpu_write(uint16_t addr, uint8_t val, void *priv)
{ {
@@ -2910,7 +3000,8 @@ cpu_write(uint16_t addr, uint8_t val, void *priv)
if (!(addr & 1)) if (!(addr & 1))
cyrix_addr = val; cyrix_addr = val;
else switch (cyrix_addr) { else
switch (cyrix_addr) {
case 0xc0: /* CCR0 */ case 0xc0: /* CCR0 */
ccr0 = val; ccr0 = val;
break; break;
@@ -2976,7 +3067,6 @@ cpu_write(uint16_t addr, uint8_t val, void *priv)
} }
} }
static uint8_t static uint8_t
cpu_read(uint16_t addr, void *priv) cpu_read(uint16_t addr, void *priv)
{ {
@@ -3018,7 +3108,6 @@ cpu_read(uint16_t addr, void *priv)
return 0xff; return 0xff;
} }
void void
#ifdef USE_DYNAREC #ifdef USE_DYNAREC
x86_setopcodes(const OpFn *opcodes, const OpFn *opcodes_0f, x86_setopcodes(const OpFn *opcodes, const OpFn *opcodes_0f,
@@ -3037,7 +3126,6 @@ x86_setopcodes(const OpFn *opcodes, const OpFn *opcodes_0f)
} }
#endif #endif
void void
cpu_update_waitstates(void) cpu_update_waitstates(void)
{ {
@@ -3053,11 +3141,11 @@ cpu_update_waitstates(void)
cpu_prefetch_cycles = 0; cpu_prefetch_cycles = 0;
} else if (cpu_waitstates && (cpu_s->cpu_type >= CPU_286 && cpu_s->cpu_type <= CPU_386DX)) { } else if (cpu_waitstates && (cpu_s->cpu_type >= CPU_286 && cpu_s->cpu_type <= CPU_386DX)) {
/* Waitstates override */ /* Waitstates override */
cpu_prefetch_cycles = cpu_waitstates+1; cpu_prefetch_cycles = cpu_waitstates + 1;
cpu_cycles_read = cpu_waitstates+1; cpu_cycles_read = cpu_waitstates + 1;
cpu_cycles_read_l = (cpu_16bitbus ? 2 : 1) * (cpu_waitstates+1); cpu_cycles_read_l = (cpu_16bitbus ? 2 : 1) * (cpu_waitstates + 1);
cpu_cycles_write = cpu_waitstates+1; cpu_cycles_write = cpu_waitstates + 1;
cpu_cycles_write_l = (cpu_16bitbus ? 2 : 1) * (cpu_waitstates+1); cpu_cycles_write_l = (cpu_16bitbus ? 2 : 1) * (cpu_waitstates + 1);
} else if (cpu_cache_ext_enabled) { } else if (cpu_cache_ext_enabled) {
/* Use cache timings */ /* Use cache timings */
cpu_prefetch_cycles = cpu_s->cache_read_cycles; cpu_prefetch_cycles = cpu_s->cache_read_cycles;

52
src/cpu/cpu.h
View File

@@ -19,7 +19,7 @@
* Copyright 2016,2018 Miran Grca. * Copyright 2016,2018 Miran Grca.
*/ */
#ifndef EMU_CPU_H #ifndef EMU_CPU_H
# define EMU_CPU_H #define EMU_CPU_H
enum { enum {
FPU_NONE, FPU_NONE,
@@ -108,7 +108,6 @@ enum {
CPU_PKG_EBGA368 = (1 << 22) CPU_PKG_EBGA368 = (1 << 22)
}; };
#define MANU_INTEL 0 #define MANU_INTEL 0
#define MANU_AMD 1 #define MANU_AMD 1
#define MANU_CYRIX 2 #define MANU_CYRIX 2
@@ -121,12 +120,11 @@ enum {
#define CPU_FIXED_MULTIPLIER 8 #define CPU_FIXED_MULTIPLIER 8
#if (defined __amd64__ || defined _M_X64) #if (defined __amd64__ || defined _M_X64)
#define LOOKUP_INV -1LL # define LOOKUP_INV -1LL
#else #else
#define LOOKUP_INV -1 # define LOOKUP_INV -1
#endif #endif
typedef struct { typedef struct {
const char *name; const char *name;
const char *internal_name; const char *internal_name;
@@ -168,8 +166,6 @@ typedef struct {
const cpu_legacy_table_t **tables; const cpu_legacy_table_t **tables;
} cpu_legacy_machine_t; } cpu_legacy_machine_t;
#define C_FLAG 0x0001 #define C_FLAG 0x0001
#define P_FLAG 0x0004 #define P_FLAG 0x0004
#define A_FLAG 0x0010 #define A_FLAG 0x0010
@@ -193,12 +189,11 @@ typedef struct {
#define CR4_PSE (1 << 4) #define CR4_PSE (1 << 4)
#define CR4_PAE (1 << 5) #define CR4_PAE (1 << 5)
#define CPL ((cpu_state.seg_cs.access>>5)&3) #define CPL ((cpu_state.seg_cs.access >> 5) & 3)
#define IOPL ((cpu_state.flags>>12)&3) #define IOPL ((cpu_state.flags >> 12) & 3)
#define IOPLp ((!(msw&1)) || (CPL<=IOPL))
#define IOPLp ((!(msw & 1)) || (CPL <= IOPL))
typedef union { typedef union {
uint32_t l; uint32_t l;
@@ -370,12 +365,12 @@ typedef struct {
#ifdef USE_NEW_DYNAREC #ifdef USE_NEW_DYNAREC
uint32_t old_fp_control, new_fp_control; uint32_t old_fp_control, new_fp_control;
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 # if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
uint16_t old_fp_control2, new_fp_control2; uint16_t old_fp_control2, new_fp_control2;
#endif # endif
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined __amd64__ || defined _M_X64 # if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined __amd64__ || defined _M_X64
uint32_t trunc_fp_control; uint32_t trunc_fp_control;
#endif # endif
#else #else
uint16_t old_npxc, new_npxc; uint16_t old_npxc, new_npxc;
#endif #endif
@@ -393,13 +388,11 @@ typedef struct {
uint32_t _smbase; uint32_t _smbase;
} cpu_state_t; } cpu_state_t;
#define in_smm cpu_state._in_smm #define in_smm cpu_state._in_smm
#define smi_line cpu_state._smi_line #define smi_line cpu_state._smi_line
#define smbase cpu_state._smbase #define smbase cpu_state._smbase
/*The cpu_state.flags below must match in both cpu_cur_status and block->status for a block /*The cpu_state.flags below must match in both cpu_cur_status and block->status for a block
to be valid*/ to be valid*/
#define CPU_STATUS_USE32 (1 << 0) #define CPU_STATUS_USE32 (1 << 0)
@@ -412,13 +405,13 @@ typedef struct {
/*If the cpu_state.flags below are set in cpu_cur_status, they must be set in block->status. /*If the cpu_state.flags below are set in cpu_cur_status, they must be set in block->status.
Otherwise they are ignored*/ Otherwise they are ignored*/
#ifdef USE_NEW_DYNAREC #ifdef USE_NEW_DYNAREC
#define CPU_STATUS_NOTFLATDS (1 << 8) # define CPU_STATUS_NOTFLATDS (1 << 8)
#define CPU_STATUS_NOTFLATSS (1 << 9) # define CPU_STATUS_NOTFLATSS (1 << 9)
#define CPU_STATUS_MASK 0xff00 # define CPU_STATUS_MASK 0xff00
#else #else
#define CPU_STATUS_NOTFLATDS (1 << 16) # define CPU_STATUS_NOTFLATDS (1 << 16)
#define CPU_STATUS_NOTFLATSS (1 << 17) # define CPU_STATUS_NOTFLATSS (1 << 17)
#define CPU_STATUS_MASK 0xffff0000 # define CPU_STATUS_MASK 0xffff0000
#endif #endif
#ifdef _MSC_VER #ifdef _MSC_VER
@@ -433,7 +426,7 @@ typedef struct {
COMPILE_TIME_ASSERT(sizeof(cpu_state_t) <= 128) COMPILE_TIME_ASSERT(sizeof(cpu_state_t) <= 128)
#define cpu_state_offset(MEMBER) ((uint8_t)((uintptr_t)&cpu_state.MEMBER - (uintptr_t)&cpu_state - 128)) #define cpu_state_offset(MEMBER) ((uint8_t) ((uintptr_t) &cpu_state.MEMBER - (uintptr_t) &cpu_state - 128))
#define EAX cpu_state.regs[0].l #define EAX cpu_state.regs[0].l
#define AX cpu_state.regs[0].w #define AX cpu_state.regs[0].w
@@ -462,7 +455,7 @@ COMPILE_TIME_ASSERT(sizeof(cpu_state_t) <= 128)
#define cycles cpu_state._cycles #define cycles cpu_state._cycles
#ifdef FPU_CYCLES #ifdef FPU_CYCLES
#define fpu_cycles cpu_state._fpu_cycles # define fpu_cycles cpu_state._fpu_cycles
#endif #endif
#define cpu_rm cpu_state.rm_data.rm_mod_reg.rm #define cpu_rm cpu_state.rm_data.rm_mod_reg.rm
@@ -475,7 +468,6 @@ COMPILE_TIME_ASSERT(sizeof(cpu_state_t) <= 128)
#define CR4_PCE (1 << 8) #define CR4_PCE (1 << 8)
#define CR4_OSFXSR (1 << 9) #define CR4_OSFXSR (1 << 9)
/* Global variables. */ /* Global variables. */
extern cpu_state_t cpu_state; extern cpu_state_t cpu_state;
@@ -528,7 +520,7 @@ extern int cpl_override;
extern int CPUID; extern int CPUID;
extern uint64_t xt_cpu_multi; extern uint64_t xt_cpu_multi;
extern int isa_cycles, cpu_inited; extern int isa_cycles, cpu_inited;
extern uint32_t oldds,oldss,olddslimit,oldsslimit,olddslimitw,oldsslimitw; extern uint32_t oldds, oldss, olddslimit, oldsslimit, olddslimitw, oldsslimitw;
extern uint32_t pccache; extern uint32_t pccache;
extern uint8_t *pccache2; extern uint8_t *pccache2;
@@ -552,12 +544,11 @@ extern uint32_t _tr[8];
extern uint32_t cache_index; extern uint32_t cache_index;
extern uint8_t _cache[2048]; extern uint8_t _cache[2048];
/*Segments - /*Segments -
_cs,_ds,_es,_ss are the segment structures _cs,_ds,_es,_ss are the segment structures
CS,DS,ES,SS is the 16-bit data CS,DS,ES,SS is the 16-bit data
cs,ds,es,ss are defines to the bases*/ cs,ds,es,ss are defines to the bases*/
extern x86seg gdt,ldt,idt,tr; extern x86seg gdt, ldt, idt, tr;
extern x86seg _oldds; extern x86seg _oldds;
#define CS cpu_state.seg_cs.seg #define CS cpu_state.seg_cs.seg
#define DS cpu_state.seg_ds.seg #define DS cpu_state.seg_ds.seg
@@ -572,7 +563,6 @@ extern x86seg _oldds;
#define fs_seg cpu_state.seg_fs.base #define fs_seg cpu_state.seg_fs.base
#define gs cpu_state.seg_gs.base #define gs cpu_state.seg_gs.base
#define ISA_CYCLES(x) (x * isa_cycles) #define ISA_CYCLES(x) (x * isa_cycles)
extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l; extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
@@ -608,7 +598,6 @@ extern int cpu_end_block_after_ins;
extern uint16_t cpu_fast_off_count, cpu_fast_off_val; extern uint16_t cpu_fast_off_count, cpu_fast_off_val;
extern uint32_t cpu_fast_off_flags; extern uint32_t cpu_fast_off_flags;
/* Functions. */ /* Functions. */
extern int cpu_has_feature(int feature); extern int cpu_has_feature(int feature);
@@ -716,7 +705,6 @@ typedef struct
uint32_t smhr; uint32_t smhr;
} cyrix_t; } cyrix_t;
extern uint32_t addr64, addr64_2; extern uint32_t addr64, addr64_2;
extern uint32_t addr64a[8], addr64a_2[8]; extern uint32_t addr64a[8], addr64a_2[8];

18
src/cpu/x87_timings.c
View File

@@ -10,8 +10,7 @@
x87_timings_t x87_timings; x87_timings_t x87_timings;
x87_timings_t x87_concurrency; x87_timings_t x87_concurrency;
const x87_timings_t x87_timings_8087 = const x87_timings_t x87_timings_8087 = {
{
.f2xm1 = (310 + 630) / 2, .f2xm1 = (310 + 630) / 2,
.fabs = (10 + 17) / 2, .fabs = (10 + 17) / 2,
.fadd = (70 + 100) / 2, .fadd = (70 + 100) / 2,
@@ -87,8 +86,7 @@ const x87_timings_t x87_timings_8087 =
}; };
/*Mostly the same as 8087*/ /*Mostly the same as 8087*/
const x87_timings_t x87_timings_287 = const x87_timings_t x87_timings_287 = {
{
.f2xm1 = (310 + 630) / 2, .f2xm1 = (310 + 630) / 2,
.fabs = (10 + 17) / 2, .fabs = (10 + 17) / 2,
.fadd = (70 + 100) / 2, .fadd = (70 + 100) / 2,
@@ -163,8 +161,7 @@ const x87_timings_t x87_timings_287 =
.fyl2xp1 = (700 + 1000) / 2 .fyl2xp1 = (700 + 1000) / 2
}; };
const x87_timings_t x87_timings_387 = const x87_timings_t x87_timings_387 = {
{
.f2xm1 = (211 + 476) / 2, .f2xm1 = (211 + 476) / 2,
.fabs = 22, .fabs = 22,
.fadd = (23 + 34) / 2, .fadd = (23 + 34) / 2,
@@ -239,8 +236,7 @@ const x87_timings_t x87_timings_387 =
.fyl2xp1 = (257 + 547) / 2 .fyl2xp1 = (257 + 547) / 2
}; };
const x87_timings_t x87_timings_486 = const x87_timings_t x87_timings_486 = {
{
.f2xm1 = (140 + 270) / 2, .f2xm1 = (140 + 270) / 2,
.fabs = 3, .fabs = 3,
.fadd = (8 + 20) / 2, .fadd = (8 + 20) / 2,
@@ -317,8 +313,7 @@ const x87_timings_t x87_timings_486 =
/* this should be used for FPUs with no concurrency. /* this should be used for FPUs with no concurrency.
some pre-486DX Cyrix FPUs reportedly are like this. */ some pre-486DX Cyrix FPUs reportedly are like this. */
const x87_timings_t x87_concurrency_none = const x87_timings_t x87_concurrency_none = {
{
.f2xm1 = 0, .f2xm1 = 0,
.fabs = 0, .fabs = 0,
.fadd = 0, .fadd = 0,
@@ -393,8 +388,7 @@ const x87_timings_t x87_concurrency_none =
.fyl2xp1 = 0, .fyl2xp1 = 0,
}; };
const x87_timings_t x87_concurrency_486 = const x87_timings_t x87_concurrency_486 = {
{
.f2xm1 = 2, .f2xm1 = 2,
.fabs = 0, .fabs = 0,
.fadd = 7, .fadd = 7,