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Some clang-formatting in src/cpu

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This commit is contained in:
Jasmine Iwanek
2022-09-20 01:00:45 -04:00
parent b2fb6dbeec
commit b4673117fd
6 changed files with 5424 additions and 5271 deletions
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26
src/cpu/386.c
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@@ -28,11 +28,9 @@
# include "codegen.h"
#endif
#undef CPU_BLOCK_END
#define CPU_BLOCK_END()
extern int codegen_flags_changed;
int tempc, oldcpl, optype, inttype, oddeven = 0;
@@ -48,11 +46,9 @@ uint32_t backupregs[16];
x86seg _oldds;
#ifdef ENABLE_386_LOG
int x386_do_log = ENABLE_386_LOG;
void
x386_log(const char *fmt, ...)
{
@@ -68,17 +64,23 @@ x386_log(const char *fmt, ...)
# define x386_log(fmt, ...)
#endif
#undef CPU_BLOCK_END
#define CPU_BLOCK_END()
#include "x86_flags.h"
#define getbytef() ((uint8_t)(fetchdat)); cpu_state.pc++
#define getwordf() ((uint16_t)(fetchdat)); cpu_state.pc+=2
#define getbyte2f() ((uint8_t)(fetchdat>>8)); cpu_state.pc++
#define getword2f() ((uint16_t)(fetchdat>>8)); cpu_state.pc+=2
#define getbytef() \
((uint8_t) (fetchdat)); \
cpu_state.pc++
#define getwordf() \
((uint16_t) (fetchdat)); \
cpu_state.pc += 2
#define getbyte2f() \
((uint8_t) (fetchdat >> 8)); \
cpu_state.pc++
#define getword2f() \
((uint16_t) (fetchdat >> 8)); \
cpu_state.pc += 2
#define OP_TABLE(name) ops_##name
@@ -107,7 +109,6 @@ x386_log(const char *fmt, ...)
#include "x86_ops.h"
void
exec386(int cycs)
{
@@ -162,7 +163,8 @@ exec386(int cycs)
#endif
#ifndef USE_NEW_DYNAREC
if (!use32) cpu_state.pc &= 0xffff;
if (!use32)
cpu_state.pc &= 0xffff;
#endif
if (cpu_end_block_after_ins)

465
src/cpu/808x.c
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File diff suppressed because it is too large Load Diff

274
src/cpu/cpu.c
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@@ -49,7 +49,6 @@
#define CCR3_SMI_LOCK (1 << 0)
#define CCR3_NMI_EN (1 << 1)
enum {
CPUID_FPU = (1 << 0),
CPUID_VME = (1 << 1),
@@ -71,7 +70,6 @@ enum {
/*Addition flags returned by CPUID function 0x80000001*/
#define CPUID_3DNOW (1UL << 31UL)
/* Make sure this is as low as possible. */
cpu_state_t cpu_state;
@@ -147,20 +145,16 @@ uint8_t do_translate = 0, do_translate2 = 0;
void (*cpu_exec)(int cycs);
static uint8_t ccr0, ccr1, ccr2, ccr3, ccr4, ccr5, ccr6;
static int cyrix_addr;
static void cpu_write(uint16_t addr, uint8_t val, void *priv);
static uint8_t cpu_read(uint16_t addr, void *priv);
#ifdef ENABLE_CPU_LOG
int cpu_do_log = ENABLE_CPU_LOG;
void
cpu_log(const char *fmt, ...)
{
@@ -176,14 +170,12 @@ cpu_log(const char *fmt, ...)
# define cpu_log(fmt, ...)
#endif
int
cpu_has_feature(int feature)
{
return cpu_features & feature;
}
void
cpu_dynamic_switch(int new_cpu)
{
@@ -199,14 +191,12 @@ cpu_dynamic_switch(int new_cpu)
cpu = c;
}
void
cpu_set_edx(void)
{
EDX = cpu_s->edx_reset;
}
cpu_family_t *
cpu_get_family(const char *internal_name)
{
@@ -221,7 +211,6 @@ cpu_get_family(const char *internal_name)
return NULL;
}
uint8_t
cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
{
@@ -295,11 +284,9 @@ cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
/* K6-2+ / K6-3+ */
else if ((cpu_s->cpu_type == CPU_K6_2P) || (cpu_s->cpu_type == CPU_K6_3P))
multi = 2.5;
else if (((cpu_s->cpu_type == CPU_WINCHIP) || (cpu_s->cpu_type == CPU_WINCHIP2)) &&
(machine_s->cpu.min_multi > 2.0)) /* WinChip (2) */
else if (((cpu_s->cpu_type == CPU_WINCHIP) || (cpu_s->cpu_type == CPU_WINCHIP2)) && (machine_s->cpu.min_multi > 2.0)) /* WinChip (2) */
multi = 2.5;
}
else if (multi == (7.0 / 3.0)) /* WinChip 2A - 2.33x */
} else if (multi == (7.0 / 3.0)) /* WinChip 2A - 2.33x */
multi = 5.0;
else if (multi == (8.0 / 3.0)) /* WinChip 2A - 2.66x */
multi = 5.5;
@@ -320,8 +307,7 @@ cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
multi = 4.5;
} else if ((cpu_s->cpu_type == CPU_Cx6x86) || (cpu_s->cpu_type == CPU_Cx6x86L)) /* 6x86(L) */
multi = 3.0;
} else if ((multi == 5.0) && ((cpu_s->cpu_type == CPU_WINCHIP) || (cpu_s->cpu_type == CPU_WINCHIP2)) &&
(machine_s->cpu.min_multi > 5.0)) /* WinChip (2) */
} else if ((multi == 5.0) && ((cpu_s->cpu_type == CPU_WINCHIP) || (cpu_s->cpu_type == CPU_WINCHIP2)) && (machine_s->cpu.min_multi > 5.0)) /* WinChip (2) */
multi = 5.5;
else if (multi == 6.0) /* K6-2(+) / K6-3(+) */
multi = 2.0;
@@ -338,7 +324,6 @@ cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
return 1;
}
uint8_t
cpu_family_is_eligible(const cpu_family_t *cpu_family, int machine)
{
@@ -353,7 +338,6 @@ cpu_family_is_eligible(const cpu_family_t *cpu_family, int machine)
return 0;
}
void
cpu_set(void)
{
@@ -376,8 +360,7 @@ cpu_set(void)
is286 = (cpu_s->cpu_type >= CPU_286);
is386 = (cpu_s->cpu_type >= CPU_386SX);
israpidcad = (cpu_s->cpu_type == CPU_RAPIDCAD);
isibm486 = (cpu_s->cpu_type == CPU_IBM386SLC) || (cpu_s->cpu_type == CPU_IBM486SLC) ||
(cpu_s->cpu_type == CPU_IBM486BL);
isibm486 = (cpu_s->cpu_type == CPU_IBM386SLC) || (cpu_s->cpu_type == CPU_IBM486SLC) || (cpu_s->cpu_type == CPU_IBM486BL);
is486 = (cpu_s->cpu_type >= CPU_RAPIDCAD);
is_am486 = (cpu_s->cpu_type == CPU_ENH_Am486DX);
is_am486dxl = (cpu_s->cpu_type == CPU_Am486DXL);
@@ -389,24 +372,19 @@ cpu_set(void)
/* SL-Enhanced Intel 486s have the same SMM save state table layout as Pentiums,
and the WinChip datasheet claims those are Pentium-compatible as well. AMD Am486DXL/DXL2 also has compatible SMM, or would if not for it's different SMBase*/
is_pentium = (cpu_isintel && (cpu_s->cpu_type >= CPU_i486SX_SLENH) && (cpu_s->cpu_type < CPU_PENTIUMPRO)) ||
!strcmp(cpu_f->manufacturer, "IDT") || (cpu_s->cpu_type == CPU_Am486DXL);
is_pentium = (cpu_isintel && (cpu_s->cpu_type >= CPU_i486SX_SLENH) && (cpu_s->cpu_type < CPU_PENTIUMPRO)) || !strcmp(cpu_f->manufacturer, "IDT") || (cpu_s->cpu_type == CPU_Am486DXL);
is_k5 = !strcmp(cpu_f->manufacturer, "AMD") && (cpu_s->cpu_type > CPU_ENH_Am486DX) && (cpu_s->cpu_type < CPU_K6);
is_k6 = (cpu_s->cpu_type >= CPU_K6) && !strcmp(cpu_f->manufacturer, "AMD");
/* The Samuel 2 datasheet claims it's Celeron-compatible. */
is_p6 = (cpu_isintel && (cpu_s->cpu_type >= CPU_PENTIUMPRO)) || !strcmp(cpu_f->manufacturer, "VIA");
is_cxsmm = (!strcmp(cpu_f->manufacturer, "Cyrix") || !strcmp(cpu_f->manufacturer, "ST")) &&
(cpu_s->cpu_type >= CPU_Cx486S);
is_cxsmm = (!strcmp(cpu_f->manufacturer, "Cyrix") || !strcmp(cpu_f->manufacturer, "ST")) && (cpu_s->cpu_type >= CPU_Cx486S);
cpu_isintel = cpu_isintel || !strcmp(cpu_f->manufacturer, "AMD");
hasfpu = (fpu_type != FPU_NONE);
hascache = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC) ||
(cpu_s->cpu_type == CPU_IBM486SLC) || (cpu_s->cpu_type == CPU_IBM486BL);
hascache = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC) || (cpu_s->cpu_type == CPU_IBM486SLC) || (cpu_s->cpu_type == CPU_IBM486BL);
cpu_16bitbus = (cpu_s->cpu_type == CPU_286) || (cpu_s->cpu_type == CPU_386SX) ||
(cpu_s->cpu_type == CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC) ||
(cpu_s->cpu_type == CPU_IBM486SLC);
cpu_16bitbus = (cpu_s->cpu_type == CPU_286) || (cpu_s->cpu_type == CPU_386SX) || (cpu_s->cpu_type == CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC) || (cpu_s->cpu_type == CPU_IBM486SLC);
cpu_64bitbus = (cpu_s->cpu_type >= CPU_WINCHIP);
if (cpu_s->multi)
@@ -1391,14 +1369,12 @@ cpu_set(void)
gdbstub_cpu_init();
}
void
cpu_close(void)
{
cpu_inited = 0;
}
void
cpu_set_isa_speed(int speed)
{
@@ -1413,7 +1389,6 @@ cpu_set_isa_speed(int speed)
cpu_log("cpu_set_isa_speed(%d) = %d\n", speed, cpu_isa_speed);
}
void
cpu_set_pci_speed(int speed)
{
@@ -1439,7 +1414,6 @@ cpu_set_pci_speed(int speed)
cpu_log("cpu_set_pci_speed(%d) = %d\n", speed, cpu_pci_speed);
}
void
cpu_set_isa_pci_div(int div)
{
@@ -1453,15 +1427,13 @@ cpu_set_isa_pci_div(int div)
cpu_set_isa_speed(0);
}
void
cpu_set_agp_speed(int speed)
{
if (speed) {
cpu_agp_speed = speed;
pc_speed_changed();
}
else if (cpu_busspeed < 84000000)
} else if (cpu_busspeed < 84000000)
cpu_agp_speed = cpu_busspeed;
else if (cpu_busspeed < 120000000)
cpu_agp_speed = cpu_busspeed / 1.5;
@@ -1474,7 +1446,6 @@ cpu_set_agp_speed(int speed)
cpu_log("cpu_set_agp_speed(%d) = %d\n", speed, cpu_agp_speed);
}
char *
cpu_current_pc(char *bufp)
{
@@ -1488,7 +1459,6 @@ cpu_current_pc(char *bufp)
return (bufp);
}
void
cpu_CPUID(void)
{
@@ -2056,7 +2026,6 @@ cpu_CPUID(void)
}
}
void
cpu_ven_reset(void)
{
@@ -2087,7 +2056,6 @@ cpu_ven_reset(void)
}
}
void
cpu_RDMSR(void)
{
@@ -2145,7 +2113,8 @@ cpu_RDMSR(void)
case CPU_CYRIX3S:
EAX = EDX = 0;
switch (ECX) {
case 0x00: case 0x01:
case 0x00:
case 0x01:
break;
case 0x10:
EAX = tsc & 0xffffffff;
@@ -2184,10 +2153,22 @@ cpu_RDMSR(void)
EAX = msr.fcr2 & 0xffffffff;
EDX = msr.fcr2 >> 32;
break;
case 0x200: case 0x201: case 0x202: case 0x203:
case 0x204: case 0x205: case 0x206: case 0x207:
case 0x208: case 0x209: case 0x20a: case 0x20b:
case 0x20c: case 0x20d: case 0x20e: case 0x20f:
case 0x200:
case 0x201:
case 0x202:
case 0x203:
case 0x204:
case 0x205:
case 0x206:
case 0x207:
case 0x208:
case 0x209:
case 0x20a:
case 0x20b:
case 0x20c:
case 0x20d:
case 0x20e:
case 0x20f:
if (ECX & 1) {
EAX = msr.mtrr_physmask[(ECX - 0x200) >> 1] & 0xffffffff;
EDX = msr.mtrr_physmask[(ECX - 0x200) >> 1] >> 32;
@@ -2208,8 +2189,14 @@ cpu_RDMSR(void)
EAX = msr.mtrr_fix16k_a000 & 0xffffffff;
EDX = msr.mtrr_fix16k_a000 >> 32;
break;
case 0x268: case 0x269: case 0x26a: case 0x26b:
case 0x26c: case 0x26d: case 0x26e: case 0x26f:
case 0x268:
case 0x269:
case 0x26a:
case 0x26b:
case 0x26c:
case 0x26d:
case 0x26e:
case 0x26f:
EAX = msr.mtrr_fix4k[ECX - 0x268] & 0xffffffff;
EDX = msr.mtrr_fix4k[ECX - 0x268] >> 32;
break;
@@ -2315,7 +2302,8 @@ amd_k_invalid_rdmsr:
#endif
EAX = EDX = 0;
switch (ECX) {
case 0x00: case 0x01:
case 0x00:
case 0x01:
break;
case 0x10:
EAX = tsc & 0xffffffff;
@@ -2330,7 +2318,8 @@ amd_k_invalid_rdmsr:
case CPU_PENTIUM2D:
EAX = EDX = 0;
switch (ECX) {
case 0x00: case 0x01:
case 0x00:
case 0x01:
break;
case 0x10:
EAX = tsc & 0xffffffff;
@@ -2388,12 +2377,21 @@ amd_k_invalid_rdmsr:
EAX = msr.ecx79 & 0xffffffff;
EDX = msr.ecx79 >> 32;
break;
case 0x88: case 0x89: case 0x8a: case 0x8b:
case 0x88:
case 0x89:
case 0x8a:
case 0x8b:
EAX = msr.ecx8x[ECX - 0x88] & 0xffffffff;
EDX = msr.ecx8x[ECX - 0x88] >> 32;
break;
case 0xc1: case 0xc2: case 0xc3: case 0xc4:
case 0xc5: case 0xc6: case 0xc7: case 0xc8:
case 0xc1:
case 0xc2:
case 0xc3:
case 0xc4:
case 0xc5:
case 0xc6:
case 0xc7:
case 0xc8:
EAX = msr.ia32_pmc[ECX - 0xC1] & 0xffffffff;
EDX = msr.ia32_pmc[ECX - 0xC1] >> 32;
break;
@@ -2405,7 +2403,10 @@ amd_k_invalid_rdmsr:
EAX = msr.ecx116 & 0xffffffff;
EDX = msr.ecx116 >> 32;
break;
case 0x118: case 0x119: case 0x11a: case 0x11b:
case 0x118:
case 0x119:
case 0x11a:
case 0x11b:
EAX = msr.ecx11x[ECX - 0x118] & 0xffffffff;
EDX = msr.ecx11x[ECX - 0x118] >> 32;
break;
@@ -2457,10 +2458,22 @@ amd_k_invalid_rdmsr:
EAX = msr.ecx1e0 & 0xffffffff;
EDX = msr.ecx1e0 >> 32;
break;
case 0x200: case 0x201: case 0x202: case 0x203:
case 0x204: case 0x205: case 0x206: case 0x207:
case 0x208: case 0x209: case 0x20a: case 0x20b:
case 0x20c: case 0x20d: case 0x20e: case 0x20f:
case 0x200:
case 0x201:
case 0x202:
case 0x203:
case 0x204:
case 0x205:
case 0x206:
case 0x207:
case 0x208:
case 0x209:
case 0x20a:
case 0x20b:
case 0x20c:
case 0x20d:
case 0x20e:
case 0x20f:
if (ECX & 1) {
EAX = msr.mtrr_physmask[(ECX - 0x200) >> 1] & 0xffffffff;
EDX = msr.mtrr_physmask[(ECX - 0x200) >> 1] >> 32;
@@ -2481,8 +2494,14 @@ amd_k_invalid_rdmsr:
EAX = msr.mtrr_fix16k_a000 & 0xffffffff;
EDX = msr.mtrr_fix16k_a000 >> 32;
break;
case 0x268: case 0x269: case 0x26a: case 0x26b:
case 0x26c: case 0x26d: case 0x26e: case 0x26f:
case 0x268:
case 0x269:
case 0x26a:
case 0x26b:
case 0x26c:
case 0x26d:
case 0x26e:
case 0x26f:
EAX = msr.mtrr_fix4k[ECX - 0x268] & 0xffffffff;
EDX = msr.mtrr_fix4k[ECX - 0x268] >> 32;
break;
@@ -2494,14 +2513,24 @@ amd_k_invalid_rdmsr:
EAX = msr.mtrr_deftype & 0xffffffff;
EDX = msr.mtrr_deftype >> 32;
break;
case 0x400: case 0x404: case 0x408: case 0x40c:
case 0x400:
case 0x404:
case 0x408:
case 0x40c:
case 0x410:
EAX = msr.mca_ctl[(ECX - 0x400) >> 2] & 0xffffffff;
EDX = msr.mca_ctl[(ECX - 0x400) >> 2] >> 32;
break;
case 0x401: case 0x402: case 0x405: case 0x406:
case 0x407: case 0x409: case 0x40d: case 0x40e:
case 0x411: case 0x412:
case 0x401:
case 0x402:
case 0x405:
case 0x406:
case 0x407:
case 0x409:
case 0x40d:
case 0x40e:
case 0x411:
case 0x412:
break;
case 0x570:
EAX = msr.ecx570 & 0xffffffff;
@@ -2535,7 +2564,6 @@ i686_invalid_rdmsr:
cpu_log("RDMSR %08X %08X%08X\n", ECX, EDX, EAX);
}
void
cpu_WRMSR(void)
{
@@ -2607,7 +2635,8 @@ cpu_WRMSR(void)
case CPU_CYRIX3S:
switch (ECX) {
case 0x00: case 0x01:
case 0x00:
case 0x01:
break;
case 0x10:
tsc = EAX | ((uint64_t) EDX << 32);
@@ -2625,10 +2654,22 @@ cpu_WRMSR(void)
case 0x1109:
msr.fcr3 = EAX | ((uint64_t) EDX << 32);
break;
case 0x200: case 0x201: case 0x202: case 0x203:
case 0x204: case 0x205: case 0x206: case 0x207:
case 0x208: case 0x209: case 0x20a: case 0x20b:
case 0x20c: case 0x20d: case 0x20e: case 0x20f:
case 0x200:
case 0x201:
case 0x202:
case 0x203:
case 0x204:
case 0x205:
case 0x206:
case 0x207:
case 0x208:
case 0x209:
case 0x20a:
case 0x20b:
case 0x20c:
case 0x20d:
case 0x20e:
case 0x20f:
if (ECX & 1)
msr.mtrr_physmask[(ECX - 0x200) >> 1] = EAX | ((uint64_t) EDX << 32);
else
@@ -2643,7 +2684,14 @@ cpu_WRMSR(void)
case 0x259:
msr.mtrr_fix16k_a000 = EAX | ((uint64_t) EDX << 32);
break;
case 0x268: case 0x269: case 0x26A: case 0x26B: case 0x26C: case 0x26D: case 0x26E: case 0x26F:
case 0x268:
case 0x269:
case 0x26A:
case 0x26B:
case 0x26C:
case 0x26D:
case 0x26E:
case 0x26F:
msr.mtrr_fix4k[ECX - 0x268] = EAX | ((uint64_t) EDX << 32);
break;
case 0x2ff:
@@ -2663,7 +2711,8 @@ cpu_WRMSR(void)
case CPU_K6_2P:
case CPU_K6_3P:
switch (ECX) {
case 0x00: case 0x01:
case 0x00:
case 0x01:
break;
case 0x0e:
msr.tr12 = EAX & 0x228;
@@ -2738,7 +2787,8 @@ amd_k_invalid_wrmsr:
#endif
cpu_log("WRMSR: ECX = %08X, val = %08X%08X\n", ECX, EDX, EAX);
switch (ECX) {
case 0x00: case 0x01:
case 0x00:
case 0x01:
break;
case 0x10:
tsc = EAX | ((uint64_t) EDX << 32);
@@ -2760,7 +2810,8 @@ amd_k_invalid_wrmsr:
case CPU_PENTIUM2:
case CPU_PENTIUM2D:
switch (ECX) {
case 0x00: case 0x01:
case 0x00:
case 0x01:
if (EAX || EDX)
x86gpf(NULL, 0);
break;
@@ -2776,11 +2827,20 @@ amd_k_invalid_wrmsr:
case 0x79:
msr.ecx79 = EAX | ((uint64_t) EDX << 32);
break;
case 0x88: case 0x89: case 0x8a: case 0x8b:
case 0x88:
case 0x89:
case 0x8a:
case 0x8b:
msr.ecx8x[ECX - 0x88] = EAX | ((uint64_t) EDX << 32);
break;
case 0xc1: case 0xc2: case 0xc3: case 0xc4:
case 0xc5: case 0xc6: case 0xc7: case 0xc8:
case 0xc1:
case 0xc2:
case 0xc3:
case 0xc4:
case 0xc5:
case 0xc6:
case 0xc7:
case 0xc8:
msr.ia32_pmc[ECX - 0xC1] = EAX | ((uint64_t) EDX << 32);
break;
case 0xfe:
@@ -2789,7 +2849,10 @@ amd_k_invalid_wrmsr:
case 0x116:
msr.ecx116 = EAX | ((uint64_t) EDX << 32);
break;
case 0x118: case 0x119: case 0x11a: case 0x11b:
case 0x118:
case 0x119:
case 0x11a:
case 0x11b:
msr.ecx11x[ECX - 0x118] = EAX | ((uint64_t) EDX << 32);
break;
case 0x11e:
@@ -2831,10 +2894,22 @@ amd_k_invalid_wrmsr:
case 0x1e0:
msr.ecx1e0 = EAX | ((uint64_t) EDX << 32);
break;
case 0x200: case 0x201: case 0x202: case 0x203:
case 0x204: case 0x205: case 0x206: case 0x207:
case 0x208: case 0x209: case 0x20a: case 0x20b:
case 0x20c: case 0x20d: case 0x20e: case 0x20f:
case 0x200:
case 0x201:
case 0x202:
case 0x203:
case 0x204:
case 0x205:
case 0x206:
case 0x207:
case 0x208:
case 0x209:
case 0x20a:
case 0x20b:
case 0x20c:
case 0x20d:
case 0x20e:
case 0x20f:
if (ECX & 1)
msr.mtrr_physmask[(ECX - 0x200) >> 1] = EAX | ((uint64_t) EDX << 32);
else
@@ -2849,8 +2924,14 @@ amd_k_invalid_wrmsr:
case 0x259:
msr.mtrr_fix16k_a000 = EAX | ((uint64_t) EDX << 32);
break;
case 0x268: case 0x269: case 0x26a: case 0x26b:
case 0x26c: case 0x26d: case 0x26e: case 0x26f:
case 0x268:
case 0x269:
case 0x26a:
case 0x26b:
case 0x26c:
case 0x26d:
case 0x26e:
case 0x26f:
msr.mtrr_fix4k[ECX - 0x268] = EAX | ((uint64_t) EDX << 32);
break;
case 0x277:
@@ -2859,13 +2940,23 @@ amd_k_invalid_wrmsr:
case 0x2ff:
msr.mtrr_deftype = EAX | ((uint64_t) EDX << 32);
break;
case 0x400: case 0x404: case 0x408: case 0x40c:
case 0x400:
case 0x404:
case 0x408:
case 0x40c:
case 0x410:
msr.mca_ctl[(ECX - 0x400) >> 2] = EAX | ((uint64_t) EDX << 32);
break;
case 0x401: case 0x402: case 0x405: case 0x406:
case 0x407: case 0x409: case 0x40d: case 0x40e:
case 0x411: case 0x412:
case 0x401:
case 0x402:
case 0x405:
case 0x406:
case 0x407:
case 0x409:
case 0x40d:
case 0x40e:
case 0x411:
case 0x412:
if (EAX || EDX)
x86gpf(NULL, 0);
break;
@@ -2894,7 +2985,6 @@ i686_invalid_wrmsr:
}
}
static void
cpu_write(uint16_t addr, uint8_t val, void *priv)
{
@@ -2910,7 +3000,8 @@ cpu_write(uint16_t addr, uint8_t val, void *priv)
if (!(addr & 1))
cyrix_addr = val;
else switch (cyrix_addr) {
else
switch (cyrix_addr) {
case 0xc0: /* CCR0 */
ccr0 = val;
break;
@@ -2976,7 +3067,6 @@ cpu_write(uint16_t addr, uint8_t val, void *priv)
}
}
static uint8_t
cpu_read(uint16_t addr, void *priv)
{
@@ -3018,7 +3108,6 @@ cpu_read(uint16_t addr, void *priv)
return 0xff;
}
void
#ifdef USE_DYNAREC
x86_setopcodes(const OpFn *opcodes, const OpFn *opcodes_0f,
@@ -3037,7 +3126,6 @@ x86_setopcodes(const OpFn *opcodes, const OpFn *opcodes_0f)
}
#endif
void
cpu_update_waitstates(void)
{

12
src/cpu/cpu.h
View File

@@ -108,7 +108,6 @@ enum {
CPU_PKG_EBGA368 = (1 << 22)
};
#define MANU_INTEL 0
#define MANU_AMD 1
#define MANU_CYRIX 2
@@ -126,7 +125,6 @@ enum {
# define LOOKUP_INV -1
#endif
typedef struct {
const char *name;
const char *internal_name;
@@ -168,8 +166,6 @@ typedef struct {
const cpu_legacy_table_t **tables;
} cpu_legacy_machine_t;
#define C_FLAG 0x0001
#define P_FLAG 0x0004
#define A_FLAG 0x0010
@@ -199,7 +195,6 @@ typedef struct {
#define IOPLp ((!(msw & 1)) || (CPL <= IOPL))
typedef union {
uint32_t l;
uint16_t w;
@@ -393,13 +388,11 @@ typedef struct {
uint32_t _smbase;
} cpu_state_t;
#define in_smm cpu_state._in_smm
#define smi_line cpu_state._smi_line
#define smbase cpu_state._smbase
/*The cpu_state.flags below must match in both cpu_cur_status and block->status for a block
to be valid*/
#define CPU_STATUS_USE32 (1 << 0)
@@ -475,7 +468,6 @@ COMPILE_TIME_ASSERT(sizeof(cpu_state_t) <= 128)
#define CR4_PCE (1 << 8)
#define CR4_OSFXSR (1 << 9)
/* Global variables. */
extern cpu_state_t cpu_state;
@@ -552,7 +544,6 @@ extern uint32_t _tr[8];
extern uint32_t cache_index;
extern uint8_t _cache[2048];
/*Segments -
_cs,_ds,_es,_ss are the segment structures
CS,DS,ES,SS is the 16-bit data
@@ -572,7 +563,6 @@ extern x86seg _oldds;
#define fs_seg cpu_state.seg_fs.base
#define gs cpu_state.seg_gs.base
#define ISA_CYCLES(x) (x * isa_cycles)
extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
@@ -608,7 +598,6 @@ extern int cpu_end_block_after_ins;
extern uint16_t cpu_fast_off_count, cpu_fast_off_val;
extern uint32_t cpu_fast_off_flags;
/* Functions. */
extern int cpu_has_feature(int feature);
@@ -716,7 +705,6 @@ typedef struct
uint32_t smhr;
} cyrix_t;
extern uint32_t addr64, addr64_2;
extern uint32_t addr64a[8], addr64a_2[8];

18
src/cpu/x87_timings.c
View File

@@ -10,8 +10,7 @@
x87_timings_t x87_timings;
x87_timings_t x87_concurrency;
const x87_timings_t x87_timings_8087 =
{
const x87_timings_t x87_timings_8087 = {
.f2xm1 = (310 + 630) / 2,
.fabs = (10 + 17) / 2,
.fadd = (70 + 100) / 2,
@@ -87,8 +86,7 @@ const x87_timings_t x87_timings_8087 =
};
/*Mostly the same as 8087*/
const x87_timings_t x87_timings_287 =
{
const x87_timings_t x87_timings_287 = {
.f2xm1 = (310 + 630) / 2,
.fabs = (10 + 17) / 2,
.fadd = (70 + 100) / 2,
@@ -163,8 +161,7 @@ const x87_timings_t x87_timings_287 =
.fyl2xp1 = (700 + 1000) / 2
};
const x87_timings_t x87_timings_387 =
{
const x87_timings_t x87_timings_387 = {
.f2xm1 = (211 + 476) / 2,
.fabs = 22,
.fadd = (23 + 34) / 2,
@@ -239,8 +236,7 @@ const x87_timings_t x87_timings_387 =
.fyl2xp1 = (257 + 547) / 2
};
const x87_timings_t x87_timings_486 =
{
const x87_timings_t x87_timings_486 = {
.f2xm1 = (140 + 270) / 2,
.fabs = 3,
.fadd = (8 + 20) / 2,
@@ -317,8 +313,7 @@ const x87_timings_t x87_timings_486 =
/* this should be used for FPUs with no concurrency.
some pre-486DX Cyrix FPUs reportedly are like this. */
const x87_timings_t x87_concurrency_none =
{
const x87_timings_t x87_concurrency_none = {
.f2xm1 = 0,
.fabs = 0,
.fadd = 0,
@@ -393,8 +388,7 @@ const x87_timings_t x87_concurrency_none =
.fyl2xp1 = 0,
};
const x87_timings_t x87_concurrency_486 =
{
const x87_timings_t x87_concurrency_486 = {
.f2xm1 = 2,
.fabs = 0,
.fadd = 7,