From b987e7dacbc39744496835485c8b1e5c83521168 Mon Sep 17 00:00:00 2001
From: Cacodemon345 <wahil1976@outlook.com>
Date: Fri, 5 May 2023 23:50:50 +0600
Subject: [PATCH] usb: Partially implement HcInterruptEnable/Disable registers

---
 src/usb.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/src/usb.c b/src/usb.c
index 090e35bd1..12385c808 100644
--- a/src/usb.c
+++ b/src/usb.c
@@ -292,6 +292,36 @@ ohci_mmio_write(uint32_t addr, uint8_t val, void *p)
             break;
         case OHCI_HcHCCA:
             return;
+        case OHCI_HcInterruptEnable:
+            dev->ohci_mmio[addr] = (val & 0x7f);
+            dev->ohci_mmio[OHCI_HcInterruptDisable] &= ~(val & 0x7f);
+            return;
+        case OHCI_HcInterruptEnable + 1:
+        case OHCI_HcInterruptEnable + 2:
+            return;
+        case OHCI_HcInterruptEnable + 3:
+            dev->ohci_mmio[addr] = (val & 0x40);
+            dev->ohci_mmio[addr] |= (val & 0x80);
+            if (val & 0x80)
+                dev->ohci_mmio[OHCI_HcInterruptDisable + 3] &= ~0x80;
+            if (val & 0x40)
+                dev->ohci_mmio[OHCI_HcInterruptDisable + 3] &= ~0x40;
+            return;
+        case OHCI_HcInterruptDisable:
+            dev->ohci_mmio[addr] = (val & 0x7f);
+            dev->ohci_mmio[OHCI_HcInterruptEnable] &= ~(val & 0x7f);
+            return;
+        case OHCI_HcInterruptDisable + 1:
+        case OHCI_HcInterruptDisable + 2:
+            return;
+        case OHCI_HcInterruptDisable + 3:
+            dev->ohci_mmio[addr] = (val & 0x40);
+            dev->ohci_mmio[addr] |= (val & 0x80);
+            if (val & 0x80)
+                dev->ohci_mmio[OHCI_HcInterruptEnable + 3] &= ~0x80;
+            if (val & 0x40)
+                dev->ohci_mmio[OHCI_HcInterruptEnable + 3] &= ~0x40;
+            return;
         case OHCI_HcInterruptStatus:
             dev->ohci_mmio[addr] &= ~(val & 0x7f);
             return;