From ba40831002241b2ea9704b2a253dad40da7d458c Mon Sep 17 00:00:00 2001 From: OBattler Date: Wed, 13 Apr 2022 02:07:23 +0200 Subject: [PATCH] Phase 2. --- src/cpu/386_ops.h | 4 +++ src/cpu/x86_ops_bitscan.h | 54 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/src/cpu/386_ops.h b/src/cpu/386_ops.h index 4518be9a9..790216cb9 100644 --- a/src/cpu/386_ops.h +++ b/src/cpu/386_ops.h @@ -195,7 +195,11 @@ extern void x386_dynarec_log(const char *fmt, ...); #include "x86_ops_mul.h" #include "x86_ops_pmode.h" #include "x86_ops_prefix.h" +#ifdef IS_DYNAREC +#include "x86_ops_rep_dyn.h" +#else #include "x86_ops_rep.h" +#endif #include "x86_ops_ret.h" #include "x86_ops_set.h" #include "x86_ops_stack.h" diff --git a/src/cpu/x86_ops_bitscan.h b/src/cpu/x86_ops_bitscan.h index 36ae1058e..5b94e96e2 100644 --- a/src/cpu/x86_ops_bitscan.h +++ b/src/cpu/x86_ops_bitscan.h @@ -1,3 +1,24 @@ +#ifdef IS_DYNAREC +#define BS_common(start, end, dir, dest, time) \ + flags_rebuild(); \ + if (temp) \ + { \ + int c; \ + cpu_state.flags &= ~Z_FLAG; \ + for (c = start; c != end; c += dir) \ + { \ + CLOCK_CYCLES(time); \ + instr_cycles += time; \ + if (temp & (1 << c)) \ + { \ + dest = c; \ + break; \ + } \ + } \ + } \ + else \ + cpu_state.flags |= Z_FLAG; +#else #define BS_common(start, end, dir, dest, time) \ flags_rebuild(); \ instr_cycles = 0; \ @@ -18,11 +39,14 @@ } \ else \ cpu_state.flags |= Z_FLAG; +#endif static int opBSF_w_a16(uint32_t fetchdat) { uint16_t temp; +#ifndef IS_DYNAREC int instr_cycles = 0; +#endif fetch_ea_16(fetchdat); if (cpu_mod != 3) @@ -32,14 +56,18 @@ static int opBSF_w_a16(uint32_t fetchdat) BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3); CLOCK_CYCLES((is486) ? 6 : 10); +#ifndef IS_DYNAREC instr_cycles += ((is486) ? 6 : 10); PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0); +#enif return 0; } static int opBSF_w_a32(uint32_t fetchdat) { uint16_t temp; +#ifndef IS_DYNAREC int instr_cycles = 0; +#endif fetch_ea_32(fetchdat); if (cpu_mod != 3) @@ -49,14 +77,18 @@ static int opBSF_w_a32(uint32_t fetchdat) BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3); CLOCK_CYCLES((is486) ? 6 : 10); +#ifndef IS_DYNAREC instr_cycles += ((is486) ? 6 : 10); PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1); +#endif return 0; } static int opBSF_l_a16(uint32_t fetchdat) { uint32_t temp; +#ifndef IS_DYNAREC int instr_cycles = 0; +#endif fetch_ea_16(fetchdat); if (cpu_mod != 3) @@ -66,14 +98,18 @@ static int opBSF_l_a16(uint32_t fetchdat) BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3); CLOCK_CYCLES((is486) ? 6 : 10); +#ifndef IS_DYNAREC instr_cycles += ((is486) ? 6 : 10); PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0); +#endif return 0; } static int opBSF_l_a32(uint32_t fetchdat) { uint32_t temp; +#ifndef IS_DYNAREC int instr_cycles = 0; +#endif fetch_ea_32(fetchdat); if (cpu_mod != 3) @@ -83,15 +119,19 @@ static int opBSF_l_a32(uint32_t fetchdat) BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3); CLOCK_CYCLES((is486) ? 6 : 10); +#ifndef IS_DYNAREC instr_cycles += ((is486) ? 6 : 10); PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1); +#endif return 0; } static int opBSR_w_a16(uint32_t fetchdat) { uint16_t temp; +#ifndef IS_DYNAREC int instr_cycles = 0; +#endif fetch_ea_16(fetchdat); if (cpu_mod != 3) @@ -101,14 +141,18 @@ static int opBSR_w_a16(uint32_t fetchdat) BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3); CLOCK_CYCLES((is486) ? 6 : 10); +#ifndef IS_DYNAREC instr_cycles += ((is486) ? 6 : 10); PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0); +#endif return 0; } static int opBSR_w_a32(uint32_t fetchdat) { uint16_t temp; +#ifndef IS_DYNAREC int instr_cycles = 0; +#endif fetch_ea_32(fetchdat); if (cpu_mod != 3) @@ -118,14 +162,18 @@ static int opBSR_w_a32(uint32_t fetchdat) BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3); CLOCK_CYCLES((is486) ? 6 : 10); +#ifndef IS_DYNAREC instr_cycles += ((is486) ? 6 : 10); PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1); +#endif return 0; } static int opBSR_l_a16(uint32_t fetchdat) { uint32_t temp; +#ifndef IS_DYNAREC int instr_cycles = 0; +#enif fetch_ea_16(fetchdat); if (cpu_mod != 3) @@ -135,14 +183,18 @@ static int opBSR_l_a16(uint32_t fetchdat) BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3); CLOCK_CYCLES((is486) ? 6 : 10); +#ifndef IS_DYNAREC instr_cycles += ((is486) ? 6 : 10); PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0); +#endif return 0; } static int opBSR_l_a32(uint32_t fetchdat) { uint32_t temp; +#ifndef IS_DYNAREC int instr_cycles = 0; +#endif fetch_ea_32(fetchdat); if (cpu_mod != 3) @@ -152,7 +204,9 @@ static int opBSR_l_a32(uint32_t fetchdat) BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3); CLOCK_CYCLES((is486) ? 6 : 10); +#ifndef IS_DYNAREC instr_cycles += ((is486) ? 6 : 10); PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1); +#enif return 0; }