From f831d3dd7c3962b43ca990f71436a262154b91e4 Mon Sep 17 00:00:00 2001 From: Winins Date: Wed, 8 Jul 2020 10:06:26 +0300 Subject: [PATCH 1/4] Update the website address on version.h and fix a typo on README.md. --- README.md | 2 +- src/include/86box/version.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 080e2d1c9..c2e7b8e97 100644 --- a/README.md +++ b/README.md @@ -55,5 +55,5 @@ Donations We do not charge you for the emulator but donations are still welcome: https://paypal.me/86Box. -You can now also support the project on Pateron: +You can now also support the project on Patreon: https://www.patreon.com/86box. diff --git a/src/include/86box/version.h b/src/include/86box/version.h index ee5dbba80..7691bdab4 100644 --- a/src/include/86box/version.h +++ b/src/include/86box/version.h @@ -25,5 +25,5 @@ #define COPYRIGHT_YEAR "2020" /* Web URL info. */ -#define EMU_SITE L"86box.github.io" +#define EMU_SITE L"86box.net" #define EMU_ROMS_URL L"https://github.com/86Box/roms/releases/latest" \ No newline at end of file From 263c48a49b0a2bd28432d5f1646388a533857c7f Mon Sep 17 00:00:00 2001 From: nerd73 Date: Wed, 8 Jul 2020 01:41:18 -0600 Subject: [PATCH 2/4] Implement F0000-FFFFF shadowing on the OPTi 291 The datasheet only gave a small reference to it in passing. Port 92 is also implemented as it is also present on the 291. --- src/chipset/opti291.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/src/chipset/opti291.c b/src/chipset/opti291.c index cad4341a9..f9dadc72f 100644 --- a/src/chipset/opti291.c +++ b/src/chipset/opti291.c @@ -35,33 +35,41 @@ typedef struct { uint8_t index, regs[256]; + port_92_t *port_92; } opti291_t; static void opti291_recalc(opti291_t *dev) { uint32_t base; - uint32_t i, shflags, write = 0; - + uint32_t i, shflags, write, writef = 0; + + + writef = (dev->regs[0x27] & 0x80) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; + if (!(dev->regs[0x23] & 0x40)) + mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | writef); + else + mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | writef); + for (i = 0; i < 4; i++) { base = 0xe0000 + (i << 14); shflags = (dev->regs[0x24] & (1 << (i+4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - shflags |= (dev->regs[0x24] & (1 << (i))) ? write : MEM_WRITE_EXTANY; - write = (dev->regs[0x27] & 0x40) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; + write = (dev->regs[0x24] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; + shflags |= (dev->regs[0x27] & 0x40) ? MEM_WRITE_DISABLED : write; mem_set_mem_state(base, 0x4000, shflags); } for (i = 0; i < 4; i++) { base = 0xd0000 + (i << 14); shflags = (dev->regs[0x25] & (1 << (i+4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - shflags |= (dev->regs[0x25] & (1 << (i))) ? write : MEM_WRITE_EXTANY; - write = (dev->regs[0x27] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; + write = (dev->regs[0x25] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; + shflags |= (dev->regs[0x27] & 0x20) ? MEM_WRITE_DISABLED : write; mem_set_mem_state(base, 0x4000, shflags); } for (i = 0; i < 4; i++) { base = 0xc0000 + (i << 14); shflags = (dev->regs[0x26] & (1 << (i+4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - shflags |= (dev->regs[0x26] & (1 << i)) ? write : MEM_WRITE_EXTANY; - write = (dev->regs[0x27] & 0x10) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; + write = (dev->regs[0x26] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; + shflags |= (dev->regs[0x27] & 0x10) ? MEM_WRITE_DISABLED : write; mem_set_mem_state(base, 0x4000, shflags); } flushmmucache(); @@ -83,10 +91,11 @@ opti291_write(uint16_t addr, uint8_t val, void *priv) case 0x21: cpu_update_waitstates(); break; + case 0x23: case 0x24: case 0x25: case 0x26: - case 0x27: + case 0x27: opti291_recalc(dev); break; } @@ -103,6 +112,7 @@ opti291_read(uint16_t addr, void *priv) switch (addr) { case 0x24: +// pclog("OPTi 291: read from dev->regs[%02x]\n", dev->index); ret = dev->regs[dev->index]; break; } @@ -128,7 +138,8 @@ opti291_init(const device_t *info) io_sethandler(0x022, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev); io_sethandler(0x024, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev); - + dev->regs[0x23] = 0x40; + dev->port_92 = device_add(&port_92_device); opti291_recalc(dev); return dev; From 845e2fdb6e36b123c13d8a04fabf4d6ef3e5cb01 Mon Sep 17 00:00:00 2001 From: nerd73 Date: Wed, 8 Jul 2020 01:50:40 -0600 Subject: [PATCH 3/4] also, remove the hdc flag as it has no internal hdc --- src/machine/machine_table.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 4376f9dc6..117b850a0 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -173,7 +173,7 @@ const machine_t machines[] = { { "[SCAT] KMX-C-02", "kmxc02", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 127, machine_at_kmxc02_init, NULL }, { "[Intel 82335] Shuttle 386SX", "shuttle386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_shuttle386sx_init, NULL }, { "[Intel 82335] ADI 386SX", "adi386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_adi386sx_init, NULL }, - { "[OPTi 291] DTK Award 386SX", "awardsx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_awardsx_init, NULL }, + { "[OPTi 291] DTK Award 386SX", "awardsx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_awardsx_init, NULL }, /* 386SX machines which utilize the MCA bus */ { "[MCA] IBM PS/2 model 55SX", "ibmps2_m55sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"IBM",cpus_IBM486SLC},{"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 8, 1, 63, machine_ps2_model_55sx_init, NULL }, From 5a862e9551481972813a92e2964c2dc541333f10 Mon Sep 17 00:00:00 2001 From: OBattler Date: Thu, 9 Jul 2020 19:28:47 +0200 Subject: [PATCH 4/4] Fixed 440GX ID without AGP and the FDC now causes the CPU to run the timers on MSR read when the recompiler is used. --- src/chipset/intel_4x0.c | 2 +- src/floppy/fdc.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c index 7d5c6f43c..492b4ef4f 100644 --- a/src/chipset/intel_4x0.c +++ b/src/chipset/intel_4x0.c @@ -1571,7 +1571,7 @@ static void regs[0x7a] = (info->local >> 8) & 0xff; dev->max_func = (regs[0x7a] & 0x02) ? 0 : 1; - regs[0x02] = 0xa0; regs[0x03] = 0x71; /* 82443GX */ + regs[0x02] = (regs[0x7a] & 0x02) ? 0xa2 : 0xa0; regs[0x03] = 0x71; /* 82443GX */ regs[0x06] = (regs[0x7a] & 0x02) ? 0x00 : 0x10; regs[0x08] = 0x02; regs[0x10] = 0x08; diff --git a/src/floppy/fdc.c b/src/floppy/fdc.c index 3be66cf0f..c49ba984d 100644 --- a/src/floppy/fdc.c +++ b/src/floppy/fdc.c @@ -1350,6 +1350,10 @@ fdc_read(uint16_t addr, void *priv) break; case 4: /*Status*/ ret = fdc->stat; +#ifdef USE_DYNAREC + if (cpu_use_dynarec) + update_tsc(); +#endif break; case 5: /*Data*/ if ((fdc->stat & 0xf0) == 0xf0) {