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Reverted the PIT structure to Mainline, fixes NT 4.0;

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THe RTL8029/AS PCI IRQ field is now hardwired, makes it work on chipsets using the PIIX3 chip (mostly boards based on 430VX and 440FX);
Fixed S3 Trio64 rendering in NT 4.0.
This commit is contained in:
OBattler
2016-11-05 07:17:08 +01:00
parent 0e3990aa29
commit c376302ad3
3 changed files with 16 additions and 12 deletions
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10
src/ibm.h
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@@ -265,8 +265,8 @@ extern int cpl_override;
/*Timer*/ /*Timer*/
typedef struct PIT typedef struct PIT
{ {
uint64_t l[3]; uint32_t l[3];
int64_t c[3]; int c[3];
uint8_t m[3]; uint8_t m[3];
uint8_t ctrl,ctrls[3]; uint8_t ctrl,ctrls[3];
int wp,rm[3],wm[3]; int wp,rm[3],wm[3];
@@ -276,9 +276,9 @@ typedef struct PIT
int rereadlatch[3]; int rereadlatch[3];
int gate[3]; int gate[3];
int out[3]; int out[3];
int64_t running[3]; int running[3];
int64_t enabled[3]; int enabled[3];
int64_t newcount[3]; int newcount[3];
int count[3]; int count[3];
int using_timer[3]; int using_timer[3];
int initial[3]; int initial[3];

6
src/ne2000.c
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@@ -1698,6 +1698,9 @@ void ne2000_pci_write(int func, int addr, uint8_t val, void *p)
ne2000_update_bios(ne2000); ne2000_update_bios(ne2000);
return; return;
/* Commented out until an APIC controller is emulated for the PIIX3,
otherwise the RTL-8029/AS will not get an IRQ on boards using the PIIX3. */
#if 0
case 0x3C: case 0x3C:
ne2000_pci_regs[addr] = val; ne2000_pci_regs[addr] = val;
if (val != 0xFF) if (val != 0xFF)
@@ -1706,7 +1709,8 @@ void ne2000_pci_write(int func, int addr, uint8_t val, void *p)
ne2000_setirq(ne2000, val); ne2000_setirq(ne2000, val);
} }
return; return;
} #endif
}
} }
void ne2000_rom_init(ne2000_t *ne2000, char *s) void ne2000_rom_init(ne2000_t *ne2000, char *s)

12
src/vid_s3.c
View File

@@ -877,19 +877,19 @@ void s3_out(uint16_t addr, uint8_t val, void *p)
break; break;
case 0x58: case 0x58:
s3_update_linear_size(s3); s3_update_linear_size(s3);
s3->linear_base &= ((s3->linear_size - 1) ^ 0xffffffff); // s3->linear_base &= ((s3->linear_size - 1) ^ 0xffffffff);
s3_updatemapping(s3); s3_updatemapping(s3);
break; break;
case 0x59: case 0x59:
s3->linear_base &= 0x00ffffff; s3->linear_base &= 0x00ffffff;
s3->linear_base |= (((uint32_t) val) << 24); s3->linear_base |= (((uint32_t) val) << 24);
s3->linear_base &= ((s3->linear_size - 1) ^ 0xffffffff); // s3->linear_base &= ((s3->linear_size - 1) ^ 0xffffffff);
s3_updatemapping(s3); s3_updatemapping(s3);
break; break;
case 0x5a: case 0x5a:
s3->linear_base &= 0xff00ffff; s3->linear_base &= 0xff00ffff;
s3->linear_base |= (((uint32_t) val) << 16); s3->linear_base |= (((uint32_t) val) << 16);
s3->linear_base &= ((s3->linear_size - 1) ^ 0xffffffff); // s3->linear_base &= ((s3->linear_size - 1) ^ 0xffffffff);
s3_updatemapping(s3); s3_updatemapping(s3);
break; break;
@@ -1146,7 +1146,7 @@ void s3_updatemapping(s3_t *s3)
lbase = s3->linear_base; lbase = s3->linear_base;
} }
svga->linear_base = lbase; svga->linear_base = lbase & ((s3->linear_size - 1) ^ 0xffffffff);
if (lbase == 0xa0000) if (lbase == 0xa0000)
{ {
@@ -2181,8 +2181,8 @@ uint8_t s3_pci_read(int func, int addr, void *p)
case 0x10: return 0x00; /*Linear frame buffer address*/ case 0x10: return 0x00; /*Linear frame buffer address*/
case 0x11: return 0x00; case 0x11: return 0x00;
case 0x12: return (s3->linear_base >> 16) & 0xff; case 0x12: return ((s3->linear_base & ((s3->linear_size - 1) ^ 0xffffffff)) >> 16) & 0xff;
case 0x13: return (s3->linear_base >> 24) & 0xff; case 0x13: return ((s3->linear_base & ((s3->linear_size - 1) ^ 0xffffffff)) >> 24) & 0xff;
case 0x30: return s3->pci_regs[0x30] & 0x01; /*BIOS ROM address*/ case 0x30: return s3->pci_regs[0x30] & 0x01; /*BIOS ROM address*/
case 0x31: return 0x00; case 0x31: return 0x00;