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Merge pull request #1306 from 86Box/tc1995

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Fixed 1280x1024x8bpp mode in the 928.
This commit is contained in:
Miran Grča
2021-03-16 17:09:10 +01:00
committed by GitHub
parent 82b26f75be 2d79719df5
commit c5773cd371
4 changed files with 534 additions and 170 deletions
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4
src/include/86box/video.h
View File

@@ -260,8 +260,12 @@ extern const device_t et4000_kasan_isa_device;
extern const device_t et4000_mca_device; extern const device_t et4000_mca_device;
/* Tseng ET4000-W32p */ /* Tseng ET4000-W32p */
extern const device_t et4000w32_device;
extern const device_t et4000w32i_device;
extern const device_t et4000w32p_vlb_device; extern const device_t et4000w32p_vlb_device;
extern const device_t et4000w32p_pci_device; extern const device_t et4000w32p_pci_device;
extern const device_t et4000w32p_noncardex_vlb_device;
extern const device_t et4000w32p_noncardex_pci_device;
extern const device_t et4000w32p_cardex_vlb_device; extern const device_t et4000w32p_cardex_vlb_device;
extern const device_t et4000w32p_cardex_pci_device; extern const device_t et4000w32p_cardex_pci_device;

560
src/video/vid_et4000w32.c
View File

@@ -39,8 +39,10 @@
#define BIOS_ROM_PATH_DIAMOND L"roms/video/et4000w32/et4000w32.bin" #define BIOS_ROM_PATH_DIAMOND L"roms/video/et4000w32/et4000w32.bin"
#define BIOS_ROM_PATH_CARDEX L"roms/video/et4000w32/cardex.vbi" #define BIOS_ROM_PATH_CARDEX L"roms/video/et4000w32/et4000w32pcardex.BIN"
#define BIOS_ROM_PATH_W32 L"roms/video/et4000w32/et4000w32isa.BIN"
#define BIOS_ROM_PATH_W32I L"roms/video/et4000w32/ET4KW32I.VBI"
#define BIOS_ROM_PATH_W32P L"roms/video/et4000w32/tsenget4000w32ppci.BIN"
#define FIFO_SIZE 65536 #define FIFO_SIZE 65536
#define FIFO_MASK (FIFO_SIZE - 1) #define FIFO_MASK (FIFO_SIZE - 1)
@@ -53,11 +55,11 @@
#define FIFO_TYPE 0xff000000 #define FIFO_TYPE 0xff000000
#define FIFO_ADDR 0x00ffffff #define FIFO_ADDR 0x00ffffff
enum #define ET4000W32 0
{ #define ET4000W32I 1
ET4000W32_CARDEX = 0, #define ET4000W32P 2
ET4000W32_DIAMOND #define ET4000W32_CARDEX 3
}; #define ET4000W32_DIAMOND 4
enum enum
{ {
@@ -83,6 +85,7 @@ typedef struct et4000w32p_t
int index; int index;
int pci; int pci;
int isa;
uint8_t regs[256]; uint8_t regs[256];
uint32_t linearbase, linearbase_old; uint32_t linearbase, linearbase_old;
uint32_t vram_mask; uint32_t vram_mask;
@@ -100,7 +103,7 @@ typedef struct et4000w32p_t
{ {
uint32_t pattern_addr,source_addr,dest_addr,mix_addr; uint32_t pattern_addr,source_addr,dest_addr,mix_addr;
uint16_t pattern_off,source_off,dest_off,mix_off; uint16_t pattern_off,source_off,dest_off,mix_off;
uint8_t pixel_depth,xy_dir; uint8_t vbus, pixel_depth,xy_dir;
uint8_t pattern_wrap,source_wrap; uint8_t pattern_wrap,source_wrap;
uint16_t count_x,count_y; uint16_t count_x,count_y;
uint8_t ctrl_routing,ctrl_reload; uint8_t ctrl_routing,ctrl_reload;
@@ -118,6 +121,8 @@ typedef struct et4000w32p_t
uint64_t cpu_dat; uint64_t cpu_dat;
int cpu_dat_pos; int cpu_dat_pos;
int pix_pos; int pix_pos;
uint32_t cpu_input;
int cpu_input_num;
} acl; } acl;
struct struct
@@ -143,6 +148,7 @@ typedef struct et4000w32p_t
static video_timings_t timing_et4000w32_vlb = {VIDEO_BUS, 4, 4, 4, 10, 10, 10}; static video_timings_t timing_et4000w32_vlb = {VIDEO_BUS, 4, 4, 4, 10, 10, 10};
static video_timings_t timing_et4000w32_pci = {VIDEO_PCI, 4, 4, 4, 10, 10, 10}; static video_timings_t timing_et4000w32_pci = {VIDEO_PCI, 4, 4, 4, 10, 10, 10};
static video_timings_t timing_et4000w32_isa = {VIDEO_ISA, 4, 4, 4, 10, 10, 10};
void et4000w32p_recalcmapping(et4000w32p_t *et4000); void et4000w32p_recalcmapping(et4000w32p_t *et4000);
@@ -150,8 +156,9 @@ uint8_t et4000w32p_mmu_read(uint32_t addr, void *p);
void et4000w32p_mmu_write(uint32_t addr, uint8_t val, void *p); void et4000w32p_mmu_write(uint32_t addr, uint8_t val, void *p);
void et4000w32_blit_start(et4000w32p_t *et4000); void et4000w32_blit_start(et4000w32p_t *et4000);
void et4000w32p_blit_start(et4000w32p_t *et4000);
void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et4000w32p_t *et4000); void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et4000w32p_t *et4000);
void et4000w32p_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et4000w32p_t *et4000);
#ifdef ENABLE_ET4000W32_LOG #ifdef ENABLE_ET4000W32_LOG
int et4000w32_do_log = ENABLE_ET4000W32_LOG; int et4000w32_do_log = ENABLE_ET4000W32_LOG;
@@ -175,6 +182,8 @@ et4000w32_log(const char *fmt, ...)
uint8_t et4000w32p_in(uint16_t addr, void *p); uint8_t et4000w32p_in(uint16_t addr, void *p);
static int et4000w32_vbus[4]={1,2,4,4};
void et4000w32p_out(uint16_t addr, uint8_t val, void *p) void et4000w32p_out(uint16_t addr, uint8_t val, void *p)
{ {
et4000w32p_t *et4000 = (et4000w32p_t *)p; et4000w32p_t *et4000 = (et4000w32p_t *)p;
@@ -225,7 +234,7 @@ void et4000w32p_out(uint16_t addr, uint8_t val, void *p)
} }
break; break;
case 0x3D4: case 0x3D4:
svga->crtcreg = val & 63; svga->crtcreg = val & 0x3f;
return; return;
case 0x3D5: case 0x3D5:
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80)) if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
@@ -320,8 +329,23 @@ uint8_t et4000w32p_in(uint16_t addr, void *p)
return et4000->index; return et4000->index;
case 0x210B: case 0x211B: case 0x212B: case 0x213B: case 0x210B: case 0x211B: case 0x212B: case 0x213B:
case 0x214B: case 0x215B: case 0x216B: case 0x217B: case 0x214B: case 0x215B: case 0x216B: case 0x217B:
if (et4000->index==0xec) if (et4000->index==0xec) {
if (et4000->type == ET4000W32I)
return (et4000->regs[0xec] & 0xf) | 0x30; /*ET4000/W32i rev B*/
else if (et4000->type == ET4000W32)
return (et4000->regs[0xec] & 0xf); /*ET4000/W32*/
else if (et4000->type == ET4000W32P || et4000->type == ET4000W32_DIAMOND) {
if (et4000->pci)
return (et4000->regs[0xec] & 0xf) | 0xe0; /*ET4000/W32p rev D*/
else
return (et4000->regs[0xec] & 0xf) | 0x60; /*ET4000/W32p rev D*/ return (et4000->regs[0xec] & 0xf) | 0x60; /*ET4000/W32p rev D*/
} else {
if (et4000->pci)
return (et4000->regs[0xec] & 0xf) | 0xf0; /*ET4000/W32p rev C*/
else
return (et4000->regs[0xec] & 0xf) | 0x70; /*ET4000/W32p rev C*/
}
}
if (et4000->index == 0xee) /*Preliminary implementation*/ if (et4000->index == 0xee) /*Preliminary implementation*/
{ {
if (svga->bpp == 8) if (svga->bpp == 8)
@@ -333,8 +357,21 @@ uint8_t et4000w32p_in(uint16_t addr, void *p)
} }
if (et4000->index == 0xef) if (et4000->index == 0xef)
{ {
if (et4000->pci) return et4000->regs[0xef] | 0xe0; /*PCI*/ if (et4000->type == ET4000W32I)
else return et4000->regs[0xef] | 0x60; /*VESA local bus*/ return et4000->regs[0xef] | 0x30; /*ET4000/W32i rev B*/
else if (et4000->type == ET4000W32)
return et4000->regs[0xef]; /*ET4000/W32*/
else if (et4000->type == ET4000W32P || et4000->type == ET4000W32_DIAMOND) {
if (et4000->pci)
return et4000->regs[0xef] | 0xe0; /*ET4000/W32p rev D*/
else
return et4000->regs[0xef] | 0x60; /*ET4000/W32p rev D*/
} else {
if (et4000->pci)
return et4000->regs[0xec] | 0xf0; /*ET4000/W32p rev C*/
else
return et4000->regs[0xec] | 0x70; /*ET4000/W32p rev C*/
}
} }
return et4000->regs[et4000->index]; return et4000->regs[et4000->index];
} }
@@ -343,6 +380,8 @@ uint8_t et4000w32p_in(uint16_t addr, void *p)
void et4000w32p_recalctimings(svga_t *svga) void et4000w32p_recalctimings(svga_t *svga)
{ {
et4000w32p_t *et4000 = (et4000w32p_t *)svga->p;
svga->ma_latch |= (svga->crtc[0x33] & 0x7) << 16; svga->ma_latch |= (svga->crtc[0x33] & 0x7) << 16;
if (svga->crtc[0x35] & 0x01) svga->vblankstart += 0x400; if (svga->crtc[0x35] & 0x01) svga->vblankstart += 0x400;
if (svga->crtc[0x35] & 0x02) svga->vtotal += 0x400; if (svga->crtc[0x35] & 0x02) svga->vtotal += 0x400;
@@ -355,19 +394,7 @@ void et4000w32p_recalctimings(svga_t *svga)
svga->clock = (cpuclock * (double)(1ull << 32)) / svga->getclock((svga->miscout >> 2) & 3, svga->clock_gen); svga->clock = (cpuclock * (double)(1ull << 32)) / svga->getclock((svga->miscout >> 2) & 3, svga->clock_gen);
if (svga->adv_flags & FLAG_NOSKEW) { switch (svga->bpp) {
/* On the Cardex ET4000/W32p, adjust text mode clocks by 1. */
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) { /*Text mode*/
svga->ma_latch--;
if ((svga->seqregs[1] & 8)) /*40 column*/
svga->hdisp += (svga->seqregs[1] & 1) ? 16 : 18;
else
svga->hdisp += (svga->seqregs[1] & 1) ? 8 : 9;
}
}
switch (svga->bpp)
{
case 15: case 16: case 15: case 16:
svga->hdisp >>= 1; svga->hdisp >>= 1;
break; break;
@@ -398,6 +425,9 @@ void et4000w32p_recalctimings(svga_t *svga)
svga->render = svga_render_2bpp_highres; svga->render = svga_render_2bpp_highres;
break; break;
case 0x40: case 0x60: /*256+ colours*/ case 0x40: case 0x60: /*256+ colours*/
if (et4000->type != ET4000W32_DIAMOND)
svga->clock /= 2;
switch (svga->bpp) { switch (svga->bpp) {
case 8: case 8:
svga->map8 = svga->pallook; svga->map8 = svga->pallook;
@@ -441,7 +471,7 @@ void et4000w32p_recalcmapping(et4000w32p_t *et4000)
{ {
svga_t *svga = &et4000->svga; svga_t *svga = &et4000->svga;
if (!(et4000->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) if (et4000->pci && !(et4000->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))
{ {
mem_mapping_disable(&svga->mapping); mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&et4000->linear_mapping); mem_mapping_disable(&et4000->linear_mapping);
@@ -465,7 +495,7 @@ void et4000w32p_recalcmapping(et4000w32p_t *et4000)
case 0x0: case 0x4: case 0x8: case 0xC: /*128k at A0000*/ case 0x0: case 0x4: case 0x8: case 0xC: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000); mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
mem_mapping_disable(&et4000->mmu_mapping); mem_mapping_disable(&et4000->mmu_mapping);
svga->banked_mask = 0x1ffff; svga->banked_mask = 0xffff;
break; break;
case 0x1: /*64k at A0000*/ case 0x1: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
@@ -503,7 +533,7 @@ void et4000w32p_recalcmapping(et4000w32p_t *et4000)
} }
et4000->linearbase_old = et4000->linearbase; et4000->linearbase_old = et4000->linearbase;
if (!et4000->interleaved && (et4000->svga.crtc[0x32] & 0x80)) if (!et4000->interleaved && (svga->crtc[0x32] & 0x80))
mem_mapping_disable(&svga->mapping); mem_mapping_disable(&svga->mapping);
} }
@@ -530,30 +560,53 @@ static void et4000w32p_accel_write_fifo(et4000w32p_t *et4000, uint32_t addr, uin
case 0x7f8b: et4000->acl.queued.source_off = (et4000->acl.queued.source_off & 0x00FF) | (val << 8); break; case 0x7f8b: et4000->acl.queued.source_off = (et4000->acl.queued.source_off & 0x00FF) | (val << 8); break;
case 0x7f8c: et4000->acl.queued.dest_off = (et4000->acl.queued.dest_off & 0xFF00) | val; break; case 0x7f8c: et4000->acl.queued.dest_off = (et4000->acl.queued.dest_off & 0xFF00) | val; break;
case 0x7f8d: et4000->acl.queued.dest_off = (et4000->acl.queued.dest_off & 0x00FF) | (val << 8); break; case 0x7f8d: et4000->acl.queued.dest_off = (et4000->acl.queued.dest_off & 0x00FF) | (val << 8); break;
case 0x7f8e: et4000->acl.queued.pixel_depth = val; break; case 0x7f8e:
if (et4000->type < ET4000W32P)
et4000->acl.queued.vbus = val;
else
et4000->acl.queued.pixel_depth = val;
break;
case 0x7f8f: et4000->acl.queued.xy_dir = val; break; case 0x7f8f: et4000->acl.queued.xy_dir = val; break;
case 0x7f90: et4000->acl.queued.pattern_wrap = val; break; case 0x7f90: et4000->acl.queued.pattern_wrap = val; break;
case 0x7f92: et4000->acl.queued.source_wrap = val; break; case 0x7f92: et4000->acl.queued.source_wrap = val; break;
case 0x7f94: et4000->acl.queued.pos_x = (et4000->acl.queued.pos_x & 0xFF00) | val; break;
case 0x7f95: et4000->acl.queued.pos_x = (et4000->acl.queued.pos_x & 0x00FF) | (val << 8); break;
case 0x7f96: et4000->acl.queued.pos_y = (et4000->acl.queued.pos_y & 0xFF00) | val; break;
case 0x7f97: et4000->acl.queued.pos_y = (et4000->acl.queued.pos_y & 0x00FF) | (val << 8); break;
case 0x7f98: et4000->acl.queued.count_x = (et4000->acl.queued.count_x & 0xFF00) | val; break; case 0x7f98: et4000->acl.queued.count_x = (et4000->acl.queued.count_x & 0xFF00) | val; break;
case 0x7f99: et4000->acl.queued.count_x = (et4000->acl.queued.count_x & 0x00FF) | (val << 8); break; case 0x7f99: et4000->acl.queued.count_x = (et4000->acl.queued.count_x & 0x00FF) | (val << 8); break;
case 0x7f9a: et4000->acl.queued.count_y = (et4000->acl.queued.count_y & 0xFF00) | val; break; case 0x7f9a: et4000->acl.queued.count_y = (et4000->acl.queued.count_y & 0xFF00) | val; break;
case 0x7f9b: et4000->acl.queued.count_y = (et4000->acl.queued.count_y & 0x00FF) | (val << 8); break; case 0x7f9b: et4000->acl.queued.count_y = (et4000->acl.queued.count_y & 0x00FF) | (val << 8); break;
case 0x7f9c: et4000->acl.queued.ctrl_routing = val; break; case 0x7f9c: et4000->acl.queued.ctrl_routing = val;
break;
case 0x7f9d: et4000->acl.queued.ctrl_reload = val; break; case 0x7f9d: et4000->acl.queued.ctrl_reload = val; break;
case 0x7f9e: et4000->acl.queued.rop_bg = val; break; case 0x7f9e: et4000->acl.queued.rop_bg = val; break;
case 0x7f9f: et4000->acl.queued.rop_fg = val; break; case 0x7f9f: et4000->acl.queued.rop_fg = val; break;
case 0x7fa0: et4000->acl.queued.dest_addr = (et4000->acl.queued.dest_addr & 0xFFFFFF00) | val; break; case 0x7fa0: et4000->acl.queued.dest_addr = (et4000->acl.queued.dest_addr & 0xFFFFFF00) | val;
case 0x7fa1: et4000->acl.queued.dest_addr = (et4000->acl.queued.dest_addr & 0xFFFF00FF) | (val << 8); break; break;
case 0x7fa2: et4000->acl.queued.dest_addr = (et4000->acl.queued.dest_addr & 0xFF00FFFF) | (val << 16); break; case 0x7fa1: et4000->acl.queued.dest_addr = (et4000->acl.queued.dest_addr & 0xFFFF00FF) | (val << 8);
break;
case 0x7fa2: et4000->acl.queued.dest_addr = (et4000->acl.queued.dest_addr & 0xFF00FFFF) | (val << 16);
break;
case 0x7fa3: et4000->acl.queued.dest_addr = (et4000->acl.queued.dest_addr & 0x00FFFFFF) | (val << 24); case 0x7fa3: et4000->acl.queued.dest_addr = (et4000->acl.queued.dest_addr & 0x00FFFFFF) | (val << 24);
et4000->acl.internal = et4000->acl.queued; et4000->acl.internal = et4000->acl.queued;
et4000w32_blit_start(et4000); if (et4000->type >= ET4000W32P) {
et4000w32p_blit_start(et4000);
if (!(et4000->acl.queued.ctrl_routing & 0x43)) if (!(et4000->acl.queued.ctrl_routing & 0x43))
{
et4000w32p_blit(0xFFFFFF, ~0, 0, 0, et4000);
}
if ((et4000->acl.queued.ctrl_routing & 0x40) && !(et4000->acl.internal.ctrl_routing & 3)) {
et4000w32p_blit(4, ~0, 0, 0, et4000);
}
} else {
et4000w32_blit_start(et4000);
et4000->acl.cpu_input_num = 0;
if (!(et4000->acl.queued.ctrl_routing & 0x37))
{ {
et4000w32_blit(0xFFFFFF, ~0, 0, 0, et4000); et4000w32_blit(0xFFFFFF, ~0, 0, 0, et4000);
} }
if ((et4000->acl.queued.ctrl_routing & 0x40) && !(et4000->acl.internal.ctrl_routing & 3)) }
et4000w32_blit(4, ~0, 0, 0, et4000);
break; break;
case 0x7fa4: et4000->acl.queued.mix_addr = (et4000->acl.queued.mix_addr & 0xFFFFFF00) | val; break; case 0x7fa4: et4000->acl.queued.mix_addr = (et4000->acl.queued.mix_addr & 0xFFFFFF00) | val; break;
case 0x7fa5: et4000->acl.queued.mix_addr = (et4000->acl.queued.mix_addr & 0xFFFF00FF) | (val << 8); break; case 0x7fa5: et4000->acl.queued.mix_addr = (et4000->acl.queued.mix_addr & 0xFFFF00FF) | (val << 8); break;
@@ -572,18 +625,21 @@ static void et4000w32p_accel_write_fifo(et4000w32p_t *et4000, uint32_t addr, uin
static void et4000w32p_accel_write_mmu(et4000w32p_t *et4000, uint32_t addr, uint8_t val) static void et4000w32p_accel_write_mmu(et4000w32p_t *et4000, uint32_t addr, uint8_t val)
{ {
if (!(et4000->acl.status & ACL_XYST)) return; if (!(et4000->acl.status & ACL_XYST)) {
return;
}
if (et4000->acl.internal.ctrl_routing & 3) if (et4000->acl.internal.ctrl_routing & 3)
{ {
if ((et4000->acl.internal.ctrl_routing & 3) == 2) if ((et4000->acl.internal.ctrl_routing & 3) == 2)
{ {
if (et4000->acl.mix_addr & 7) if (et4000->acl.mix_addr & 7)
et4000w32_blit(8 - (et4000->acl.mix_addr & 7), val >> (et4000->acl.mix_addr & 7), 0, 1, et4000); et4000w32p_blit(8 - (et4000->acl.mix_addr & 7), val >> (et4000->acl.mix_addr & 7), 0, 1, et4000);
else else
et4000w32_blit(8, val, 0, 1, et4000); et4000w32p_blit(8, val, 0, 1, et4000);
} }
else if ((et4000->acl.internal.ctrl_routing & 3) == 1) else if ((et4000->acl.internal.ctrl_routing & 3) == 1)
et4000w32_blit(1, ~0, val, 2, et4000); et4000w32p_blit(1, ~0, val, 2, et4000);
} }
} }
@@ -671,6 +727,7 @@ void et4000w32p_mmu_write(uint32_t addr, uint8_t val, void *p)
et4000w32p_t *et4000 = (et4000w32p_t *)p; et4000w32p_t *et4000 = (et4000w32p_t *)p;
svga_t *svga = &et4000->svga; svga_t *svga = &et4000->svga;
int bank; int bank;
switch (addr & 0x6000) switch (addr & 0x6000)
{ {
case 0x0000: /*MMU 0*/ case 0x0000: /*MMU 0*/
@@ -679,11 +736,41 @@ void et4000w32p_mmu_write(uint32_t addr, uint8_t val, void *p)
bank = (addr >> 13) & 3; bank = (addr >> 13) & 3;
if (et4000->mmu.ctrl & (1 << bank)) if (et4000->mmu.ctrl & (1 << bank))
{ {
if (et4000->type >= ET4000W32P)
et4000w32p_queue(et4000, addr & 0x7fff, val, FIFO_WRITE_MMU); et4000w32p_queue(et4000, addr & 0x7fff, val, FIFO_WRITE_MMU);
else {
if (!(et4000->acl.status & ACL_XYST)) {
et4000->acl.queued.dest_addr = (addr & 0x1FFF) + et4000->mmu.base[bank];
et4000->acl.internal = et4000->acl.queued;
et4000w32_blit_start(et4000);
if (!(et4000->acl.internal.ctrl_routing & 0x37))
et4000w32_blit(0xFFFFFF, ~0, 0, 0, et4000);
et4000->acl.cpu_input_num = 0;
}
if (et4000->acl.internal.ctrl_routing & 7) {
et4000->acl.cpu_input = (et4000->acl.cpu_input &~ (0xFF << (et4000->acl.cpu_input_num << 3))) | (val << (et4000->acl.cpu_input_num << 3));
et4000->acl.cpu_input_num++;
if (et4000->acl.cpu_input_num == et4000w32_vbus[et4000->acl.internal.vbus & 3])
{
if ((et4000->acl.internal.ctrl_routing & 7) == 2)
et4000w32_blit(et4000->acl.cpu_input_num << 3, et4000->acl.cpu_input, 0, 1, et4000);
else if ((et4000->acl.internal.ctrl_routing & 7) == 1)
et4000w32_blit(et4000->acl.cpu_input_num, ~0, et4000->acl.cpu_input, 2, et4000);
else if ((et4000->acl.internal.ctrl_routing & 7) == 4)
et4000w32_blit(et4000->acl.cpu_input_num, ~0, et4000->acl.internal.count_x, 2, et4000);
else if ((et4000->acl.internal.ctrl_routing & 7) == 5)
et4000w32_blit(et4000->acl.cpu_input_num, ~0, et4000->acl.internal.count_y, 2, et4000);
et4000->acl.cpu_input_num = 0;
}
}
}
} }
else else
{ {
if ((addr&0x1fff) + et4000->mmu.base[bank] < svga->vram_max) if ((addr & 0x1fff) + et4000->mmu.base[bank] < svga->vram_max)
{ {
svga->vram[(addr & 0x1fff) + et4000->mmu.base[bank]] = val; svga->vram[(addr & 0x1fff) + et4000->mmu.base[bank]] = val;
svga->changedvram[((addr & 0x1fff) + et4000->mmu.base[bank]) >> 12] = changeframecount; svga->changedvram[((addr & 0x1fff) + et4000->mmu.base[bank]) >> 12] = changeframecount;
@@ -693,28 +780,44 @@ void et4000w32p_mmu_write(uint32_t addr, uint8_t val, void *p)
case 0x6000: case 0x6000:
if ((addr & 0x7fff) >= 0x7f80) if ((addr & 0x7fff) >= 0x7f80)
{ {
if (et4000->type >= ET4000W32P)
et4000w32p_queue(et4000, addr & 0x7fff, val, FIFO_WRITE_BYTE); et4000w32p_queue(et4000, addr & 0x7fff, val, FIFO_WRITE_BYTE);
else
et4000w32p_accel_write_fifo(et4000, addr & 0x7fff, val);
} }
else switch (addr & 0x7fff) else switch (addr & 0x7fff)
{ {
case 0x7f00: et4000->mmu.base[0] = (et4000->mmu.base[0] & 0xFFFFFF00) | val; break; case 0x7f00: et4000->mmu.base[0] = (et4000->mmu.base[0] & 0xFFFFFF00) | val;
case 0x7f01: et4000->mmu.base[0] = (et4000->mmu.base[0] & 0xFFFF00FF) | (val << 8); break; break;
case 0x7f02: et4000->mmu.base[0] = (et4000->mmu.base[0] & 0xFF00FFFF) | (val << 16); break; case 0x7f01: et4000->mmu.base[0] = (et4000->mmu.base[0] & 0xFFFF00FF) | (val << 8);
case 0x7f03: et4000->mmu.base[0] = (et4000->mmu.base[0] & 0x00FFFFFF) | (val << 24); break; break;
case 0x7f04: et4000->mmu.base[1] = (et4000->mmu.base[1] & 0xFFFFFF00) | val; break; case 0x7f02: et4000->mmu.base[0] = (et4000->mmu.base[0] & 0xFF00FFFF) | (val << 16);
case 0x7f05: et4000->mmu.base[1] = (et4000->mmu.base[1] & 0xFFFF00FF) | (val << 8); break; break;
case 0x7f06: et4000->mmu.base[1] = (et4000->mmu.base[1] & 0xFF00FFFF) | (val << 16); break; case 0x7f03: et4000->mmu.base[0] = (et4000->mmu.base[0] & 0x00FFFFFF) | (val << 24);
case 0x7f07: et4000->mmu.base[1] = (et4000->mmu.base[1] & 0x00FFFFFF) | (val << 24); break; break;
case 0x7f08: et4000->mmu.base[2] = (et4000->mmu.base[2] & 0xFFFFFF00) | val; break; case 0x7f04: et4000->mmu.base[1] = (et4000->mmu.base[1] & 0xFFFFFF00) | val;
case 0x7f09: et4000->mmu.base[2] = (et4000->mmu.base[2] & 0xFFFF00FF) | (val << 8); break; break;
case 0x7f0a: et4000->mmu.base[2] = (et4000->mmu.base[2] & 0xFF00FFFF) | (val << 16); break; case 0x7f05: et4000->mmu.base[1] = (et4000->mmu.base[1] & 0xFFFF00FF) | (val << 8);
case 0x7f0d: et4000->mmu.base[2] = (et4000->mmu.base[2] & 0x00FFFFFF) | (val << 24); break; break;
case 0x7f06: et4000->mmu.base[1] = (et4000->mmu.base[1] & 0xFF00FFFF) | (val << 16);
break;
case 0x7f07: et4000->mmu.base[1] = (et4000->mmu.base[1] & 0x00FFFFFF) | (val << 24);
break;
case 0x7f08: et4000->mmu.base[2] = (et4000->mmu.base[2] & 0xFFFFFF00) | val;
break;
case 0x7f09: et4000->mmu.base[2] = (et4000->mmu.base[2] & 0xFFFF00FF) | (val << 8);
break;
case 0x7f0a: et4000->mmu.base[2] = (et4000->mmu.base[2] & 0xFF00FFFF) | (val << 16);
break;
case 0x7f0b: et4000->mmu.base[2] = (et4000->mmu.base[2] & 0x00FFFFFF) | (val << 24);
break;
case 0x7f13: et4000->mmu.ctrl=val; break; case 0x7f13: et4000->mmu.ctrl=val; break;
} }
break; break;
} }
} }
uint8_t et4000w32p_mmu_read(uint32_t addr, void *p) uint8_t et4000w32p_mmu_read(uint32_t addr, void *p)
{ {
et4000w32p_t *et4000 = (et4000w32p_t *)p; et4000w32p_t *et4000 = (et4000w32p_t *)p;
@@ -729,7 +832,9 @@ uint8_t et4000w32p_mmu_read(uint32_t addr, void *p)
bank = (addr >> 13) & 3; bank = (addr >> 13) & 3;
if (et4000->mmu.ctrl & (1 << bank)) if (et4000->mmu.ctrl & (1 << bank))
{ {
if (et4000->type >= ET4000W32P)
et4000w32p_wait_fifo_idle(et4000); et4000w32p_wait_fifo_idle(et4000);
temp = 0xff; temp = 0xff;
if (et4000->acl.cpu_dat_pos) if (et4000->acl.cpu_dat_pos)
{ {
@@ -738,17 +843,19 @@ uint8_t et4000w32p_mmu_read(uint32_t addr, void *p)
et4000->acl.cpu_dat >>= 8; et4000->acl.cpu_dat >>= 8;
} }
if ((et4000->acl.queued.ctrl_routing & 0x40) && !et4000->acl.cpu_dat_pos && !(et4000->acl.internal.ctrl_routing & 3)) if ((et4000->acl.queued.ctrl_routing & 0x40) && !et4000->acl.cpu_dat_pos && !(et4000->acl.internal.ctrl_routing & 3))
et4000w32_blit(4, ~0, 0, 0, et4000); et4000w32p_blit(4, ~0, 0, 0, et4000);
/*???*/ /*???*/
return temp; return temp;
} }
if ((addr&0x1fff) + et4000->mmu.base[bank] >= svga->vram_max) if ((addr & 0x1fff) + et4000->mmu.base[bank] >= svga->vram_max)
return 0xff; return 0xff;
return svga->vram[(addr&0x1fff) + et4000->mmu.base[bank]]; return svga->vram[(addr & 0x1fff) + et4000->mmu.base[bank]];
case 0x6000: case 0x6000:
if ((addr & 0x7fff) >= 0x7f80) if ((addr & 0x7fff) >= 0x7f80) {
if (et4000->type >= ET4000W32P)
et4000w32p_wait_fifo_idle(et4000); et4000w32p_wait_fifo_idle(et4000);
}
switch (addr&0x7fff) switch (addr&0x7fff)
{ {
case 0x7f00: return et4000->mmu.base[0]; case 0x7f00: return et4000->mmu.base[0];
@@ -766,13 +873,21 @@ uint8_t et4000w32p_mmu_read(uint32_t addr, void *p)
case 0x7f13: return et4000->mmu.ctrl; case 0x7f13: return et4000->mmu.ctrl;
case 0x7f36: case 0x7f36:
if (et4000->type >= ET4000W32P) {
temp = et4000->acl.status; temp = et4000->acl.status;
temp &= ~0x03; temp &= ~(ACL_RDST | ACL_WRST);
if (!FIFO_EMPTY) if (!FIFO_EMPTY)
temp |= 0x02; temp |= ACL_RDST;
if (FIFO_FULL) if (FIFO_FULL)
temp |= 0x01; temp |= ACL_WRST;
if (temp == ACL_XYST)
temp |= ACL_RDST;
} else {
et4000->acl.status &= ~(ACL_XYST | ACL_SSO);
temp = et4000->acl.status;
}
return temp; return temp;
case 0x7f80: return et4000->acl.internal.pattern_addr; case 0x7f80: return et4000->acl.internal.pattern_addr;
case 0x7f81: return et4000->acl.internal.pattern_addr >> 8; case 0x7f81: return et4000->acl.internal.pattern_addr >> 8;
case 0x7f82: return et4000->acl.internal.pattern_addr >> 16; case 0x7f82: return et4000->acl.internal.pattern_addr >> 16;
@@ -787,10 +902,19 @@ uint8_t et4000w32p_mmu_read(uint32_t addr, void *p)
case 0x7f8b: return et4000->acl.internal.source_off >> 8; case 0x7f8b: return et4000->acl.internal.source_off >> 8;
case 0x7f8c: return et4000->acl.internal.dest_off; case 0x7f8c: return et4000->acl.internal.dest_off;
case 0x7f8d: return et4000->acl.internal.dest_off >> 8; case 0x7f8d: return et4000->acl.internal.dest_off >> 8;
case 0x7f8e: return et4000->acl.internal.pixel_depth; case 0x7f8e:
if (et4000->type < ET4000W32P)
return et4000->acl.internal.vbus;
else
return et4000->acl.internal.pixel_depth;
break;
case 0x7f8f: return et4000->acl.internal.xy_dir; case 0x7f8f: return et4000->acl.internal.xy_dir;
case 0x7f90: return et4000->acl.internal.pattern_wrap; case 0x7f90: return et4000->acl.internal.pattern_wrap;
case 0x7f92: return et4000->acl.internal.source_wrap; case 0x7f92: return et4000->acl.internal.source_wrap;
case 0x7f94: return et4000->acl.internal.pos_x;
case 0x7f95: return et4000->acl.internal.pos_x >> 8;
case 0x7f96: return et4000->acl.internal.pos_y;
case 0x7f97: return et4000->acl.internal.pos_y >> 8;
case 0x7f98: return et4000->acl.internal.count_x; case 0x7f98: return et4000->acl.internal.count_x;
case 0x7f99: return et4000->acl.internal.count_x >> 8; case 0x7f99: return et4000->acl.internal.count_x >> 8;
case 0x7f9a: return et4000->acl.internal.count_y; case 0x7f9a: return et4000->acl.internal.count_y;
@@ -803,6 +927,14 @@ uint8_t et4000w32p_mmu_read(uint32_t addr, void *p)
case 0x7fa1: return et4000->acl.internal.dest_addr >> 8; case 0x7fa1: return et4000->acl.internal.dest_addr >> 8;
case 0x7fa2: return et4000->acl.internal.dest_addr >> 16; case 0x7fa2: return et4000->acl.internal.dest_addr >> 16;
case 0x7fa3: return et4000->acl.internal.dest_addr >> 24; case 0x7fa3: return et4000->acl.internal.dest_addr >> 24;
case 0x7fa4: return et4000->acl.internal.pattern_addr;
case 0x7fa5: return et4000->acl.internal.pattern_addr >> 8;
case 0x7fa6: return et4000->acl.internal.pattern_addr >> 16;
case 0x7fa7: return et4000->acl.internal.pattern_addr >> 24;
case 0x7fa8: return et4000->acl.internal.source_addr;
case 0x7fa9: return et4000->acl.internal.source_addr >> 8;
case 0x7faa: return et4000->acl.internal.source_addr >> 16;
case 0x7fab: return et4000->acl.internal.source_addr >> 24;
} }
return 0xff; return 0xff;
} }
@@ -813,8 +945,46 @@ static int et4000w32_max_x[8]={0,0,4,8,16,32,64,0x70000000};
static int et4000w32_wrap_x[8]={0,0,3,7,15,31,63,0xFFFFFFFF}; static int et4000w32_wrap_x[8]={0,0,3,7,15,31,63,0xFFFFFFFF};
static int et4000w32_wrap_y[8]={1,2,4,8,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF}; static int et4000w32_wrap_y[8]={1,2,4,8,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF};
/* int bltout=0; */
void et4000w32_blit_start(et4000w32p_t *et4000) void et4000w32_blit_start(et4000w32p_t *et4000)
{
et4000->acl.pattern_addr= et4000->acl.internal.pattern_addr;
et4000->acl.source_addr = et4000->acl.internal.source_addr;
et4000->acl.dest_addr = et4000->acl.internal.dest_addr;
et4000->acl.dest_back = et4000->acl.dest_addr;
et4000->acl.internal.pos_x = et4000->acl.internal.pos_y = 0;
et4000->acl.pattern_x = et4000->acl.source_x = et4000->acl.pattern_y = et4000->acl.source_y = 0;
et4000->acl.status |= ACL_XYST;
if (!(et4000->acl.internal.ctrl_routing & 7))
et4000->acl.status |= ACL_SSO;
if (et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7])
{
et4000->acl.pattern_x = et4000->acl.pattern_addr & et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7];
et4000->acl.pattern_addr &= ~et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7];
}
et4000->acl.pattern_back = et4000->acl.pattern_addr;
if (!(et4000->acl.internal.pattern_wrap & 0x40))
{
et4000->acl.pattern_y = (et4000->acl.pattern_addr / (et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7] + 1)) & (et4000w32_wrap_y[(et4000->acl.internal.pattern_wrap >> 4) & 7] - 1);
et4000->acl.pattern_back &= ~(((et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7] + 1) * et4000w32_wrap_y[(et4000->acl.internal.pattern_wrap >> 4) & 7]) - 1);
}
et4000->acl.pattern_x_back = et4000->acl.pattern_x;
if (et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7])
{
et4000->acl.source_x = et4000->acl.source_addr & et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7];
et4000->acl.source_addr &= ~et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7];
}
et4000->acl.source_back = et4000->acl.source_addr;
if (!(et4000->acl.internal.source_wrap & 0x40))
{
et4000->acl.source_y = (et4000->acl.source_addr / (et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7] + 1)) & (et4000w32_wrap_y[(et4000->acl.internal.source_wrap >> 4) & 7] - 1);
et4000->acl.source_back &= ~(((et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7] + 1) * et4000w32_wrap_y[(et4000->acl.internal.source_wrap >> 4) & 7]) - 1);
}
et4000->acl.source_x_back = et4000->acl.source_x;
}
void et4000w32p_blit_start(et4000w32p_t *et4000)
{ {
if (!(et4000->acl.queued.xy_dir & 0x20)) if (!(et4000->acl.queued.xy_dir & 0x20))
et4000->acl.internal.error = et4000->acl.internal.dmaj / 2; et4000->acl.internal.error = et4000->acl.internal.dmaj / 2;
@@ -870,27 +1040,42 @@ void et4000w32_incx(int c, et4000w32p_t *et4000)
et4000->acl.dest_addr += c; et4000->acl.dest_addr += c;
et4000->acl.pattern_x += c; et4000->acl.pattern_x += c;
et4000->acl.source_x += c; et4000->acl.source_x += c;
if (et4000->type >= ET4000W32P) {
et4000->acl.mix_addr += c; et4000->acl.mix_addr += c;
if (et4000->acl.pattern_x >= et4000w32_max_x[et4000->acl.internal.pattern_wrap & 7]) if (et4000->acl.pattern_x >= et4000w32_max_x[et4000->acl.internal.pattern_wrap & 7])
et4000->acl.pattern_x -= et4000w32_max_x[et4000->acl.internal.pattern_wrap & 7]; et4000->acl.pattern_x -= et4000w32_max_x[et4000->acl.internal.pattern_wrap & 7];
if (et4000->acl.source_x >= et4000w32_max_x[et4000->acl.internal.source_wrap & 7]) if (et4000->acl.source_x >= et4000w32_max_x[et4000->acl.internal.source_wrap & 7])
et4000->acl.source_x -= et4000w32_max_x[et4000->acl.internal.source_wrap & 7]; et4000->acl.source_x -= et4000w32_max_x[et4000->acl.internal.source_wrap & 7];
} else {
if (et4000->acl.pattern_x >= et4000w32_max_x[et4000->acl.internal.pattern_wrap & 7])
et4000->acl.pattern_x -= et4000w32_max_x[et4000->acl.internal.pattern_wrap & 7];
if (et4000->acl.source_x >= et4000w32_max_x[et4000->acl.internal.source_wrap & 7])
et4000->acl.source_x -= et4000w32_max_x[et4000->acl.internal.source_wrap & 7];
}
} }
void et4000w32_decx(int c, et4000w32p_t *et4000) void et4000w32_decx(int c, et4000w32p_t *et4000)
{ {
et4000->acl.dest_addr -= c; et4000->acl.dest_addr -= c;
et4000->acl.pattern_x -= c; et4000->acl.pattern_x -= c;
et4000->acl.source_x -= c; et4000->acl.source_x -= c;
if (et4000->type >= ET4000W32P) {
et4000->acl.mix_addr -= c; et4000->acl.mix_addr -= c;
if (et4000->acl.pattern_x < 0) if (et4000->acl.pattern_x < 0)
et4000->acl.pattern_x += et4000w32_max_x[et4000->acl.internal.pattern_wrap & 7]; et4000->acl.pattern_x += et4000w32_max_x[et4000->acl.internal.pattern_wrap & 7];
if (et4000->acl.source_x < 0) if (et4000->acl.source_x < 0)
et4000->acl.source_x += et4000w32_max_x[et4000->acl.internal.source_wrap & 7]; et4000->acl.source_x += et4000w32_max_x[et4000->acl.internal.source_wrap & 7];
} else {
if (et4000->acl.pattern_x < 0)
et4000->acl.pattern_x += et4000w32_max_x[et4000->acl.internal.pattern_wrap & 7];
if (et4000->acl.source_x < 0)
et4000->acl.source_x += et4000w32_max_x[et4000->acl.internal.source_wrap & 7];
}
} }
void et4000w32_incy(et4000w32p_t *et4000) void et4000w32_incy(et4000w32p_t *et4000)
{ {
et4000->acl.pattern_addr += et4000->acl.internal.pattern_off + 1; et4000->acl.pattern_addr += et4000->acl.internal.pattern_off + 1;
et4000->acl.source_addr += et4000->acl.internal.source_off + 1; et4000->acl.source_addr += et4000->acl.internal.source_off + 1;
if (et4000->type >= ET4000W32P)
et4000->acl.mix_addr += et4000->acl.internal.mix_off + 1; et4000->acl.mix_addr += et4000->acl.internal.mix_off + 1;
et4000->acl.dest_addr += et4000->acl.internal.dest_off + 1; et4000->acl.dest_addr += et4000->acl.internal.dest_off + 1;
et4000->acl.pattern_y++; et4000->acl.pattern_y++;
@@ -910,6 +1095,7 @@ void et4000w32_decy(et4000w32p_t *et4000)
{ {
et4000->acl.pattern_addr -= et4000->acl.internal.pattern_off + 1; et4000->acl.pattern_addr -= et4000->acl.internal.pattern_off + 1;
et4000->acl.source_addr -= et4000->acl.internal.source_off + 1; et4000->acl.source_addr -= et4000->acl.internal.source_off + 1;
if (et4000->type >= ET4000W32P)
et4000->acl.mix_addr -= et4000->acl.internal.mix_off + 1; et4000->acl.mix_addr -= et4000->acl.internal.mix_off + 1;
et4000->acl.dest_addr -= et4000->acl.internal.dest_off + 1; et4000->acl.dest_addr -= et4000->acl.internal.dest_off + 1;
et4000->acl.pattern_y--; et4000->acl.pattern_y--;
@@ -932,29 +1118,103 @@ void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et400
int c,d; int c,d;
uint8_t pattern, source, dest, out; uint8_t pattern, source, dest, out;
uint8_t rop; uint8_t rop;
int mixdat;
if (!(et4000->acl.status & ACL_XYST)) return;
if (et4000->acl.internal.xy_dir & 0x80) /*Line draw*/
{
while (count--)
{
et4000w32_log("%i,%i : ", et4000->acl.internal.pos_x, et4000->acl.internal.pos_y); et4000w32_log("%i,%i : ", et4000->acl.internal.pos_x, et4000->acl.internal.pos_y);
pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & 0x1fffff]; while (count--) {
source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & 0x1fffff]; et4000w32_log("%i,%i : ", et4000->acl.internal.pos_x, et4000->acl.internal.pos_y);
et4000w32_log("%06X %06X ", (et4000->acl.pattern_addr + et4000->acl.pattern_x) & 0x1fffff, (et4000->acl.source_addr + et4000->acl.source_x) & 0x1fffff);
pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->vram_mask];
source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & et4000->vram_mask];
et4000w32_log("%i %06X %06X %02X %02X ", et4000->acl.pattern_y, (et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->vram_mask, (et4000->acl.source_addr + et4000->acl.source_x) & et4000->vram_mask, pattern, source);
if (cpu_input == 2) if (cpu_input == 2)
{ {
source = sdat & 0xff; source = sdat & 0xff;
sdat >>= 8; sdat >>= 8;
} }
dest = svga->vram[et4000->acl.dest_addr & 0x1fffff]; dest = svga->vram[et4000->acl.dest_addr & et4000->vram_mask];
out = 0;
et4000w32_log("%06X %02X %i %08X %08X ", dest, et4000->acl.dest_addr, mix & 1, mix, et4000->acl.mix_addr);
rop = (mix & 1) ? et4000->acl.internal.rop_fg : et4000->acl.internal.rop_bg;
mix >>= 1;
mix |= 0x80000000;
for (c = 0; c < 8; c++)
{
d = (dest & (1 << c)) ? 1 : 0;
if (source & (1 << c)) d |= 2;
if (pattern & (1 << c)) d |= 4;
if (rop & (1 << d)) out |= (1 << c);
}
et4000w32_log("%06X = %02X\n", et4000->acl.dest_addr & et4000->vram_mask, out);
svga->vram[et4000->acl.dest_addr & et4000->vram_mask] = out;
svga->changedvram[(et4000->acl.dest_addr & et4000->vram_mask) >> 12] = changeframecount;
if (et4000->acl.internal.xy_dir & 1) et4000w32_decx(1, et4000);
else et4000w32_incx(1, et4000);
et4000->acl.internal.pos_x++;
if (et4000->acl.internal.pos_x > et4000->acl.internal.count_x)
{
if (et4000->acl.internal.xy_dir & 2)
{
et4000w32_decy(et4000);
et4000->acl.dest_back = et4000->acl.dest_addr = et4000->acl.dest_back - (et4000->acl.internal.dest_off + 1);
}
else
{
et4000w32_incy(et4000);
et4000->acl.dest_back = et4000->acl.dest_addr = et4000->acl.dest_back + et4000->acl.internal.dest_off + 1;
}
et4000->acl.pattern_x = et4000->acl.pattern_x_back;
et4000->acl.source_x = et4000->acl.source_x_back;
et4000->acl.internal.pos_y++;
et4000->acl.internal.pos_x = 0;
if (et4000->acl.internal.pos_y > et4000->acl.internal.count_y)
{
et4000->acl.status &= ~(ACL_XYST | ACL_SSO);
return;
}
if (cpu_input)
return;
}
}
}
void et4000w32p_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et4000w32p_t *et4000)
{
svga_t *svga = &et4000->svga;
int c,d;
uint8_t pattern, source, dest, out;
uint8_t rop;
int mixdat;
if (!(et4000->acl.status & ACL_XYST))
return;
if (et4000->acl.internal.xy_dir & 0x80) /*Line draw*/
{
while (count--)
{
et4000w32_log("%i,%i : ", et4000->acl.internal.pos_x, et4000->acl.internal.pos_y);
pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->vram_mask];
source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & et4000->vram_mask];
et4000w32_log("%06X %06X ", (et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->vram_mask, (et4000->acl.source_addr + et4000->acl.source_x) & et4000->vram_mask);
if (cpu_input == 2)
{
source = sdat & 0xff;
sdat >>= 8;
}
dest = svga->vram[et4000->acl.dest_addr & et4000->vram_mask];
out = 0; out = 0;
et4000w32_log("%06X ", et4000->acl.dest_addr); et4000w32_log("%06X ", et4000->acl.dest_addr);
if ((et4000->acl.internal.ctrl_routing & 0xa) == 8) if ((et4000->acl.internal.ctrl_routing & 0xa) == 8)
{ {
mixdat = svga->vram[(et4000->acl.mix_addr >> 3) & 0x1fffff] & (1 << (et4000->acl.mix_addr & 7)); mixdat = svga->vram[(et4000->acl.mix_addr >> 3) & et4000->vram_mask] & (1 << (et4000->acl.mix_addr & 7));
et4000w32_log("%06X %02X ", et4000->acl.mix_addr, svga->vram[(et4000->acl.mix_addr >> 3) & 0x1fffff]); et4000w32_log("%06X %02X ", et4000->acl.mix_addr, svga->vram[(et4000->acl.mix_addr >> 3) & et4000->vram_mask]);
} }
else else
{ {
@@ -971,11 +1231,11 @@ void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et400
if (pattern & (1 << c)) d |= 4; if (pattern & (1 << c)) d |= 4;
if (rop & (1 << d)) out |= (1 << c); if (rop & (1 << d)) out |= (1 << c);
} }
et4000w32_log("%06X = %02X\n", et4000->acl.dest_addr & 0x1fffff, out); et4000w32_log("%06X = %02X\n", et4000->acl.dest_addr & et4000->vram_mask, out);
if (!(et4000->acl.internal.ctrl_routing & 0x40)) if (!(et4000->acl.internal.ctrl_routing & 0x40))
{ {
svga->vram[et4000->acl.dest_addr & 0x1fffff] = out; svga->vram[et4000->acl.dest_addr & et4000->vram_mask] = out;
svga->changedvram[(et4000->acl.dest_addr & 0x1fffff) >> 12] = changeframecount; svga->changedvram[(et4000->acl.dest_addr & et4000->vram_mask) >> 12] = changeframecount;
} }
else else
{ {
@@ -1056,22 +1316,22 @@ void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et400
{ {
et4000w32_log("%i,%i : ", et4000->acl.internal.pos_x, et4000->acl.internal.pos_y); et4000w32_log("%i,%i : ", et4000->acl.internal.pos_x, et4000->acl.internal.pos_y);
pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & 0x1fffff]; pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->vram_mask];
source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & 0x1fffff]; source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & et4000->vram_mask];
et4000w32_log("%i %06X %06X %02X %02X ", et4000->acl.pattern_y, (et4000->acl.pattern_addr + et4000->acl.pattern_x) & 0x1fffff, (et4000->acl.source_addr + et4000->acl.source_x) & 0x1fffff, pattern, source); et4000w32_log("%i %06X %06X %02X %02X ", et4000->acl.pattern_y, (et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->vram_mask, (et4000->acl.source_addr + et4000->acl.source_x) & et4000->vram_mask, pattern, source);
if (cpu_input == 2) if (cpu_input == 2)
{ {
source = sdat & 0xff; source = sdat & 0xff;
sdat >>= 8; sdat >>= 8;
} }
dest = svga->vram[et4000->acl.dest_addr & 0x1fffff]; dest = svga->vram[et4000->acl.dest_addr & et4000->vram_mask];
out = 0; out = 0;
et4000w32_log("%06X %02X %i %08X %08X ", dest, et4000->acl.dest_addr, mix & 1, mix, et4000->acl.mix_addr); et4000w32_log("%06X %02X %i %08X %08X ", dest, et4000->acl.dest_addr, mix & 1, mix, et4000->acl.mix_addr);
if ((et4000->acl.internal.ctrl_routing & 0xa) == 8) if ((et4000->acl.internal.ctrl_routing & 0xa) == 8)
{ {
mixdat = svga->vram[(et4000->acl.mix_addr >> 3) & 0x1fffff] & (1 << (et4000->acl.mix_addr & 7)); mixdat = svga->vram[(et4000->acl.mix_addr >> 3) & et4000->vram_mask] & (1 << (et4000->acl.mix_addr & 7));
et4000w32_log("%06X %02X ", et4000->acl.mix_addr, svga->vram[(et4000->acl.mix_addr >> 3) & 0x1fffff]); et4000w32_log("%06X %02X ", et4000->acl.mix_addr, svga->vram[(et4000->acl.mix_addr >> 3) & et4000->vram_mask]);
} }
else else
{ {
@@ -1088,11 +1348,11 @@ void et4000w32_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et400
if (pattern & (1 << c)) d |= 4; if (pattern & (1 << c)) d |= 4;
if (rop & (1 << d)) out |= (1 << c); if (rop & (1 << d)) out |= (1 << c);
} }
et4000w32_log("%06X = %02X\n", et4000->acl.dest_addr & 0x1fffff, out); et4000w32_log("%06X = %02X\n", et4000->acl.dest_addr & et4000->vram_mask, out);
if (!(et4000->acl.internal.ctrl_routing & 0x40)) if (!(et4000->acl.internal.ctrl_routing & 0x40))
{ {
svga->vram[et4000->acl.dest_addr & 0x1fffff] = out; svga->vram[et4000->acl.dest_addr & et4000->vram_mask] = out;
svga->changedvram[(et4000->acl.dest_addr & 0x1fffff) >> 12] = changeframecount; svga->changedvram[(et4000->acl.dest_addr & et4000->vram_mask) >> 12] = changeframecount;
} }
else else
{ {
@@ -1209,7 +1469,7 @@ uint8_t et4000w32p_pci_read(int func, int addr, void *p)
case 0x00: return 0x0c; /*Tseng Labs*/ case 0x00: return 0x0c; /*Tseng Labs*/
case 0x01: return 0x10; case 0x01: return 0x10;
case 0x02: return 0x06; /*ET4000W32p Rev D*/ case 0x02: return (et4000->type == ET4000W32_CARDEX) ? 0x07 : 0x06; /*ET4000W32p Rev C or D*/
case 0x03: return 0x32; case 0x03: return 0x32;
case PCI_REG_COMMAND: case PCI_REG_COMMAND:
@@ -1257,7 +1517,7 @@ void et4000w32p_pci_write(int func, int addr, uint8_t val, void *p)
case 0x13: case 0x13:
et4000->linearbase &= 0x00c00000; et4000->linearbase &= 0x00c00000;
et4000->linearbase |= (et4000->pci_regs[0x13] << 24); et4000->linearbase |= (val << 24);
svga->crtc[0x30] &= 3; svga->crtc[0x30] &= 3;
svga->crtc[0x30] |= ((et4000->linearbase & 0x3f000000) >> 22); svga->crtc[0x30] |= ((et4000->linearbase & 0x3f000000) >> 22);
et4000w32p_recalcmapping(et4000); et4000w32p_recalcmapping(et4000);
@@ -1271,13 +1531,13 @@ void et4000w32p_pci_write(int func, int addr, uint8_t val, void *p)
et4000->pci_regs[0x33] &= 0xf0; et4000->pci_regs[0x33] &= 0xf0;
if (et4000->pci_regs[0x30] & 0x01) if (et4000->pci_regs[0x30] & 0x01)
{ {
uint32_t addr = (et4000->pci_regs[0x33] << 24); uint32_t bios_addr = (et4000->pci_regs[0x33] << 24);
if (!addr) if (!bios_addr)
{ {
addr = 0xC0000; bios_addr = 0xC0000;
} }
et4000w32_log("ET4000 bios_rom enabled at %08x\n", addr); et4000w32_log("ET4000 bios_rom enabled at %08x\n", bios_addr);
mem_mapping_set_addr(&et4000->bios_rom.mapping, addr, 0x8000); mem_mapping_set_addr(&et4000->bios_rom.mapping, bios_addr, 0x8000);
} }
else else
{ {
@@ -1294,14 +1554,20 @@ void *et4000w32p_init(const device_t *info)
et4000w32p_t *et4000 = malloc(sizeof(et4000w32p_t)); et4000w32p_t *et4000 = malloc(sizeof(et4000w32p_t));
memset(et4000, 0, sizeof(et4000w32p_t)); memset(et4000, 0, sizeof(et4000w32p_t));
if (info->local != ET4000W32) {
vram_size = device_get_config_int("memory"); vram_size = device_get_config_int("memory");
et4000->interleaved = (vram_size == 2) ? 1 : 0; et4000->interleaved = (vram_size == 2) ? 1 : 0;
} else {
vram_size = 1;
et4000->interleaved = 0;
}
if (info->flags & DEVICE_PCI) if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000w32_pci); video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000w32_pci);
else else if (info->flags & DEVICE_VLB)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000w32_vlb); video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000w32_vlb);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000w32_isa);
svga_init(info, &et4000->svga, et4000, vram_size << 20, svga_init(info, &et4000->svga, et4000, vram_size << 20,
et4000w32p_recalctimings, et4000w32p_recalctimings,
@@ -1310,32 +1576,59 @@ void *et4000w32p_init(const device_t *info)
NULL); NULL);
et4000->svga.hwcursor.ysize = 64; et4000->svga.hwcursor.ysize = 64;
et4000->svga.ramdac = device_add(&stg_ramdac_device);
et4000->vram_mask = (vram_size << 20) - 1; et4000->vram_mask = (vram_size << 20) - 1;
et4000->type = info->local; et4000->type = info->local;
switch(et4000->type) { switch(et4000->type) {
case ET4000W32:
rom_init(&et4000->bios_rom, BIOS_ROM_PATH_W32, 0xc0000, 0x8000, 0x7fff, 0,
MEM_MAPPING_EXTERNAL);
et4000->svga.ramdac = device_add(&stg_ramdac_device);
et4000->svga.clock_gen = device_add(&gendac_ramdac_device);
et4000->svga.getclock = sdac_getclock;
break;
case ET4000W32I:
rom_init(&et4000->bios_rom, BIOS_ROM_PATH_W32I, 0xc0000, 0x8000, 0x7fff, 0,
MEM_MAPPING_EXTERNAL);
et4000->svga.ramdac = device_add(&stg_ramdac_device);
et4000->svga.clock_gen = device_add(&gendac_ramdac_device);
et4000->svga.getclock = sdac_getclock;
break;
case ET4000W32P:
rom_init(&et4000->bios_rom, BIOS_ROM_PATH_W32P, 0xc0000, 0x8000, 0x7fff, 0,
MEM_MAPPING_EXTERNAL);
et4000->svga.ramdac = device_add(&stg_ramdac_device);
et4000->svga.clock_gen = device_add(&sdac_ramdac_device);
et4000->svga.getclock = sdac_getclock;
break;
case ET4000W32_CARDEX: case ET4000W32_CARDEX:
rom_init(&et4000->bios_rom, BIOS_ROM_PATH_CARDEX, 0xc0000, 0x8000, 0x7fff, 0, rom_init(&et4000->bios_rom, BIOS_ROM_PATH_CARDEX, 0xc0000, 0x8000, 0x7fff, 0,
MEM_MAPPING_EXTERNAL); MEM_MAPPING_EXTERNAL);
et4000->svga.clock_gen = et4000->svga.ramdac; et4000->svga.ramdac = device_add(&stg_ramdac_device);
et4000->svga.getclock = stg_getclock; et4000->svga.clock_gen = device_add(&sdac_ramdac_device);
et4000->svga.adv_flags |= FLAG_NOSKEW; et4000->svga.getclock = sdac_getclock;
break; break;
case ET4000W32_DIAMOND: case ET4000W32_DIAMOND:
rom_init(&et4000->bios_rom, BIOS_ROM_PATH_DIAMOND, 0xc0000, 0x8000, 0x7fff, 0, rom_init(&et4000->bios_rom, BIOS_ROM_PATH_DIAMOND, 0xc0000, 0x8000, 0x7fff, 0,
MEM_MAPPING_EXTERNAL); MEM_MAPPING_EXTERNAL);
et4000->svga.ramdac = device_add(&stg_ramdac_device);
et4000->svga.clock_gen = device_add(&icd2061_device); et4000->svga.clock_gen = device_add(&icd2061_device);
et4000->svga.getclock = icd2061_getclock; et4000->svga.getclock = icd2061_getclock;
break; break;
} }
et4000->pci = !!(info->flags & DEVICE_PCI); et4000->pci = !!(info->flags & DEVICE_PCI);
if (info->flags & DEVICE_PCI) et4000->isa = !!(info->flags & (DEVICE_ISA | DEVICE_AT));
if (et4000->pci)
mem_mapping_disable(&et4000->bios_rom.mapping); mem_mapping_disable(&et4000->bios_rom.mapping);
mem_mapping_add(&et4000->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL, MEM_MAPPING_EXTERNAL, &et4000->svga); mem_mapping_add(&et4000->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL, MEM_MAPPING_EXTERNAL, &et4000->svga);
@@ -1343,7 +1636,7 @@ void *et4000w32p_init(const device_t *info)
et4000w32p_io_set(et4000); et4000w32p_io_set(et4000);
if (info->flags & DEVICE_PCI) if (et4000->pci)
pci_add_card(PCI_ADD_VIDEO, et4000w32p_pci_read, et4000w32p_pci_write, et4000); pci_add_card(PCI_ADD_VIDEO, et4000w32p_pci_read, et4000w32p_pci_write, et4000);
/* Hardwired bits: 00000000 1xx0x0xx */ /* Hardwired bits: 00000000 1xx0x0xx */
@@ -1361,13 +1654,30 @@ void *et4000w32p_init(const device_t *info)
et4000->pci_regs[0x32] = 0x00; et4000->pci_regs[0x32] = 0x00;
et4000->pci_regs[0x33] = 0xf0; et4000->pci_regs[0x33] = 0xf0;
if (et4000->type >= ET4000W32P) {
et4000->wake_fifo_thread = thread_create_event(); et4000->wake_fifo_thread = thread_create_event();
et4000->fifo_not_full_event = thread_create_event(); et4000->fifo_not_full_event = thread_create_event();
et4000->fifo_thread = thread_create(fifo_thread, et4000); et4000->fifo_thread = thread_create(fifo_thread, et4000);
}
return et4000; return et4000;
} }
int et4000w32_available(void)
{
return rom_present(BIOS_ROM_PATH_W32);
}
int et4000w32i_available(void)
{
return rom_present(BIOS_ROM_PATH_W32I);
}
int et4000w32p_noncardex_available(void)
{
return rom_present(BIOS_ROM_PATH_W32P);
}
int et4000w32p_available(void) int et4000w32p_available(void)
{ {
return rom_present(BIOS_ROM_PATH_DIAMOND); return rom_present(BIOS_ROM_PATH_DIAMOND);
@@ -1426,6 +1736,50 @@ static const device_config_t et4000w32p_config[] =
} }
}; };
const device_t et4000w32_device =
{
"Tseng Labs ET4000/w32",
DEVICE_ISA | DEVICE_AT, ET4000W32,
et4000w32p_init, et4000w32p_close, NULL,
{ et4000w32_available },
et4000w32p_speed_changed,
et4000w32p_force_redraw,
NULL
};
const device_t et4000w32i_device =
{
"Tseng Labs ET4000/w32i",
DEVICE_ISA | DEVICE_AT, ET4000W32I,
et4000w32p_init, et4000w32p_close, NULL,
{ et4000w32i_available },
et4000w32p_speed_changed,
et4000w32p_force_redraw,
et4000w32p_config
};
const device_t et4000w32p_noncardex_vlb_device =
{
"Tseng Labs ET4000/w32p VLB",
DEVICE_VLB, ET4000W32P,
et4000w32p_init, et4000w32p_close, NULL,
{ et4000w32p_noncardex_available },
et4000w32p_speed_changed,
et4000w32p_force_redraw,
et4000w32p_config
};
const device_t et4000w32p_noncardex_pci_device =
{
"Tseng Labs ET4000/w32p PCI",
DEVICE_PCI, ET4000W32P,
et4000w32p_init, et4000w32p_close, NULL,
{ et4000w32p_noncardex_available },
et4000w32p_speed_changed,
et4000w32p_force_redraw,
et4000w32p_config
};
const device_t et4000w32p_cardex_vlb_device = const device_t et4000w32p_cardex_vlb_device =
{ {
"Tseng Labs ET4000/w32p VLB (Cardex)", "Tseng Labs ET4000/w32p VLB (Cardex)",

8
src/video/vid_s3.c
View File

@@ -2517,10 +2517,7 @@ static void s3_recalctimings(svga_t *svga)
switch (svga->crtc[0x67] >> 4) { switch (svga->crtc[0x67] >> 4) {
case 3: case 5: case 7: case 3: case 5: case 7:
if (s3->chip != S3_VISION868)
svga->clock /= 2; svga->clock /= 2;
else
svga->clock *= 2;
break; break;
} }
@@ -2530,9 +2527,14 @@ static void s3_recalctimings(svga_t *svga)
case 8: case 8:
svga->render = svga_render_8bpp_highres; svga->render = svga_render_8bpp_highres;
if (s3->chip != S3_VISION868) { if (s3->chip != S3_VISION868) {
if (s3->chip == S3_86C928) {
if (s3->width == 2048 || s3->width == 1280 || s3->width == 1600)
svga->hdisp *= 2;
} else {
if (s3->width == 1280 || s3->width == 1600) if (s3->width == 1280 || s3->width == 1600)
svga->hdisp *= 2; svga->hdisp *= 2;
} }
}
break; break;
case 15: case 15:
svga->render = svga_render_15bpp_highres; svga->render = svga_render_15bpp_highres;

4
src/video/vid_table.c
View File

@@ -110,6 +110,8 @@ video_cards[] = {
{ "tgkorvga", &et4000k_isa_device }, { "tgkorvga", &et4000k_isa_device },
{ "et2000", &et2000_device }, { "et2000", &et2000_device },
{ "et4000ax", &et4000_isa_device }, { "et4000ax", &et4000_isa_device },
{ "et4000w32", &et4000w32_device },
{ "et4000w32i", &et4000w32i_device },
{ "vga", &vga_device }, { "vga", &vga_device },
{ "v7_vga_1024i", &v7_vga_1024i_device }, { "v7_vga_1024i", &v7_vga_1024i_device },
{ "wy700", &wy700_device }, { "wy700", &wy700_device },
@@ -118,6 +120,7 @@ video_cards[] = {
{ "mach64gx_pci", &mach64gx_pci_device }, { "mach64gx_pci", &mach64gx_pci_device },
{ "mach64vt2", &mach64vt2_device }, { "mach64vt2", &mach64vt2_device },
{ "et4000w32p_pci", &et4000w32p_cardex_pci_device }, { "et4000w32p_pci", &et4000w32p_cardex_pci_device },
{ "et4000w32p_nc_pci", &et4000w32p_noncardex_pci_device },
{ "cl_gd5430_pci", &gd5430_pci_device, }, { "cl_gd5430_pci", &gd5430_pci_device, },
{ "cl_gd5434_pci", &gd5434_pci_device }, { "cl_gd5434_pci", &gd5434_pci_device },
{ "cl_gd5436_pci", &gd5436_pci_device }, { "cl_gd5436_pci", &gd5436_pci_device },
@@ -158,6 +161,7 @@ video_cards[] = {
{ "voodoo3_3k_pci", &voodoo_3_3000_device }, { "voodoo3_3k_pci", &voodoo_3_3000_device },
{ "mach64gx_vlb", &mach64gx_vlb_device }, { "mach64gx_vlb", &mach64gx_vlb_device },
{ "et4000w32p_vlb", &et4000w32p_cardex_vlb_device }, { "et4000w32p_vlb", &et4000w32p_cardex_vlb_device },
{ "et4000w32p_nc_vlb", &et4000w32p_noncardex_vlb_device },
{ "cl_gd5424_vlb", &gd5424_vlb_device }, { "cl_gd5424_vlb", &gd5424_vlb_device },
{ "cl_gd5428_vlb", &gd5428_vlb_device }, { "cl_gd5428_vlb", &gd5428_vlb_device },
{ "cl_gd5429_vlb", &gd5429_vlb_device }, { "cl_gd5429_vlb", &gd5429_vlb_device },