From c5ac252eb165b8ebf3da30944505af78b5679cbf Mon Sep 17 00:00:00 2001 From: OBattler Date: Wed, 15 Jan 2020 02:28:24 +0100 Subject: [PATCH] Fixed two integer handling issues in the AMD PCnet code. --- src/network/net_pcnet.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/src/network/net_pcnet.c b/src/network/net_pcnet.c index 3b53da687..49de94317 100644 --- a/src/network/net_pcnet.c +++ b/src/network/net_pcnet.c @@ -907,6 +907,24 @@ pcnetInit(nic_t *dev) dev->GCTDRA = PHYSADDR(dev, initblk.tdra); \ } while (0) +#define PCNET_INIT16() do { \ + DMAPageRead(PHYSADDR(dev, CSR_IADR(dev)), \ + (uint8_t *)&initblk, sizeof(initblk)); \ + dev->aCSR[15] = le32_to_cpu(initblk.mode); \ + CSR_RCVRL(dev) = (1 << initblk.rlen); \ + CSR_XMTRL(dev) = (1 << initblk.tlen); \ + dev->aCSR[ 6] = (initblk.tlen << 12) | (initblk.rlen << 8); \ + dev->aCSR[ 8] = le32_to_cpu(initblk.ladrf1); \ + dev->aCSR[ 9] = le32_to_cpu(initblk.ladrf2); \ + dev->aCSR[10] = le32_to_cpu(initblk.ladrf3); \ + dev->aCSR[11] = le32_to_cpu(initblk.ladrf4); \ + dev->aCSR[12] = le32_to_cpu(initblk.padr1); \ + dev->aCSR[13] = le32_to_cpu(initblk.padr2); \ + dev->aCSR[14] = le32_to_cpu(initblk.padr3); \ + dev->GCRDRA = PHYSADDR(dev, initblk.rdra); \ + dev->GCTDRA = PHYSADDR(dev, initblk.tdra); \ +} while (0) + if (BCR_SSIZE32(dev)) { struct INITBLK32 initblk; dev->GCUpperPhys = 0; @@ -916,7 +934,7 @@ pcnetInit(nic_t *dev) } else { struct INITBLK16 initblk; dev->GCUpperPhys = (0xff00 & (uint32_t)dev->aCSR[2]) << 16; - PCNET_INIT(); + PCNET_INIT16(); pcnetlog(3, "%s: initblk.rlen=%#04x, initblk.tlen=%#04x\n", dev->name, initblk.rlen, initblk.tlen); }