diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c index 996cfc536..b21b6cb1c 100644 --- a/src/chipset/intel_4x0.c +++ b/src/chipset/intel_4x0.c @@ -42,9 +42,7 @@ enum INTEL_430HX, INTEL_430VX, INTEL_430TX, -#if defined(DEV_BRANCH) && defined(USE_I686) INTEL_440FX, -#endif INTEL_440BX, INTEL_440ZX }; @@ -259,9 +257,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) regs[0x04] = (regs[0x04] & ~0x42) | (val & 0x42); break; case INTEL_430FX: case INTEL_430FX_PB640: case INTEL_430HX: case INTEL_430VX: case INTEL_430TX: -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: -#endif regs[0x04] = (regs[0x04] & ~0x02) | (val & 0x02); break; } @@ -269,9 +265,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case 0x05: switch (dev->type) { case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX: -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: -#endif case INTEL_440BX: case INTEL_440ZX: regs[0x05] = (regs[0x05] & ~0x01) | (val & 0x01); break; @@ -286,11 +280,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_430FX: case INTEL_430FX_PB640: case INTEL_430VX: case INTEL_430TX: regs[0x07] &= ~(val & 0x30); break; -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: regs[0x07] &= ~(val & 0xf9); break; -#endif case INTEL_440BX: case INTEL_440ZX: regs[0x07] &= ~(val & 0xf0); break; @@ -370,11 +362,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_430VX: case INTEL_430TX: regs[0x50] = (val & 0x08); break; -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: regs[0x50] = (val & 0xf4); break; -#endif case INTEL_440BX: regs[0x50] = (regs[0x50] & 0x14) | (val & 0xeb); break; @@ -389,11 +379,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: regs[0x51] = (val & 0xc0); break; -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: regs[0x51] = (val & 0xc3); break; -#endif case INTEL_440BX: case INTEL_440ZX: regs[0x51] = (regs[0x50] & 0x70) | (val & 0x8f); break; @@ -409,9 +397,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) regs[0x52] = (val & 0xfb); break; case INTEL_430NX: case INTEL_430HX: -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: -#endif regs[0x52] = val; break; case INTEL_440BX: case INTEL_440ZX: @@ -449,11 +435,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_430TX: regs[0x54] = val & 0xfa; break; -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: regs[0x54] = val & 0x82; break; -#endif } break; case 0x55: @@ -461,11 +445,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_430VX: case INTEL_430TX: regs[0x55] = val & 0x01; break; -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: regs[0x55] = val; break; -#endif } break; case 0x56: @@ -479,11 +461,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_430TX: regs[0x56] = val & 0x76; break; -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: regs[0x56] = val; break; -#endif } break; case 0x57: @@ -502,11 +482,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_430TX: regs[0x57] = val & 0xdf; break; -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: regs[0x57] = val & 0x77; break; -#endif case INTEL_440BX: regs[0x57] = val & 0x3f; break; @@ -526,9 +504,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) regs[0x58] = val & 0x03; break; case INTEL_430FX: case INTEL_430FX_PB640: -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: -#endif regs[0x58] = val & 0x7f; break; case INTEL_430HX: case INTEL_430VX: @@ -600,9 +576,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX: -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: -#endif case INTEL_440BX: case INTEL_440ZX: default: regs[addr] = val; @@ -621,9 +595,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX: -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: -#endif case INTEL_440BX: case INTEL_440ZX: regs[addr] = val; break; @@ -638,9 +610,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case 0x66: switch (dev->type) { case INTEL_430NX: case INTEL_430HX: -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: -#endif case INTEL_440BX: case INTEL_440ZX: regs[addr] = val; break; @@ -649,9 +619,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case 0x67: switch (dev->type) { case INTEL_430NX: case INTEL_430HX: -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: -#endif case INTEL_440BX: case INTEL_440ZX: regs[addr] = val; break; @@ -672,11 +640,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_430FX: case INTEL_430FX_PB640: regs[0x68] = val & 0x1f; break; -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: regs[0x68] = val & 0xc0; break; -#endif case INTEL_440BX: regs[0x68] = (regs[0x68] & 0x38) | (val & 0xc7); break; @@ -705,14 +671,12 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_440BX: regs[addr] = val; break; -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440ZX: if (addr == 0x6a) regs[addr] = val & 0xfc; else regs[addr] = val & 0x33; break; -#endif } break; case 0x6c: case 0x6d: case 0x6e: @@ -740,11 +704,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_430VX: case INTEL_430TX: regs[addr] = val & 0xfc; break; -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: regs[addr] = val & 0xf8; break; -#endif } break; case 0x71: @@ -756,11 +718,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_430TX: regs[addr] = val; break; -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: regs[addr] = val & 0x1f; break; -#endif } break; case 0x72: /* SMRAM */ @@ -890,11 +850,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case INTEL_430HX: regs[0x80] = val & 0x87; break; -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: regs[0x80] = val & 0x1b; break; -#endif case INTEL_440BX: case INTEL_440ZX: regs[0x7c] = val; break; @@ -903,9 +861,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) case 0x91: switch (dev->type) { case INTEL_430HX: case INTEL_440BX: -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: -#endif /* Not applicable on 82443ZX. */ regs[0x91] &= ~(val & 0x11); break; @@ -918,7 +874,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) break; } break; -#if defined(DEV_BRANCH) && defined(USE_I686) case 0x93: switch (dev->type) { case INTEL_440FX: @@ -927,7 +882,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) break; } break; -#endif case 0xa8: case 0xa9: switch (dev->type) { case INTEL_440BX: case INTEL_440ZX: @@ -1114,12 +1068,10 @@ i4x0_read(int func, int addr, void *priv) ret = 0xff; else { ret = regs[addr]; -#if defined(DEV_BRANCH) && defined(USE_I686) /* Special behavior for 440FX register 0x93 which is basically TRC in PCI space with the addition of bits 3 and 0. */ if ((func == 0) && (addr == 0x93) && (dev->type == INTEL_440FX)) ret = (ret & 0xf9) | (trc_read(0x0093, NULL) & 0x06); -#endif } return ret; @@ -1304,7 +1256,6 @@ static void regs[0x70] = 0x20; regs[0x72] = 0x02; break; -#if defined(DEV_BRANCH) && defined(USE_I686) case INTEL_440FX: regs[0x02] = 0x37; regs[0x03] = 0x12; /* 82441FX */ regs[0x08] = 0x02; @@ -1319,7 +1270,6 @@ static void regs[0x71] = 0x10; regs[0x72] = 0x02; break; -#endif case INTEL_440BX: case INTEL_440ZX: regs[0x7a] = (info->local >> 8) & 0xff; dev->max_func = (regs[0x7a] & 0x02) ? 0 : 1; @@ -1351,12 +1301,10 @@ static void regs[0x04] = 0x06; regs[0x07] = 0x02; regs[0x0b] = 0x06; -#if defined(DEV_BRANCH) && defined(USE_I686) if (dev->type >= INTEL_440FX) { cpu_cache_ext_enabled = 1; cpu_update_waitstates(); } -#endif i4x0_write(regs[0x59], 0x59, 0x00, dev); i4x0_write(regs[0x5a], 0x5a, 0x00, dev); @@ -1526,7 +1474,6 @@ const device_t i430tx_device = }; -#if defined(DEV_BRANCH) && defined(USE_I686) const device_t i440fx_device = { "Intel 82441FX", @@ -1541,7 +1488,7 @@ const device_t i440fx_device = NULL }; -#endif + const device_t i440bx_device = { "Intel 82443BX", diff --git a/src/cpu_common/386_ops.h b/src/cpu_common/386_ops.h index f7c6e64d2..f6467dea1 100644 --- a/src/cpu_common/386_ops.h +++ b/src/cpu_common/386_ops.h @@ -190,9 +190,7 @@ extern void x386_dynarec_log(const char *fmt, ...); #include "x86_ops_jump.h" #include "x86_ops_misc.h" #include "x87_ops.h" -#if defined(DEV_BRANCH) && defined(USE_I686) -# include "x86_ops_i686.h" -#endif +#include "x86_ops_i686.h" #include "x86_ops_mmx.h" #include "x86_ops_mmx_arith.h" #include "x86_ops_mmx_cmp.h" @@ -1174,8 +1172,6 @@ const OpFn OP_TABLE(c6x86mx_0f)[1024] = }; #endif -#ifdef DEV_BRANCH -#ifdef USE_I686 const OpFn OP_TABLE(pentiumpro_0f)[1024] = { /*16-bit data, 16-bit addr*/ @@ -1448,8 +1444,6 @@ const OpFn OP_TABLE(pentium2d_0f)[1024] = /*e0*/ ILLEGAL, opPSRAW_a32, opPSRAD_a32, ILLEGAL, ILLEGAL, opPMULHW_a32, ILLEGAL, ILLEGAL, opPSUBSB_a32, opPSUBSW_a32, NULL, opPOR_a32, opPADDSB_a32, opPADDSW_a32, NULL, opPXOR_a32, /*f0*/ ILLEGAL, opPSLLW_a32, opPSLLD_a32, opPSLLQ_a32, ILLEGAL, opPMADDWD_a32, ILLEGAL, ILLEGAL, opPSUBB_a32, opPSUBW_a32, opPSUBD_a32, ILLEGAL, opPADDB_a32, opPADDW_a32, opPADDD_a32, ILLEGAL, }; -#endif -#endif const OpFn OP_TABLE(286)[1024] = { diff --git a/src/cpu_common/cpu.c b/src/cpu_common/cpu.c index e16e5f3f3..39b6e6158 100644 --- a/src/cpu_common/cpu.c +++ b/src/cpu_common/cpu.c @@ -186,7 +186,6 @@ uint64_t mtrr_fix16k_a000_msr = 0; uint64_t mtrr_fix4k_msr[8] = {0, 0, 0, 0, 0, 0, 0, 0}; uint64_t mtrr_deftype_msr = 0; -#if defined(DEV_BRANCH) && defined(USE_I686) uint16_t cs_msr = 0; uint32_t esp_msr = 0; uint32_t eip_msr = 0; @@ -203,7 +202,6 @@ uint64_t ecx186_msr = 0; uint64_t ecx187_msr = 0; uint64_t ecx1e0_msr = 0; uint64_t ecx570_msr = 0; -#endif uint64_t ecx83_msr = 0; /* AMD K5 and K6 MSR's. */ uint64_t star = 0; /* AMD K6-2+. */ @@ -317,12 +315,8 @@ cpu_set(void) is_k6 = (cpu_s->cpu_type == CPU_K6) || (cpu_s->cpu_type == CPU_K6_2) || (cpu_s->cpu_type == CPU_K6_2C) || (cpu_s->cpu_type == CPU_K6_3) || (cpu_s->cpu_type == CPU_K6_2P) || (cpu_s->cpu_type == CPU_K6_3P); -#if defined(DEV_BRANCH) && defined(USE_I686) is_p6 = (cpu_s->cpu_type == CPU_PENTIUMPRO) || (cpu_s->cpu_type == CPU_PENTIUM2) || (cpu_s->cpu_type == CPU_PENTIUM2D); -#else - is_p6 = 0; -#endif hasfpu = (cpu_s->cpu_type >= CPU_i486DX) || (cpu_s->cpu_type == CPU_RAPIDCAD); hascache = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL); #if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86) @@ -1383,7 +1377,6 @@ cpu_set(void) codegen_timing_set(&codegen_timing_k6); break; -#if defined(DEV_BRANCH) && defined(USE_I686) case CPU_PENTIUMPRO: #ifdef USE_DYNAREC x86_setopcodes(ops_386, ops_pentiumpro_0f, dynarec_ops_386, dynarec_ops_pentiumpro_0f); @@ -1548,7 +1541,7 @@ cpu_set(void) codegen_timing_set(&codegen_timing_p6); #endif break; -#endif + case CPU_CYRIX3S: #ifdef USE_DYNAREC x86_setopcodes(ops_386, ops_winchip2_0f, dynarec_ops_386, dynarec_ops_winchip2_0f); @@ -2196,8 +2189,6 @@ cpu_CPUID(void) break; #endif -#ifdef DEV_BRANCH -#ifdef USE_I686 case CPU_PENTIUMPRO: if (!EAX) { @@ -2266,8 +2257,7 @@ cpu_CPUID(void) else EAX = EBX = ECX = EDX = 0; break; -#endif -#endif + case CPU_CYRIX3S: switch (EAX) { @@ -2712,8 +2702,6 @@ void cpu_RDMSR() break; #endif -#ifdef DEV_BRANCH -#ifdef USE_I686 case CPU_PENTIUMPRO: case CPU_PENTIUM2: case CPU_PENTIUM2D: @@ -2839,8 +2827,6 @@ i686_invalid_rdmsr: break; } break; -#endif -#endif } } @@ -3154,8 +3140,6 @@ void cpu_WRMSR() break; #endif -#ifdef DEV_BRANCH -#ifdef USE_I686 case CPU_PENTIUMPRO: case CPU_PENTIUM2: case CPU_PENTIUM2D: @@ -3249,8 +3233,6 @@ i686_invalid_wrmsr: break; } break; -#endif -#endif } } diff --git a/src/cpu_common/cpu.h b/src/cpu_common/cpu.h index c471b1e75..3f54e9680 100644 --- a/src/cpu_common/cpu.h +++ b/src/cpu_common/cpu.h @@ -73,11 +73,9 @@ enum { CPU_K6_2P, CPU_K6_3P, CPU_CYRIX3S, -#if defined(DEV_BRANCH) && defined(USE_I686) CPU_PENTIUMPRO, /* 686 class CPUs */ CPU_PENTIUM2, CPU_PENTIUM2D, -#endif CPU_MAX /* Only really needed to close the enum in a way independent of the #ifdef's. */ }; @@ -145,12 +143,10 @@ extern CPU cpus_6x86[]; extern CPU cpus_6x86SS7[]; #endif #endif -extern CPU cpus_Cyrix3[]; -#if defined(DEV_BRANCH) && defined(USE_I686) +extern CPU cpus_Cyrix3[]; extern CPU cpus_PentiumPro[]; extern CPU cpus_PentiumII[]; extern CPU cpus_Celeron[]; -#endif #define C_FLAG 0x0001 diff --git a/src/cpu_common/cpu_table.c b/src/cpu_common/cpu_table.c index 326556317..230ac5191 100644 --- a/src/cpu_common/cpu_table.c +++ b/src/cpu_common/cpu_table.c @@ -660,8 +660,6 @@ CPU cpus_K56_SS7[] = { {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }; -#ifdef DEV_BRANCH -#ifdef USE_I686 CPU cpus_PentiumPro[] = { /*Intel Pentium Pro*/ {"Pentium Pro 50", CPU_PENTIUMPRO, 50000000, 1.0, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, @@ -735,8 +733,7 @@ CPU cpus_Celeron[] = { {"Celeron Mendocino 533", CPU_PENTIUM2D, 533333333, 5.5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48,48,17,17, 64}, {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }; -#endif -#endif + CPU cpus_Cyrix3[] = { /*VIA Cyrix III (Samuel)*/ {"Cyrix III 66", CPU_CYRIX3S, 66666666, 1.0, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 8}, /*66 MHz version*/ diff --git a/src/cpu_common/x86_ops.h b/src/cpu_common/x86_ops.h index d41cca96f..f66e2392d 100644 --- a/src/cpu_common/x86_ops.h +++ b/src/cpu_common/x86_ops.h @@ -93,11 +93,9 @@ extern const OpFn dynarec_ops_c6x86mx_0f[1024]; extern const OpFn dynarec_ops_k6_0f[1024]; extern const OpFn dynarec_ops_k62_0f[1024]; -#if defined(DEV_BRANCH) && defined(USE_I686) extern const OpFn dynarec_ops_pentiumpro_0f[1024]; extern const OpFn dynarec_ops_pentium2_0f[1024]; extern const OpFn dynarec_ops_pentium2d_0f[1024]; -#endif extern const OpFn dynarec_ops_fpu_287_d9_a16[256]; extern const OpFn dynarec_ops_fpu_287_d9_a32[256]; @@ -190,11 +188,9 @@ extern const OpFn ops_c6x86mx_0f[1024]; extern const OpFn ops_k6_0f[1024]; extern const OpFn ops_k62_0f[1024]; -#if defined(DEV_BRANCH) && defined(USE_I686) extern const OpFn ops_pentiumpro_0f[1024]; extern const OpFn ops_pentium2_0f[1024]; extern const OpFn ops_pentium2d_0f[1024]; -#endif extern const OpFn ops_fpu_287_d9_a16[256]; extern const OpFn ops_fpu_287_d9_a32[256]; diff --git a/src/cpu_common/x86_ops_mov.h b/src/cpu_common/x86_ops_mov.h index dd49465bc..2c96317b7 100644 --- a/src/cpu_common/x86_ops_mov.h +++ b/src/cpu_common/x86_ops_mov.h @@ -688,7 +688,6 @@ static int opMOV_r_l_a32(uint32_t fetchdat) return 0; } -#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && (defined(USE_CYRIX_6X86) || defined(USE_I686))) #define opCMOV(condition) \ static int opCMOV ## condition ## _w_a16(uint32_t fetchdat) \ { \ @@ -783,4 +782,3 @@ opCMOV(L) opCMOV(NL) opCMOV(LE) opCMOV(NLE) -#endif diff --git a/src/cpu_common/x87_ops.h b/src/cpu_common/x87_ops.h index ac304c190..e1d04c96f 100644 --- a/src/cpu_common/x87_ops.h +++ b/src/cpu_common/x87_ops.h @@ -1064,7 +1064,6 @@ const OpFn OP_TABLE(fpu_da_a32)[256] = ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, }; -#if defined(DEV_BRANCH) && (defined(USE_CYRIX_6X86) || defined(USE_I686)) const OpFn OP_TABLE(fpu_686_da_a16)[256] = { opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, @@ -1141,7 +1140,6 @@ const OpFn OP_TABLE(fpu_686_da_a32)[256] = ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, }; -#endif const OpFn OP_TABLE(fpu_287_db_a16)[256] = { @@ -1297,7 +1295,6 @@ const OpFn OP_TABLE(fpu_db_a32)[256] = ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, }; -#if defined(DEV_BRANCH) && (defined(USE_CYRIX_6X86) || defined(USE_I686)) const OpFn OP_TABLE(fpu_686_db_a16)[256] = { opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, @@ -1374,7 +1371,6 @@ const OpFn OP_TABLE(fpu_686_db_a32)[256] = opFCOMI, opFCOMI, opFCOMI, opFCOMI, opFCOMI, opFCOMI, opFCOMI, opFCOMI, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, }; -#endif const OpFn OP_TABLE(fpu_287_dc_a16)[32] = { @@ -1870,7 +1866,6 @@ const OpFn OP_TABLE(fpu_df_a32)[256] = ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, }; -#if defined(DEV_BRANCH) && (defined(USE_CYRIX_6X86) || defined(USE_I686)) const OpFn OP_TABLE(fpu_686_df_a16)[256] = { opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, @@ -1947,7 +1942,6 @@ const OpFn OP_TABLE(fpu_686_df_a32)[256] = opFCOMIP, opFCOMIP, opFCOMIP, opFCOMIP, opFCOMIP, opFCOMIP, opFCOMIP, opFCOMIP, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, }; -#endif const OpFn OP_TABLE(nofpu_a16)[256] = { diff --git a/src/cpu_common/x87_ops_arith.h b/src/cpu_common/x87_ops_arith.h index 13427fbc6..1e7722a17 100644 --- a/src/cpu_common/x87_ops_arith.h +++ b/src/cpu_common/x87_ops_arith.h @@ -203,7 +203,6 @@ static int opFUCOMPP(uint32_t fetchdat) return 0; } -#if defined(DEV_BRANCH) && (defined(USE_CYRIX_6X86) || defined(USE_I686)) static int opFCOMI(uint32_t fetchdat) { FP_ENTER(); @@ -228,7 +227,6 @@ static int opFCOMIP(uint32_t fetchdat) return 0; } #endif -#endif static int opFDIV(uint32_t fetchdat) { @@ -397,7 +395,6 @@ static int opFUCOMP(uint32_t fetchdat) return 0; } -#if defined(DEV_BRANCH) && (defined(USE_CYRIX_6X86) || defined(USE_I686)) static int opFUCOMI(uint32_t fetchdat) { FP_ENTER(); @@ -422,4 +419,3 @@ static int opFUCOMIP(uint32_t fetchdat) return 0; } #endif -#endif diff --git a/src/cpu_common/x87_ops_misc.h b/src/cpu_common/x87_ops_misc.h index 2145a245e..a4e437744 100644 --- a/src/cpu_common/x87_ops_misc.h +++ b/src/cpu_common/x87_ops_misc.h @@ -845,7 +845,7 @@ static int opFSTCW_a32(uint32_t fetchdat) } #endif -#if !defined(FPU_8087) && defined(DEV_BRANCH) && (defined(USE_CYRIX_6X86) || defined(USE_I686)) +#ifndef FPU_8087 #define opFCMOV(condition) \ static int opFCMOV ## condition(uint32_t fetchdat) \ { \ diff --git a/src/include/86box/chipset.h b/src/include/86box/chipset.h index 87a4b44e4..520d7f0ba 100644 --- a/src/include/86box/chipset.h +++ b/src/include/86box/chipset.h @@ -41,9 +41,7 @@ extern const device_t i430fx_pb640_device; extern const device_t i430hx_device; extern const device_t i430vx_device; extern const device_t i430tx_device; -#if defined(DEV_BRANCH) && defined(USE_I686) extern const device_t i440fx_device; -#endif extern const device_t i440bx_device; extern const device_t i440zx_device; diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h index 027adc4dc..24ebcb947 100644 --- a/src/include/86box/machine.h +++ b/src/include/86box/machine.h @@ -309,10 +309,8 @@ extern const device_t *at_pb640_get_device(void); #endif /* m_at_socket8.c */ -#if defined(DEV_BRANCH) && defined(USE_I686) extern int machine_at_i440fx_init(const machine_t *); extern int machine_at_s1668_init(const machine_t *); -#endif /* m_at_slot1.c */ extern int machine_at_6bxc_init(const machine_t *); @@ -325,7 +323,7 @@ extern int machine_at_atc7020bxii_init(const machine_t *); extern int machine_at_63a_init(const machine_t *); extern int machine_at_apas3_init(const machine_t *); -#if defined(DEV_BRANCH) && defined(USE_I686) && defined(USE_596B) +#if defined(DEV_BRANCH) && defined(USE_596B) extern int machine_at_bx98_init(const machine_t *); #endif diff --git a/src/intel_piix.c b/src/intel_piix.c index 49b5757f1..41de30e14 100644 --- a/src/intel_piix.c +++ b/src/intel_piix.c @@ -95,6 +95,7 @@ typedef struct regs[4][256], readout_regs[256], board_config[2]; uint16_t func0_id, + nvr_io_base, usb_io_base, power_io_base; sff8038i_t *bm[2]; ddma_t ddma[2]; @@ -306,7 +307,7 @@ ddma_update_io_mapping(piix_t *dev, int n) int base_reg = 0x92 + (n << 1); if (dev->ddma[n].io_base != 0x0000) - io_removehandler(dev->usb_io_base, 0x40, ddma_reg_read, NULL, NULL, ddma_reg_write, NULL, NULL, &dev->ddma[n]); + io_removehandler(dev->ddma[n].io_base, 0x40, ddma_reg_read, NULL, NULL, ddma_reg_write, NULL, NULL, &dev->ddma[n]); dev->ddma[n].io_base = (dev->regs[0][base_reg] & ~0x3f) | (dev->regs[0][base_reg + 1] << 8); @@ -462,6 +463,30 @@ smbus_update_io_mapping(piix_t *dev) } +static void +nvr_update_io_mapping(piix_t *dev) +{ + if (dev->nvr_io_base != 0x0000) { + nvr_at_handler(0, dev->nvr_io_base, dev->nvr); + nvr_at_handler(0, dev->nvr_io_base + 0x0002, dev->nvr); + nvr_at_handler(0, dev->nvr_io_base + 0x0004, dev->nvr); + nvr_at_handler(0, dev->nvr_io_base + 0x0006, dev->nvr); + } + + if (dev->type == 5) + dev->power_io_base = (dev->regs[0][0xd5] << 8) | (dev->regs[3][0xd4] & 0xf0); + else + dev->power_io_base = 0x70; + + if ((dev->regs[0][0xcb] & 0x01) && (dev->regs[2][0xff] & 0x10)) + nvr_at_handler(1, dev->nvr_io_base, dev->nvr); + if (dev->regs[0][0xcb] & 0x04) + nvr_at_handler(1, dev->nvr_io_base + 0x0002, dev->nvr); + nvr_at_handler(1, dev->nvr_io_base + 0x0004, dev->nvr); + nvr_at_handler(1, dev->nvr_io_base + 0x0006, dev->nvr); +} + + static void piix_write(int func, int addr, uint8_t val, void *priv) { @@ -538,6 +563,14 @@ piix_write(int func, int addr, uint8_t val, void *priv) if (dev->type > 3) fregs[0x64] = val; break; + case 0x65: + if (dev->type > 4) + fregs[0x65] = val; + break; + case 0x68: + if (dev->type > 4) + fregs[0x68] = val & 0x81; + break; case 0x69: if (dev->type > 1) fregs[0x69] = val & 0xfe; @@ -564,7 +597,7 @@ piix_write(int func, int addr, uint8_t val, void *priv) } break; case 0x6b: - if ((dev->type > 1) && (val & 0x80)) + if ((dev->type > 1) && (dev->type <= 4) && (val & 0x80)) fregs[0x6b] &= 0x7f; return; case 0x70: case 0x71: @@ -586,7 +619,7 @@ piix_write(int func, int addr, uint8_t val, void *priv) case 0x76: case 0x77: if (dev->type > 1) fregs[addr] = val & 0x87; - else + else if (dev->type <= 4) fregs[addr] = val & 0x8f; break; case 0x78: case 0x79: @@ -601,6 +634,10 @@ piix_write(int func, int addr, uint8_t val, void *priv) if (dev->type > 1) fregs[addr] = val & 0x0f; break; + case 0x82: + if (dev->type > 3) + fregs[addr] = val & 0x0f; + break; case 0x90: if (dev->type > 3) fregs[addr] = val; @@ -610,7 +647,7 @@ piix_write(int func, int addr, uint8_t val, void *priv) fregs[addr] = val & 0xfc; break; case 0x92: case 0x93: case 0x94: case 0x95: - if (dev->type == 4) { + if (dev->type > 3) { if (addr & 0x01) fregs[addr] = val & 0xc0; else @@ -666,21 +703,36 @@ piix_write(int func, int addr, uint8_t val, void *priv) fregs[addr] = val & 0xfb; break; case 0xcb: - if (dev->type == 4) { + if (dev->type > 3) { fregs[addr] = val & 0x3d; - nvr_at_handler(0, 0x0070, dev->nvr); - nvr_at_handler(0, 0x0072, dev->nvr); - - if ((val & 0x01) && (dev->regs[2][0xff] & 0x10)) - nvr_at_handler(1, 0x0070, dev->nvr); - if (val & 0x04) - nvr_at_handler(1, 0x0072, dev->nvr); + nvr_update_io_mapping(dev); nvr_wp_set(!!(val & 0x08), 0, dev->nvr); nvr_wp_set(!!(val & 0x10), 1, dev->nvr); } break; + case 0xd4: + if ((dev->type > 4) && !(fregs[addr] & 0x01)) { + fregs[addr] = val & 0xf1; + nvr_update_io_mapping(dev); + } + break; + case 0xd5: + if ((dev->type > 4) && !(fregs[0xd4] & 0x01)) { + fregs[addr] = val & 0xff; + nvr_update_io_mapping(dev); + } + break; + case 0xe0: + if (dev->type > 4) + fregs[addr] = val & 0xe7; + break; + case 0xe1: case 0xe4: case 0xe5: case 0xe6: case 0xe7: + case 0xe8: case 0xe9: case 0xea: case 0xeb: + if (dev->type > 4) + fregs[addr] = val; + break; } else if (func == 1) switch(addr) { /* IDE */ case 0x04: fregs[0x04] = (val & 5); @@ -934,7 +986,7 @@ piix_reset_hard(piix_t *dev) sff_bus_master_reset(dev->bm[0], old_base); sff_bus_master_reset(dev->bm[1], old_base + 8); - if (dev->type == 4) { + if (dev->type >= 4) { sff_set_irq_mode(dev->bm[0], 0); sff_set_irq_mode(dev->bm[1], 0); } @@ -951,12 +1003,13 @@ piix_reset_hard(piix_t *dev) nvr_wp_set(0, 1, dev->nvr); nvr_at_handler(1, 0x0074, dev->nvr); nvr_at_handler(1, 0x0076, dev->nvr); + dev->nvr_io_base = 0x0070; } /* Clear all 4 functions' arrays and set their vendor and device ID's. */ for (i = 0; i < 4; i++) { memset(dev->regs[i], 0, 256); - if (dev->func0_id == 0x9460) { + if (dev->type == 5) { dev->regs[i][0x00] = 0x55; dev->regs[i][0x01] = 0x10; /* SMSC */ if (i == 1) { /* IDE controller is 9130, breaking convention */ dev->regs[i][0x02] = 0x30; @@ -977,7 +1030,7 @@ piix_reset_hard(piix_t *dev) piix_log("PIIX Function 0: %02X%02X:%02X%02X\n", fregs[0x01], fregs[0x00], fregs[0x03], fregs[0x02]); fregs[0x04] = 0x07; fregs[0x06] = 0x80; fregs[0x07] = 0x02; - if (dev->type == 4 && dev->func0_id != 0x9460) + if (dev->type == 4) fregs[0x08] = (dev->rev & 0x08) ? 0x02 : (dev->rev & 0x07); else fregs[0x08] = dev->rev; @@ -991,13 +1044,22 @@ piix_reset_hard(piix_t *dev) fregs[0x69] = 0x02; fregs[0x70] = (dev->type < 4) ? 0x80 : 0x00; fregs[0x71] = (dev->type < 3) ? 0x80 : 0x00; - fregs[0x76] = fregs[0x77] = (dev->type > 1) ? 0x04 : 0x0c; + if (dev->type <= 4) { + fregs[0x76] = fregs[0x77] = (dev->type > 1) ? 0x04 : 0x0c; + } fregs[0x78] = (dev->type < 4) ? 0x02 : 0x00; fregs[0xa0] = (dev->type < 4) ? 0x08 : 0x00; fregs[0xa8] = (dev->type < 4) ? 0x0f : 0x00; - if (dev->type == 4) + if (dev->type > 3) fregs[0xb0] = (is_pentium) ? 0x00 : 0x04; fregs[0xcb] = (dev->type > 3) ? 0x21 : 0x00; + if (dev->type > 4) { + fregs[0xd4] = 0x70; + fregs[0xe1] = 0x40; + fregs[0xe6] = 0x12; + fregs[0xe8] = 0x02; + fregs[0xea] = 0x12; + } dev->max_func = 0; /* Function 1: IDE */ @@ -1242,7 +1304,7 @@ const device_t slc90e66_device = { "SMSC SLC90E66 (Victory66)", DEVICE_PCI, - 0x94600004, + 0x94600005, piix_init, piix_close, NULL, diff --git a/src/machine/m_at_slot1.c b/src/machine/m_at_slot1.c index 0220a699b..11191608c 100644 --- a/src/machine/m_at_slot1.c +++ b/src/machine/m_at_slot1.c @@ -123,10 +123,8 @@ machine_at_p2bls_init(const machine_t *model) 0 } }; -#if defined(DEV_BRANCH) && defined(USE_I686) if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_PENTIUM2) machine_hwm.voltages[0] = 2800; /* set higher VCORE (2.8V) for Klamath */ -#endif hwm_set_values(machine_hwm); device_add(&w83781d_device); diff --git a/src/machine/m_at_socket370.c b/src/machine/m_at_socket370.c index db284a73c..e7d302a2a 100644 --- a/src/machine/m_at_socket370.c +++ b/src/machine/m_at_socket370.c @@ -139,7 +139,7 @@ machine_at_apas3_init(const machine_t *model) return ret; } -#if defined(DEV_BRANCH) && defined(USE_I686) && defined(USE_596B) +#if defined(DEV_BRANCH) && defined(USE_596B) int machine_at_bx98_init(const machine_t *model) { @@ -166,4 +166,4 @@ machine_at_bx98_init(const machine_t *model) return ret; } -#endif \ No newline at end of file +#endif diff --git a/src/machine/m_at_socket8.c b/src/machine/m_at_socket8.c index c97161509..70ba64a4f 100644 --- a/src/machine/m_at_socket8.c +++ b/src/machine/m_at_socket8.c @@ -40,9 +40,6 @@ #include "cpu.h" #include <86box/machine.h> -#if defined(DEV_BRANCH) && defined(USE_I686) - - int machine_at_i440fx_init(const machine_t *model) { @@ -103,5 +100,3 @@ machine_at_s1668_init(const machine_t *model) return ret; } - -#endif \ No newline at end of file diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 83df9abcd..219399bb4 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -237,33 +237,20 @@ const machine_t machines[] = { { "[Super 7 MVP3] FIC VA-503+", "ficva503p", MACHINE_CPUS_PENTIUM_SS7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_mvp3_init, NULL }, -#if defined(DEV_BRANCH) && defined(USE_I686) { "[Socket 8 FX] Tyan Titan-Pro AT", "440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_i440fx_init, NULL }, { "[Socket 8 FX] Tyan Titan-Pro ATX", "tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_s1668_init, NULL }, { "[Slot 1 BX] Gigabyte GA-6BXC", "6bxc", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_6bxc_init, NULL }, { "[Slot 1 BX] ASUS P2B-LS", "p2bls", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL }, { "[Slot 1 BX] ABit BF6", "bf6", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_bf6_init, NULL }, -#else - { "[Slot 1 BX] Gigabyte GA-6BXC", "6bxc", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_6bxc_init, NULL }, - { "[Slot 1 BX] ASUS P2B-LS", "p2bls", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL }, - { "[Slot 1 BX] ABit BF6", "bf6", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_bf6_init, NULL }, -#endif -#if defined(DEV_BRANCH) && defined(USE_I686) + { "[Slot 1 ZX] Packard Bell Bora Pro", "borapro", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_borapro_init, NULL }, { "[Socket 370 BX] A-Trend ATC7020BXII", "atc7020bxii", {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_atc7020bxii_init, NULL }, { "[Socket 370 ZX] Soltek SL-63A1", "63a", {{"Intel", cpus_Celeron}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_63a_init, NULL }, { "[Socket 370 APRO] PC Partner APAS3", "apas3", {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_apas3_init, NULL }, -#else - { "[Slot 1 ZX] Packard Bell Bora Pro", "borapro", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_borapro_init, NULL }, - { "[Socket 370 BX] A-Trend ATC7020BXII", "atc7020bxii", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_atc7020bxii_init, NULL }, - { "[Socket 370 ZX] Soltek SL-63A1", "63a", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_63a_init, NULL }, - { "[Socket 370 APRO] PC Partner APAS3", "apas3", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_apas3_init, NULL }, -#endif - -#if defined(DEV_BRANCH) && defined(USE_I686) && defined(USE_596B) +#if defined(DEV_BRANCH) && defined(USE_596B) { "[Socket 370 APRO] Zida Tomato BX98", "bx98", {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_bx98_init, NULL }, #endif diff --git a/src/via_vt82c596b.c b/src/via_vt82c596b.c index fd5c4e20d..4aa548d34 100644 --- a/src/via_vt82c596b.c +++ b/src/via_vt82c596b.c @@ -59,7 +59,7 @@ #define ACPI_IO_ENABLE (1 << 7) #define ACPI_TIMER_32BIT (1 << 3) -#if defined(DEV_BRANCH) && defined(USE_I686) && defined(USE_596B) +#if defined(DEV_BRANCH) && defined(USE_596B) typedef struct { diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw index 311d50036..de4990cfc 100644 --- a/src/win/Makefile.mingw +++ b/src/win/Makefile.mingw @@ -50,9 +50,6 @@ ifeq ($(DEV_BUILD), y) ifndef D2D D2D := y endif - ifndef I686 - I686 := y - endif ifndef LASERXT LASERXT := y endif @@ -120,9 +117,6 @@ else ifndef D2D D2D := n endif - ifndef I686 - I686 := n - endif ifndef LASERXT LASERXT := n endif @@ -465,10 +459,6 @@ OPTS += -DUSE_CRASHDUMP DEVBROBJ += win_crashdump.o endif -ifeq ($(I686), y) -OPTS += -DUSE_I686 -endif - ifeq ($(LASERXT), y) OPTS += -DUSE_LASERXT DEVBROBJ += m_xt_laserxt.o diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw index 8a61d111e..66f503ec2 100644 --- a/src/win/Makefile_ndr.mingw +++ b/src/win/Makefile_ndr.mingw @@ -50,9 +50,6 @@ ifeq ($(DEV_BUILD), y) ifndef D2D D2D := y endif - ifndef I686 - I686 := y - endif ifndef LASERXT LASERXT := y endif @@ -120,9 +117,6 @@ else ifndef D2D D2D := n endif - ifndef I686 - I686 := n - endif ifndef LASERXT LASERXT := n endif @@ -474,10 +468,6 @@ OPTS += -DUSE_CRASHDUMP DEVBROBJ += win_crashdump.o endif -ifeq ($(I686), y) -OPTS += -DUSE_I686 -endif - ifeq ($(LASERXT), y) OPTS += -DUSE_LASERXT DEVBROBJ += m_xt_laserxt.o