From e1180a77df2c605b93b3f1325bba86a54850adf8 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Thu, 14 Mar 2024 01:06:12 +0100
Subject: [PATCH] NCR 53c8xx: Implement the readout of SODL via SBDL when
 STEST2 bit 7 is set, v3.04 BIOS'es now work.

---
 src/scsi/scsi_ncr53c8xx.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/scsi/scsi_ncr53c8xx.c b/src/scsi/scsi_ncr53c8xx.c
index 42925338d..ad1b31fe8 100644
--- a/src/scsi/scsi_ncr53c8xx.c
+++ b/src/scsi/scsi_ncr53c8xx.c
@@ -280,6 +280,7 @@ typedef struct ncr53c8xx_t {
     uint8_t swide;
     uint8_t gpcntl;
     uint8_t last_command;
+    uint8_t sodl;
 
     int                command_complete;
     ncr53c8xx_request *current;
@@ -1704,6 +1705,8 @@ ncr53c8xx_reg_writeb(ncr53c8xx_t *dev, uint32_t offset, uint8_t val)
             dev->stest3 = val;
             break;
         case 0x54:
+            dev->sodl = val;
+            break;
         case 0x55:
             break;
             CASE_SET_REG32(scratchb, 0x5c)
@@ -1989,6 +1992,9 @@ ncr53c8xx_reg_readb(ncr53c8xx_t *dev, uint32_t offset)
             if ((dev->sstat1 & PHASE_MASK) == PHASE_MI) {
                 ncr53c8xx_log("NCR 810: Read SBDL %02X\n", dev->msg[0]);
                 return dev->msg[0];
+            } else if (dev->stest2 & 0x80) {
+                ncr53c8xx_log("NCR 810: Read SBDL %02X\n", dev->sodl);
+                return dev->sodl;
             }
             ncr53c8xx_log("NCR 810: Read SBDL 00\n");
             return 0;