80486DX2-66/86Box-fork
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Removed ROM set checking from all the emulated Super I/O chips that did it;

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Ported over the ET4000AX init function clean-up from VARCem;
Cleaned up the S3 Vision864/Trio32/Trio64 init stuff.
This commit is contained in:
OBattler
2018-09-15 02:48:54 +02:00
parent 9cfa5bb80e
commit e401ea0e7b
5 changed files with 749 additions and 675 deletions
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4
src/sio.h
View File

@@ -8,7 +8,7 @@
* *
* Definitions for the Super I/O chips. * Definitions for the Super I/O chips.
* *
* Version: @(#)sio.h 1.0.2 2017/10/26 * Version: @(#)sio.h 1.0.3 2018/09/15
* *
* Author: Fred N. van Kempen, <decwiz@yahoo.com> * Author: Fred N. van Kempen, <decwiz@yahoo.com>
* Copyright 2017 Fred N. van Kempen. * Copyright 2017 Fred N. van Kempen.
@@ -25,7 +25,7 @@ extern void fdc37c932fr_init(void);
extern void fdc37c935_init(void); extern void fdc37c935_init(void);
extern void pc87306_init(void); extern void pc87306_init(void);
extern void um8669f_init(void); extern void um8669f_init(void);
extern void w83877f_init(void); extern void w83877f_init(uint8_t reg16init);
#endif /*EMU_SIO_H*/ #endif /*EMU_SIO_H*/

6
src/sio_fdc37c66x.c
View File

@@ -9,7 +9,7 @@
* Implementation of the SMC FDC37C663 and FDC37C665 Super * Implementation of the SMC FDC37C663 and FDC37C665 Super
* I/O Chips. * I/O Chips.
* *
* Version: @(#)sio_fdc37c66x.c 1.0.11 2018/04/04 * Version: @(#)sio_fdc37c66x.c 1.0.12 2018/09/15
* *
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/> * Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com> * Miran Grca, <mgrca8@gmail.com>
@@ -56,10 +56,6 @@ static void ide_handler()
{ {
#if 0 #if 0
uint16_t or_value = 0; uint16_t or_value = 0;
if ((romset == ROM_440FX) || (romset == ROM_R418) || (romset == ROM_MB500N))
{
return;
}
ide_pri_disable(); ide_pri_disable();
if (fdc37c66x_regs[0] & 1) if (fdc37c66x_regs[0] & 1)
{ {

8
src/sio_w83877f.c
View File

@@ -11,7 +11,7 @@
* Winbond W83877F Super I/O Chip * Winbond W83877F Super I/O Chip
* Used by the Award 430HX * Used by the Award 430HX
* *
* Version: @(#)sio_w83877f.c 1.0.11 2018/04/29 * Version: @(#)sio_w83877f.c 1.0.12 2018/09/12
* *
* Author: Miran Grca, <mgrca8@gmail.com> * Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2016-2018 Miran Grca. * Copyright 2016-2018 Miran Grca.
@@ -39,6 +39,7 @@ static int w83877f_rw_locked = 0;
static int w83877f_curreg = 0; static int w83877f_curreg = 0;
static uint8_t w83877f_regs[0x2A]; static uint8_t w83877f_regs[0x2A];
static uint8_t tries; static uint8_t tries;
static uint8_t w83877f_reg16init = 5;
static fdc_t *w83877f_fdc; static fdc_t *w83877f_fdc;
static int winbond_port = 0x3f0; static int winbond_port = 0x3f0;
@@ -507,7 +508,7 @@ void w83877f_reset(void)
w83877f_regs[0xA] = 0x1F; w83877f_regs[0xA] = 0x1F;
w83877f_regs[0xC] = 0x28; w83877f_regs[0xC] = 0x28;
w83877f_regs[0xD] = 0xA3; w83877f_regs[0xD] = 0xA3;
w83877f_regs[0x16] = (romset == ROM_PRESIDENT) ? 4 : 5; w83877f_regs[0x16] = w83877f_reg16init;
w83877f_regs[0x1E] = 0x81; w83877f_regs[0x1E] = 0x81;
w83877f_regs[0x20] = (0x3f0 >> 2) & 0xfc; w83877f_regs[0x20] = (0x3f0 >> 2) & 0xfc;
w83877f_regs[0x21] = (0x1f0 >> 2) & 0xfc; w83877f_regs[0x21] = (0x1f0 >> 2) & 0xfc;
@@ -528,11 +529,12 @@ void w83877f_reset(void)
} }
void w83877f_init(void) void w83877f_init(uint8_t reg16init)
{ {
w83877f_fdc = device_add(&fdc_at_winbond_device); w83877f_fdc = device_add(&fdc_at_winbond_device);
lpt2_remove(); lpt2_remove();
w83877f_reg16init = reg16init;
w83877f_reset(); w83877f_reset();
} }

723
src/video/vid_et4000.c
View File

@@ -8,13 +8,34 @@
* *
* Emulation of the Tseng Labs ET4000. * Emulation of the Tseng Labs ET4000.
* *
* Version: @(#)vid_et4000.c 1.0.15 2018/08/26 * Version: @(#)vid_et4000.c 1.0.16 2018/09/15
* *
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/> * Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com> * Miran Grca, <mgrca8@gmail.com>
* GreatPsycho, <greatpsycho@yahoo.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
* *
* Copyright 2008-2018 Sarah Walker. * Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca. * Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/ */
#include <stdio.h> #include <stdio.h>
#include <stdint.h> #include <stdint.h>
@@ -34,35 +55,35 @@
#include "vid_et4000.h" #include "vid_et4000.h"
#define BIOS_ROM_PATH L"roms/video/et4000/et4000.bin" #define BIOS_ROM_PATH L"video/tseng/et4000/et4000.bin"
#define KOREAN_BIOS_ROM_PATH L"roms/video/et4000/tgkorvga.bin" #define KOREAN_BIOS_ROM_PATH L"video/tseng/et4000/tgkorvga.bin"
#define KOREAN_FONT_ROM_PATH L"roms/video/et4000/tg_ksc5601.rom" #define KOREAN_FONT_ROM_PATH L"video/tseng/et4000/tg_ksc5601.rom"
typedef struct et4000_t typedef struct {
{ const char *name;
int type;
svga_t svga; svga_t svga;
sc1502x_ramdac_t ramdac; sc1502x_ramdac_t ramdac;
uint8_t pos_regs[8];
rom_t bios_rom; rom_t bios_rom;
uint8_t banking; uint8_t banking;
uint32_t vram_size,
uint8_t pos_regs[8]; vram_mask;
int is_mca;
uint8_t port_22cb_val; uint8_t port_22cb_val;
uint8_t port_32cb_val; uint8_t port_32cb_val;
int get_korean_font_enabled; int get_korean_font_enabled;
int get_korean_font_index; int get_korean_font_index;
uint16_t get_korean_font_base; uint16_t get_korean_font_base;
uint32_t vram_mask;
uint8_t hcr, mcr;
} et4000_t; } et4000_t;
static uint8_t crtc_mask[0x40] =
{ static const uint8_t crtc_mask[0x40] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
@@ -73,44 +94,158 @@ static uint8_t crtc_mask[0x40] =
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}; };
uint8_t et4000_in(uint16_t addr, void *p);
void et4000_out(uint16_t addr, uint8_t val, void *p) static uint8_t
et4000_in(uint16_t addr, void *priv)
{ {
et4000_t *et4000 = (et4000_t *)p; et4000_t *dev = (et4000_t *)priv;
svga_t *svga = &et4000->svga; svga_t *svga = &dev->svga;
if (((addr & 0xfff0) == 0x3d0 ||
(addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1)) addr ^= 0x60;
switch (addr) {
case 0x3c2:
if (dev->type == 1) {
if ((svga->vgapal[0].r + svga->vgapal[0].g + svga->vgapal[0].b) >= 0x4e)
return 0;
else
return 0x10;
}
break;
case 0x3c5:
if ((svga->seqaddr & 0xf) == 7)
return svga->seqregs[svga->seqaddr & 0xf] | 4;
break;
case 0x3c6:
case 0x3c7:
case 0x3c8:
case 0x3c9:
return sc1502x_ramdac_in(addr, &dev->ramdac, svga);
case 0x3cd: /*Banking*/
return dev->banking;
case 0x3d4:
return svga->crtcreg;
case 0x3d5:
return svga->crtc[svga->crtcreg];
}
return svga_in(addr, svga);
}
static uint8_t
et4000k_in(uint16_t addr, void *priv)
{
et4000_t *dev = (et4000_t *)priv;
uint8_t val = 0xff;
// if (addr != 0x3da) pclog("IN ET4000 %04X\n", addr);
switch (addr) {
case 0x22cb:
return dev->port_22cb_val;
case 0x22cf:
val = 0;
switch(dev->get_korean_font_enabled) {
case 3:
if ((dev->port_32cb_val & 0x30) == 0x30) {
val = fontdatksc5601[dev->get_korean_font_base].chr[dev->get_korean_font_index++];
dev->get_korean_font_index &= 0x1f;
} else
if ((dev->port_32cb_val & 0x30) == 0x20 &&
(dev->get_korean_font_base & 0x7f) > 0x20 &&
(dev->get_korean_font_base & 0x7f) < 0x7f) {
switch(dev->get_korean_font_base & 0x3f80) {
case 0x2480:
if (dev->get_korean_font_index < 16)
val = fontdatksc5601_user[(dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index];
else
if (dev->get_korean_font_index >= 24 && dev->get_korean_font_index < 40)
val = fontdatksc5601_user[(dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index - 8];
break;
case 0x3f00:
if (dev->get_korean_font_index < 16)
val = fontdatksc5601_user[96 + (dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index];
else
if (dev->get_korean_font_index >= 24 && dev->get_korean_font_index < 40)
val = fontdatksc5601_user[96 + (dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index - 8];
break;
default:
break;
}
dev->get_korean_font_index++;
dev->get_korean_font_index %= 72;
}
break;
case 4:
val = 0x0f;
break;
default:
break;
}
return val;
case 0x32cb:
return dev->port_32cb_val;
default:
return et4000_in(addr, priv);
}
}
static void
et4000_out(uint16_t addr, uint8_t val, void *priv)
{
et4000_t *dev = (et4000_t *)priv;
svga_t *svga = &dev->svga;
uint8_t old; uint8_t old;
if (((addr&0xFFF0) == 0x3D0 || (addr&0xFFF0) == 0x3B0) && !(svga->miscout & 1)) if (((addr & 0xfff0) == 0x3d0 ||
addr ^= 0x60; (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1)) addr ^= 0x60;
switch (addr) switch (addr) {
{ case 0x3c6:
case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9: case 0x3c7:
sc1502x_ramdac_out(addr, val, &et4000->ramdac, svga); case 0x3c8:
case 0x3c9:
sc1502x_ramdac_out(addr, val, &dev->ramdac, svga);
return; return;
case 0x3CD: /*Banking*/ case 0x3cd: /*Banking*/
if (!(svga->crtc[0x36] & 0x10) && !(svga->gdcreg[6] & 0x08)) { if (!(svga->crtc[0x36] & 0x10) && !(svga->gdcreg[6] & 0x08)) {
svga->write_bank = (val & 0xf) * 0x10000; svga->write_bank = (val & 0xf) * 0x10000;
svga->read_bank = ((val >> 4) & 0xf) * 0x10000; svga->read_bank = ((val >> 4) & 0xf) * 0x10000;
} }
et4000->banking = val; dev->banking = val;
return; return;
case 0x3cf: case 0x3cf:
if ((svga->gdcaddr & 15) == 6) { if ((svga->gdcaddr & 15) == 6) {
if (!(svga->crtc[0x36] & 0x10) && !(val & 0x08)) { if (!(svga->crtc[0x36] & 0x10) && !(val & 0x08)) {
svga->write_bank = (et4000->banking & 0xf) * 0x10000; svga->write_bank = (dev->banking & 0x0f) * 0x10000;
svga->read_bank = ((et4000->banking >> 4) & 0xf) * 0x10000; svga->read_bank = ((dev->banking >> 4) & 0x0f) * 0x10000;
} else } else
svga->write_bank = svga->read_bank = 0; svga->write_bank = svga->read_bank = 0;
} }
break; break;
case 0x3D4:
case 0x3d4:
svga->crtcreg = val & 0x3f; svga->crtcreg = val & 0x3f;
return; return;
case 0x3D5:
case 0x3d5:
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80)) if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return; return;
if ((svga->crtcreg == 0x35) && (svga->crtc[0x11] & 0x80)) if ((svga->crtcreg == 0x35) && (svga->crtc[0x11] & 0x80))
@@ -123,26 +258,25 @@ void et4000_out(uint16_t addr, uint8_t val, void *p)
if (svga->crtcreg == 0x36) { if (svga->crtcreg == 0x36) {
if (!(val & 0x10) && !(svga->gdcreg[6] & 0x08)) { if (!(val & 0x10) && !(svga->gdcreg[6] & 0x08)) {
svga->write_bank = (et4000->banking & 0xf) * 0x10000; svga->write_bank = (dev->banking & 0x0f) * 0x10000;
svga->read_bank = ((et4000->banking >> 4) & 0xf) * 0x10000; svga->read_bank = ((dev->banking >> 4) & 0x0f) * 0x10000;
} else } else
svga->write_bank = svga->read_bank = 0; svga->write_bank = svga->read_bank = 0;
} }
if (old != val) if (old != val) {
{ if (svga->crtcreg < 0x0e || svga->crtcreg > 0x10) {
if (svga->crtcreg < 0xE || svga->crtcreg > 0x10)
{
svga->fullchange = changeframecount; svga->fullchange = changeframecount;
svga_recalctimings(svga); svga_recalctimings(svga);
} }
} }
/*Note - Silly hack to determine video memory size automatically by ET4000 BIOS.*/ /*
if ((svga->crtcreg == 0x37) && !et4000->is_mca) * Note - Silly hack to determine video memory
{ * size automatically by ET4000 BIOS.
switch(val & 0x0B) */
{ if ((svga->crtcreg == 0x37) && (dev->type != 1)) {
switch (val & 0x0b) {
case 0x00: case 0x00:
case 0x01: case 0x01:
if (svga->vram_max == 64 * 1024) if (svga->vram_max == 64 * 1024)
@@ -150,12 +284,14 @@ void et4000_out(uint16_t addr, uint8_t val, void *p)
else else
mem_mapping_disable(&svga->mapping); mem_mapping_disable(&svga->mapping);
break; break;
case 0x02: case 0x02:
if (svga->vram_max == 128 * 1024) if (svga->vram_max == 128 * 1024)
mem_mapping_enable(&svga->mapping); mem_mapping_enable(&svga->mapping);
else else
mem_mapping_disable(&svga->mapping); mem_mapping_disable(&svga->mapping);
break; break;
case 0x03: case 0x03:
case 0x08: case 0x08:
case 0x09: case 0x09:
@@ -164,18 +300,21 @@ void et4000_out(uint16_t addr, uint8_t val, void *p)
else else
mem_mapping_disable(&svga->mapping); mem_mapping_disable(&svga->mapping);
break; break;
case 0x0A:
case 0x0a:
if (svga->vram_max == 512 * 1024) if (svga->vram_max == 512 * 1024)
mem_mapping_enable(&svga->mapping); mem_mapping_enable(&svga->mapping);
else else
mem_mapping_disable(&svga->mapping); mem_mapping_disable(&svga->mapping);
break; break;
case 0x0B:
case 0x0b:
if (svga->vram_max == 1024 * 1024) if (svga->vram_max == 1024 * 1024)
mem_mapping_enable(&svga->mapping); mem_mapping_enable(&svga->mapping);
else else
mem_mapping_disable(&svga->mapping); mem_mapping_disable(&svga->mapping);
break; break;
default: default:
mem_mapping_enable(&svga->mapping); mem_mapping_enable(&svga->mapping);
break; break;
@@ -183,166 +322,86 @@ void et4000_out(uint16_t addr, uint8_t val, void *p)
} }
break; break;
} }
svga_out(addr, val, svga); svga_out(addr, val, svga);
} }
uint8_t et4000_in(uint16_t addr, void *p)
static void
et4000k_out(uint16_t addr, uint8_t val, void *priv)
{ {
et4000_t *et4000 = (et4000_t *)p; et4000_t *dev = (et4000_t *)priv;
svga_t *svga = &et4000->svga;
if (((addr&0xFFF0) == 0x3D0 || (addr&0xFFF0) == 0x3B0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr)
{
case 0x3c2:
if (et4000->is_mca)
{
if ((svga->vgapal[0].r + svga->vgapal[0].g + svga->vgapal[0].b) >= 0x4e)
return 0;
else
return 0x10;
}
break;
case 0x3C5:
if ((svga->seqaddr & 0xf) == 7) return svga->seqregs[svga->seqaddr & 0xf] | 4;
break;
case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9:
return sc1502x_ramdac_in(addr, &et4000->ramdac, svga);
case 0x3CD: /*Banking*/
return et4000->banking;
case 0x3D4:
return svga->crtcreg;
case 0x3D5:
return svga->crtc[svga->crtcreg];
}
return svga_in(addr, svga);
}
void et4000k_out(uint16_t addr, uint8_t val, void *p)
{
et4000_t *et4000 = (et4000_t *)p;
// pclog("ET4000k out %04X %02X\n", addr, val); // pclog("ET4000k out %04X %02X\n", addr, val);
switch (addr) switch (addr) {
{ case 0x22cb:
case 0x22CB: dev->port_22cb_val = (dev->port_22cb_val & 0xf0) | (val & 0x0f);
et4000->port_22cb_val = (et4000->port_22cb_val & 0xF0) | (val & 0x0F); dev->get_korean_font_enabled = val & 7;
et4000->get_korean_font_enabled = val & 7; if (dev->get_korean_font_enabled == 3)
if (et4000->get_korean_font_enabled == 3) dev->get_korean_font_index = 0;
et4000->get_korean_font_index = 0;
break; break;
case 0x22CF:
switch(et4000->get_korean_font_enabled) case 0x22cf:
{ switch(dev->get_korean_font_enabled) {
case 1: case 1:
et4000->get_korean_font_base = ((val & 0x7F) << 7) | (et4000->get_korean_font_base & 0x7F); dev->get_korean_font_base = ((val & 0x7f) << 7) | (dev->get_korean_font_base & 0x7f);
break; break;
case 2: case 2:
et4000->get_korean_font_base = (et4000->get_korean_font_base & 0x3F80) | (val & 0x7F) | (((val ^ 0x80) & 0x80) << 8); dev->get_korean_font_base = (dev->get_korean_font_base & 0x3f80) | (val & 0x7f) | (((val ^ 0x80) & 0x80) << 8);
break; break;
case 3: case 3:
if((et4000->port_32cb_val & 0x30) == 0x20 && (et4000->get_korean_font_base & 0x7F) > 0x20 && (et4000->get_korean_font_base & 0x7F) < 0x7F) if ((dev->port_32cb_val & 0x30) == 0x20 &&
{ (dev->get_korean_font_base & 0x7f) > 0x20 &&
switch(et4000->get_korean_font_base & 0x3F80) (dev->get_korean_font_base & 0x7f) < 0x7f) {
{ switch (dev->get_korean_font_base & 0x3f80) {
case 0x2480: case 0x2480:
if(et4000->get_korean_font_index < 16) if (dev->get_korean_font_index < 16)
fontdatksc5601_user[(et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index] = val; fontdatksc5601_user[(dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index] = val;
else if(et4000->get_korean_font_index >= 24 && et4000->get_korean_font_index < 40) else
fontdatksc5601_user[(et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index - 8] = val; if (dev->get_korean_font_index >= 24 && dev->get_korean_font_index < 40)
fontdatksc5601_user[(dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index - 8] = val;
break; break;
case 0x3F00:
if(et4000->get_korean_font_index < 16) case 0x3f00:
fontdatksc5601_user[96 + (et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index] = val; if (dev->get_korean_font_index < 16)
else if(et4000->get_korean_font_index >= 24 && et4000->get_korean_font_index < 40) fontdatksc5601_user[96 + (dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index] = val;
fontdatksc5601_user[96 + (et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index - 8] = val; else
if (dev->get_korean_font_index >= 24 && dev->get_korean_font_index < 40)
fontdatksc5601_user[96 + (dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index - 8] = val;
break; break;
default: default:
break; break;
} }
et4000->get_korean_font_index++; dev->get_korean_font_index++;
} }
break; break;
default: default:
break; break;
} }
break; break;
case 0x32CB:
et4000->port_32cb_val = val; case 0x32cb:
svga_recalctimings(&et4000->svga); dev->port_32cb_val = val;
svga_recalctimings(&dev->svga);
break; break;
default: default:
et4000_out(addr, val, p); et4000_out(addr, val, priv);
break; break;
} }
} }
uint8_t et4000k_in(uint16_t addr, void *p)
{
uint8_t val = 0xFF;
et4000_t *et4000 = (et4000_t *)p;
// if (addr != 0x3da) pclog("IN ET4000 %04X\n", addr); static void
et4000_recalctimings(svga_t *svga)
{
et4000_t *dev = (et4000_t *)svga->p;
switch (addr)
{
case 0x22CB:
return et4000->port_22cb_val;
case 0x22CF:
val = 0;
switch(et4000->get_korean_font_enabled)
{
case 3:
if((et4000->port_32cb_val & 0x30) == 0x30)
{
val = fontdatksc5601[et4000->get_korean_font_base].chr[et4000->get_korean_font_index++];
et4000->get_korean_font_index &= 0x1F;
}
else if((et4000->port_32cb_val & 0x30) == 0x20 && (et4000->get_korean_font_base & 0x7F) > 0x20 && (et4000->get_korean_font_base & 0x7F) < 0x7F)
{
switch(et4000->get_korean_font_base & 0x3F80)
{
case 0x2480:
if(et4000->get_korean_font_index < 16)
val = fontdatksc5601_user[(et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index];
else if(et4000->get_korean_font_index >= 24 && et4000->get_korean_font_index < 40)
val = fontdatksc5601_user[(et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index - 8];
break;
case 0x3F00:
if(et4000->get_korean_font_index < 16)
val = fontdatksc5601_user[96 + (et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index];
else if(et4000->get_korean_font_index >= 24 && et4000->get_korean_font_index < 40)
val = fontdatksc5601_user[96 + (et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index - 8];
break;
default:
break;
}
et4000->get_korean_font_index++;
et4000->get_korean_font_index %= 72;
}
break;
case 4:
val = 0x0F;
break;
default:
break;
}
return val;
case 0x32CB:
return et4000->port_32cb_val;
default:
return et4000_in(addr, p);
}
}
void et4000_recalctimings(svga_t *svga)
{
svga->ma_latch |= (svga->crtc[0x33]&3)<<16; svga->ma_latch |= (svga->crtc[0x33]&3)<<16;
if (svga->crtc[0x35] & 1) svga->vblankstart += 0x400; if (svga->crtc[0x35] & 1) svga->vblankstart += 0x400;
if (svga->crtc[0x35] & 2) svga->vtotal += 0x400; if (svga->crtc[0x35] & 2) svga->vtotal += 0x400;
@@ -353,88 +412,46 @@ void et4000_recalctimings(svga_t *svga)
if (svga->crtc[0x3f] & 1) svga->htotal += 256; if (svga->crtc[0x3f] & 1) svga->htotal += 256;
if (svga->attrregs[0x16] & 0x20) svga->hdisp <<= 1; if (svga->attrregs[0x16] & 0x20) svga->hdisp <<= 1;
switch (((svga->miscout >> 2) & 3) | ((svga->crtc[0x34] << 1) & 4)) switch (((svga->miscout >> 2) & 3) | ((svga->crtc[0x34] << 1) & 4)) {
{ case 0:
case 0: case 1: break; case 1:
case 3: svga->clock = cpuclock / 40000000.0; break; break;
case 5: svga->clock = cpuclock / 65000000.0; break;
default: svga->clock = cpuclock / 36000000.0; break; case 3:
svga->clock = cpuclock / 40000000.0;
break;
case 5:
svga->clock = cpuclock / 65000000.0;
break;
default:
svga->clock = cpuclock / 36000000.0;
break;
} }
switch (svga->bpp) switch (svga->bpp) {
{ case 15:
case 15: case 16: case 16:
svga->hdisp /= 2; svga->hdisp /= 2;
break; break;
case 24: case 24:
svga->hdisp /= 3; svga->hdisp /= 3;
break; break;
} }
}
void et4000k_recalctimings(svga_t *svga) if (dev->type == 2 || dev->type == 3) {
{ #if NOT_YET
et4000_t *et4000 = (et4000_t *)svga->p; if ((svga->render == svga_render_text_80) && ((svga->crtc[0x37] & 0x0A) == 0x0A)) {
if ((dev->port_32cb_val & 0xB4) == ((svga->crtc[0x37] & 3) == 2 ? 0xB4 : 0xB0)) {
et4000_recalctimings(svga);
if (svga->render == svga_render_text_80 && ((svga->crtc[0x37] & 0x0A) == 0x0A))
{
if((et4000->port_32cb_val & 0xB4) == ((svga->crtc[0x37] & 3) == 2 ? 0xB4 : 0xB0))
{
svga->render = svga_render_text_80_ksc5601; svga->render = svga_render_text_80_ksc5601;
} }
} }
#endif
}
} }
void *et4000_isa_init(const device_t *info)
{
et4000_t *et4000 = malloc(sizeof(et4000_t));
memset(et4000, 0, sizeof(et4000_t));
et4000->is_mca = 0;
rom_init(&et4000->bios_rom, BIOS_ROM_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
io_sethandler(0x03c0, 0x0020, et4000_in, NULL, NULL, et4000_out, NULL, NULL, et4000);
svga_init(&et4000->svga, et4000, device_get_config_int("memory") << 10, /*1mb default*/
et4000_recalctimings,
et4000_in, et4000_out,
NULL,
NULL);
et4000->vram_mask = (device_get_config_int("memory") << 10) - 1;
return et4000;
}
void *et4000k_isa_init(const device_t *info)
{
et4000_t *et4000 = malloc(sizeof(et4000_t));
memset(et4000, 0, sizeof(et4000_t));
rom_init(&et4000->bios_rom, KOREAN_BIOS_ROM_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
loadfont(KOREAN_FONT_ROM_PATH, 6);
io_sethandler(0x03c0, 0x0020, et4000_in, NULL, NULL, et4000_out, NULL, NULL, et4000);
io_sethandler(0x22cb, 0x0001, et4000k_in, NULL, NULL, et4000k_out, NULL, NULL, et4000);
io_sethandler(0x22cf, 0x0001, et4000k_in, NULL, NULL, et4000k_out, NULL, NULL, et4000);
io_sethandler(0x32cb, 0x0001, et4000k_in, NULL, NULL, et4000k_out, NULL, NULL, et4000);
et4000->port_22cb_val = 0x60;
et4000->port_32cb_val = 0;
svga_init(&et4000->svga, et4000, device_get_config_int("memory") << 10,
et4000k_recalctimings,
et4000k_in, et4000k_out,
NULL,
NULL);
et4000->vram_mask = (device_get_config_int("memory") << 10) - 1;
et4000->svga.ksc5601_sbyte_mask = 0x80;
return et4000;
}
static uint8_t static uint8_t
et4000_mca_read(int port, void *priv) et4000_mca_read(int port, void *priv)
@@ -444,6 +461,7 @@ et4000_mca_read(int port, void *priv)
return(et4000->pos_regs[port & 7]); return(et4000->pos_regs[port & 7]);
} }
static void static void
et4000_mca_write(int port, uint8_t val, void *priv) et4000_mca_write(int port, uint8_t val, void *priv)
{ {
@@ -456,137 +474,182 @@ et4000_mca_write(int port, uint8_t val, void *priv)
et4000->pos_regs[port & 7] = val; et4000->pos_regs[port & 7] = val;
} }
void *et4000_mca_init(const device_t *info)
static void *
et4000_init(const device_t *info)
{ {
et4000_t *et4000 = malloc(sizeof(et4000_t)); const wchar_t *fn;
memset(et4000, 0, sizeof(et4000_t)); et4000_t *dev;
et4000->is_mca = 1; dev = (et4000_t *)malloc(sizeof(et4000_t));
memset(dev, 0x00, sizeof(et4000_t));
dev->name = info->name;
dev->type = info->local;
fn = BIOS_ROM_PATH;
/* Enable MCA. */ switch(dev->type) {
et4000->pos_regs[0] = 0xF2; /* ET4000 MCA board ID */ case 0: /* ISA ET4000AX */
et4000->pos_regs[1] = 0x80; dev->vram_size = device_get_config_int("memory") << 10;
mca_add(et4000_mca_read, et4000_mca_write, et4000); svga_init(&dev->svga, dev, dev->vram_size,
et4000_recalctimings, et4000_in, et4000_out,
NULL, NULL);
io_sethandler(0x03c0, 32,
et4000_in,NULL,NULL, et4000_out,NULL,NULL, dev);
break;
rom_init(&et4000->bios_rom, BIOS_ROM_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); case 1: /* MCA ET4000AX */
dev->vram_size = 1024 << 10;
svga_init(&dev->svga, dev, dev->vram_size,
et4000_recalctimings, et4000_in, et4000_out,
NULL, NULL);
io_sethandler(0x03c0, 32,
et4000_in,NULL,NULL, et4000_out,NULL,NULL, dev);
dev->pos_regs[0] = 0xf2; /* ET4000 MCA board ID */
dev->pos_regs[1] = 0x80;
mca_add(et4000_mca_read, et4000_mca_write, dev);
break;
svga_init(&et4000->svga, et4000, 1 << 20, /*1mb*/ case 2: /* Korean ET4000 */
et4000_recalctimings, case 3: /* Trigem 286M ET4000 */
et4000_in, et4000_out, dev->vram_size = device_get_config_int("memory") << 10;
NULL, dev->port_22cb_val = 0x60;
NULL); dev->port_32cb_val = 0;
et4000->vram_mask = (1 << 20) - 1; dev->svga.ksc5601_sbyte_mask = 0x80;
svga_init(&dev->svga, dev, dev->vram_size,
io_sethandler(0x03c0, 0x0020, et4000_in, NULL, NULL, et4000_out, NULL, NULL, et4000); et4000_recalctimings, et4000k_in, et4000k_out,
NULL, NULL);
return et4000; io_sethandler(0x03c0, 32,
et4000k_in,NULL,NULL, et4000k_out,NULL,NULL, dev);
io_sethandler(0x22cb, 1,
et4000k_in,NULL,NULL, et4000k_out,NULL,NULL, dev);
io_sethandler(0x22cf, 1,
et4000k_in,NULL,NULL, et4000k_out,NULL,NULL, dev);
io_sethandler(0x32cb, 1,
et4000k_in,NULL,NULL, et4000k_out,NULL,NULL, dev);
loadfont(KOREAN_FONT_ROM_PATH, 6);
fn = KOREAN_BIOS_ROM_PATH;
break;
} }
static int et4000_available(void) dev->vram_mask = dev->vram_size - 1;
rom_init(&dev->bios_rom, (wchar_t *) fn,
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
pclog("VIDEO: %s (vram=%dKB)\n", dev->name, dev->vram_size>>10);
return(dev);
}
static void
et4000_close(void *priv)
{
et4000_t *dev = (et4000_t *)priv;
svga_close(&dev->svga);
free(dev);
}
static void
et4000_speed_changed(void *priv)
{
et4000_t *dev = (et4000_t *)priv;
svga_recalctimings(&dev->svga);
}
static void
et4000_force_redraw(void *priv)
{
et4000_t *dev = (et4000_t *)priv;
dev->svga.fullchange = changeframecount;
}
static int
et4000_available(void)
{ {
return rom_present(BIOS_ROM_PATH); return rom_present(BIOS_ROM_PATH);
} }
static int et4000k_available()
static int
et4000k_available(void)
{ {
return rom_present(KOREAN_BIOS_ROM_PATH) && rom_present(KOREAN_FONT_ROM_PATH); return rom_present(KOREAN_BIOS_ROM_PATH) &&
rom_present(KOREAN_FONT_ROM_PATH);
} }
void et4000_close(void *p)
{
et4000_t *et4000 = (et4000_t *)p;
svga_close(&et4000->svga); static const device_config_t et4000_config[] =
free(et4000);
}
void et4000_speed_changed(void *p)
{
et4000_t *et4000 = (et4000_t *)p;
svga_recalctimings(&et4000->svga);
}
void et4000_force_redraw(void *p)
{
et4000_t *et4000 = (et4000_t *)p;
et4000->svga.fullchange = changeframecount;
}
static device_config_t et4000_config[] =
{ {
{ {
.name = "memory", "memory", "Memory size", CONFIG_SELECTION, "", 1024,
.description = "Memory size",
.type = CONFIG_SELECTION,
.selection =
{ {
{ {
.description = "256 kB", "256 KB", 256
.value = 256
}, },
{ {
.description = "512 kB", "512 KB", 512
.value = 512
}, },
{ {
.description = "1 MB", "1 MB", 1024
.value = 1024
}, },
{ {
.description = "" ""
}
} }
}, },
.default_int = 1024
},
{ {
.type = -1 "", "", -1
} }
}; };
const device_t et4000_isa_device = const device_t et4000_isa_device = {
{
"Tseng Labs ET4000AX (ISA)", "Tseng Labs ET4000AX (ISA)",
DEVICE_ISA, 0, DEVICE_ISA,
et4000_isa_init, et4000_close, NULL, 0,
et4000_init, et4000_close, NULL,
et4000_available, et4000_available,
et4000_speed_changed, et4000_speed_changed,
et4000_force_redraw, et4000_force_redraw,
et4000_config et4000_config
}; };
const device_t et4000k_isa_device = const device_t et4000_mca_device = {
{
"Trigem Korean VGA (Tseng Labs ET4000AX Korean)",
DEVICE_ISA, 0,
et4000k_isa_init, et4000_close, NULL,
et4000k_available,
et4000_speed_changed,
et4000_force_redraw,
et4000_config
};
const device_t et4000k_tg286_isa_device =
{
"Trigem Korean VGA (Trigem 286M)",
DEVICE_ISA, 0,
et4000k_isa_init, et4000_close, NULL,
et4000k_available,
et4000_speed_changed,
et4000_force_redraw,
et4000_config
};
const device_t et4000_mca_device =
{
"Tseng Labs ET4000AX (MCA)", "Tseng Labs ET4000AX (MCA)",
DEVICE_MCA, 0, DEVICE_MCA,
et4000_mca_init, et4000_close, NULL, 1,
et4000_init, et4000_close, NULL,
et4000_available, et4000_available,
et4000_speed_changed, et4000_speed_changed,
et4000_force_redraw, et4000_force_redraw,
NULL et4000_config
}; };
const device_t et4000k_isa_device = {
"Trigem Korean VGA (Tseng Labs ET4000AX Korean)",
DEVICE_ISA,
2,
et4000_init, et4000_close, NULL,
et4000k_available,
et4000_speed_changed,
et4000_force_redraw,
et4000_config
};
const device_t et4000k_tg286_isa_device = {
"Trigem Korean VGA (Trigem 286M)",
DEVICE_ISA,
3,
et4000_init, et4000_close, NULL,
et4000k_available,
et4000_speed_changed,
et4000_force_redraw,
et4000_config
};

241
src/video/vid_s3.c
View File

@@ -8,7 +8,7 @@
* *
* S3 emulation. * S3 emulation.
* *
* Version: @(#)vid_s3.c 1.0.11 2018/07/16 * Version: @(#)vid_s3.c 1.0.12 2018/09/15
* *
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/> * Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com> * Miran Grca, <mgrca8@gmail.com>
@@ -34,6 +34,24 @@
#include "vid_svga_render.h" #include "vid_svga_render.h"
#include "vid_sdac_ramdac.h" #include "vid_sdac_ramdac.h"
#define ROM_PARADISE_BAHAMAS64 L"roms/video/s3/bahamas64.bin"
#define ROM_PHOENIX_VISION864 L"roms/video/s3/86c864p.bin"
#define ROM_PHOENIX_TRIO32 L"roms/video/s3/86c732p.bin"
#define ROM_NUMBER9_9FX L"roms/video/s3/s3_764.bin"
#define ROM_PHOENIX_TRIO64 L"roms/video/s3/86c764x1.bin"
#define ROM_DIAMOND_STEALTH64 L"roms/video/s3/stealt64.bin"
enum
{
S3_PARADISE_BAHAMAS64,
S3_NUMBER9_9FX,
S3_PHOENIX_TRIO32,
S3_PHOENIX_TRIO64,
S3_PHOENIX_TRIO64_ONBOARD,
S3_PHOENIX_VISION864,
S3_DIAMOND_STEALTH64
};
enum enum
{ {
S3_VISION864, S3_VISION864,
@@ -2690,13 +2708,48 @@ static int vram_sizes[] =
3 /*8 MB*/ 3 /*8 MB*/
}; };
static void *s3_init(const device_t *info, wchar_t *bios_fn, int chip) static void *s3_init(const device_t *info)
{ {
const wchar_t *bios_fn;
int chip;
s3_t *s3 = malloc(sizeof(s3_t)); s3_t *s3 = malloc(sizeof(s3_t));
svga_t *svga = &s3->svga; svga_t *svga = &s3->svga;
int vram; int vram;
uint32_t vram_size; uint32_t vram_size;
switch(info->local) {
case S3_PARADISE_BAHAMAS64:
bios_fn = ROM_PARADISE_BAHAMAS64;
chip = S3_VISION864;
break;
case S3_PHOENIX_VISION864:
bios_fn = ROM_PHOENIX_VISION864;
chip = S3_VISION864;
break;
case S3_PHOENIX_TRIO32:
bios_fn = ROM_PHOENIX_TRIO32;
chip = S3_TRIO32;
break;
case S3_PHOENIX_TRIO64:
bios_fn = ROM_PHOENIX_TRIO64;
chip = S3_TRIO64;
break;
case S3_PHOENIX_TRIO64_ONBOARD:
bios_fn = NULL;
chip = S3_TRIO64;
break;
case S3_DIAMOND_STEALTH64:
bios_fn = ROM_DIAMOND_STEALTH64;
chip = S3_TRIO64;
break;
case S3_NUMBER9_9FX:
bios_fn = ROM_NUMBER9_9FX;
chip = S3_TRIO64;
break;
default:
return NULL;
}
memset(s3, 0, sizeof(s3_t)); memset(s3, 0, sizeof(s3_t));
vram = device_get_config_int("memory"); vram = device_get_config_int("memory");
@@ -2706,41 +2759,48 @@ static void *s3_init(const device_t *info, wchar_t *bios_fn, int chip)
vram_size = 512 << 10; vram_size = 512 << 10;
s3->vram_mask = vram_size - 1; s3->vram_mask = vram_size - 1;
s3->has_bios = !info->local; s3->has_bios = (bios_fn != NULL);
if (s3->has_bios) { if (s3->has_bios) {
rom_init(&s3->bios_rom, bios_fn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); rom_init(&s3->bios_rom, (wchar_t *) bios_fn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (info->flags & DEVICE_PCI) if (info->flags & DEVICE_PCI)
mem_mapping_disable(&s3->bios_rom.mapping); mem_mapping_disable(&s3->bios_rom.mapping);
} }
s3->pci = !!(info->flags & DEVICE_PCI); s3->pci = !!(info->flags & DEVICE_PCI);
mem_mapping_add(&s3->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL, MEM_MAPPING_EXTERNAL, &s3->svga); mem_mapping_add(&s3->linear_mapping, 0, 0,
mem_mapping_add(&s3->mmio_mapping, 0xa0000, 0x10000, s3_accel_read, NULL, NULL, s3_accel_write, s3_accel_write_w, s3_accel_write_l, NULL, MEM_MAPPING_EXTERNAL, s3); svga_read_linear, svga_readw_linear, svga_readl_linear,
svga_write_linear, svga_writew_linear, svga_writel_linear,
NULL, MEM_MAPPING_EXTERNAL, &s3->svga);
mem_mapping_add(&s3->mmio_mapping, 0xa0000, 0x10000,
s3_accel_read, NULL, NULL,
s3_accel_write, s3_accel_write_w, s3_accel_write_l,
NULL, MEM_MAPPING_EXTERNAL, s3);
mem_mapping_disable(&s3->mmio_mapping); mem_mapping_disable(&s3->mmio_mapping);
svga_init(&s3->svga, s3, vram_size, /*4mb - 864 supports 8mb but buggy VESA driver reports 0mb*/ svga_init(&s3->svga, s3, vram_size,
s3_recalctimings, s3_recalctimings,
s3_in, s3_out, s3_in, s3_out,
s3_hwcursor_draw, s3_hwcursor_draw,
NULL); NULL);
svga->decode_mask = (4 << 20) - 1; svga->decode_mask = (4 << 20) - 1;
switch (vram) switch (vram) {
{ case 0: /* 512 kB */
case 0: /*512kb*/
svga->vram_mask = (1 << 19) - 1; svga->vram_mask = (1 << 19) - 1;
svga->vram_max = 2 << 20; svga->vram_max = 2 << 20;
break; break;
case 1: /* 1 MB */ case 1: /* 1 MB */
/*VRAM in first MB, mirrored in 2nd MB, 3rd and 4th MBs are open bus*/ /* VRAM in first MB, mirrored in 2nd MB, 3rd and 4th MBs are open bus.
/*This works with the #9 9FX BIOS, and matches how my real Trio64 behaves,
This works with the #9 9FX BIOS, and matches how my real Trio64 behaves,
but does not work with the Phoenix EDO BIOS. Possibly an FPM/EDO difference? */ but does not work with the Phoenix EDO BIOS. Possibly an FPM/EDO difference? */
svga->vram_mask = (1 << 20) - 1; svga->vram_mask = (1 << 20) - 1;
svga->vram_max = 2 << 20; svga->vram_max = 2 << 20;
break; break;
case 2: default: /*2MB*/ case 2:
/*VRAM in first 2 MB, 3rd and 4th MBs are open bus*/ default: /*2 MB */
/* VRAM in first 2 MB, 3rd and 4th MBs are open bus. */
svga->vram_mask = (2 << 20) - 1; svga->vram_mask = (2 << 20) - 1;
svga->vram_max = 2 << 20; svga->vram_max = 2 << 20;
break; break;
@@ -2765,9 +2825,7 @@ static void *s3_init(const device_t *info, wchar_t *bios_fn, int chip)
s3_io_set(s3); s3_io_set(s3);
if (info->flags & DEVICE_PCI) if (info->flags & DEVICE_PCI)
{
s3->card = pci_add_card(PCI_ADD_VIDEO, s3_pci_read, s3_pci_write, s3); s3->card = pci_add_card(PCI_ADD_VIDEO, s3_pci_read, s3_pci_write, s3);
}
s3->pci_regs[0x04] = 7; s3->pci_regs[0x04] = 7;
@@ -2783,13 +2841,9 @@ static void *s3_init(const device_t *info, wchar_t *bios_fn, int chip)
s3->int_line = 0; s3->int_line = 0;
return s3; switch(info->local) {
} case S3_PARADISE_BAHAMAS64:
case S3_PHOENIX_VISION864:
void *s3_vision864_init(const device_t *info, wchar_t *bios_fn)
{
s3_t *s3 = s3_init(info, bios_fn, S3_VISION864);
s3->id = 0xc1; /*Vision864P*/ s3->id = 0xc1; /*Vision864P*/
s3->id_ext = s3->id_ext_pci = 0xc1; s3->id_ext = s3->id_ext_pci = 0xc1;
s3->packed_mmio = 0; s3->packed_mmio = 0;
@@ -2797,37 +2851,9 @@ void *s3_vision864_init(const device_t *info, wchar_t *bios_fn)
s3->getclock = sdac_getclock; s3->getclock = sdac_getclock;
s3->getclock_p = &s3->ramdac; s3->getclock_p = &s3->ramdac;
sdac_init(&s3->ramdac); sdac_init(&s3->ramdac);
break;
return s3; case S3_PHOENIX_TRIO32:
}
static void *s3_bahamas64_init(const device_t *info)
{
s3_t *s3 = s3_vision864_init(info, L"roms/video/s3/bahamas64.bin");
return s3;
}
static void *s3_phoenix_vision864_init(const device_t *info)
{
s3_t *s3 = s3_vision864_init(info, L"roms/video/s3/86c864p.bin");
return s3;
}
static int s3_bahamas64_available(void)
{
return rom_present(L"roms/video/s3/bahamas64.bin");
}
static int s3_phoenix_vision864_available(void)
{
return rom_present(L"roms/video/s3/86c864p.bin");
}
static void *s3_phoenix_trio32_init(const device_t *info)
{
s3_t *s3 = s3_init(info, L"roms/video/s3/86c732p.bin", S3_TRIO32);
s3->id = 0xe1; /*Trio32*/ s3->id = 0xe1; /*Trio32*/
s3->id_ext = 0x10; s3->id_ext = 0x10;
s3->id_ext_pci = 0x11; s3->id_ext_pci = 0x11;
@@ -2835,72 +2861,59 @@ static void *s3_phoenix_trio32_init(const device_t *info)
s3->getclock = s3_trio64_getclock; s3->getclock = s3_trio64_getclock;
s3->getclock_p = s3; s3->getclock_p = s3;
break;
return s3; case S3_PHOENIX_TRIO64:
} case S3_PHOENIX_TRIO64_ONBOARD:
case S3_DIAMOND_STEALTH64:
static int s3_phoenix_trio32_available(void) if (device_get_config_int("memory") == 1)
{ s3->svga.vram_max = 1 << 20; /* Phoenix BIOS does not expect VRAM to be mirrored. */
return rom_present(L"roms/video/s3/86c732p.bin"); /* Fall over. */
}
static void *s3_trio64_init(const device_t *info, wchar_t *bios_fn)
{
s3_t *s3 = s3_init(info, bios_fn, S3_TRIO64);
case S3_NUMBER9_9FX:
s3->id = 0xe1; /*Trio64*/ s3->id = 0xe1; /*Trio64*/
s3->id_ext = s3->id_ext_pci = 0x11; s3->id_ext = s3->id_ext_pci = 0x11;
s3->packed_mmio = 1; s3->packed_mmio = 1;
s3->getclock = s3_trio64_getclock; s3->getclock = s3_trio64_getclock;
s3->getclock_p = s3; s3->getclock_p = s3;
break;
default:
return NULL;
}
return s3; return s3;
} }
static void *s3_9fx_init(const device_t *info) static int s3_bahamas64_available(void)
{ {
s3_t *s3 = s3_trio64_init(info, L"roms/video/s3/s3_764.bin"); return rom_present(ROM_PARADISE_BAHAMAS64);
return s3;
} }
static void *s3_phoenix_trio64_init(const device_t *info) static int s3_phoenix_vision864_available(void)
{ {
s3_t *s3 = s3_trio64_init(info, L"roms/video/s3/86c764x1.bin"); return rom_present(ROM_PHOENIX_VISION864);
if (device_get_config_int("memory") == 1)
s3->svga.vram_max = 1 << 20; /*Phoenix BIOS does not expect VRAM to be mirrored*/
return s3;
} }
static void *s3_phoenix_trio64_onboard_init(const device_t *info) static int s3_phoenix_trio32_available(void)
{ {
s3_t *s3 = s3_trio64_init(info, NULL); return rom_present(ROM_PHOENIX_TRIO32);
if (device_get_config_int("memory") == 1)
s3->svga.vram_max = 1 << 20; /*Phoenix BIOS does not expect VRAM to be mirrored*/
return s3;
}
static void *s3_diamond_stealth64_init(const device_t *info)
{
s3_t *s3 = s3_trio64_init(info, L"roms/video/s3/stealt64.bin");
if (device_get_config_int("memory") == 1)
s3->svga.vram_max = 1 << 20; /*Phoenix BIOS does not expect VRAM to be mirrored*/
return s3;
} }
static int s3_9fx_available(void) static int s3_9fx_available(void)
{ {
return rom_present(L"roms/video/s3/s3_764.bin"); return rom_present(ROM_NUMBER9_9FX);
} }
static int s3_phoenix_trio64_available(void) static int s3_phoenix_trio64_available(void)
{ {
return rom_present(L"roms/video/s3/86c764x1.bin"); return rom_present(ROM_PHOENIX_TRIO64);
} }
static int s3_diamond_stealth64_available(void) static int s3_diamond_stealth64_available(void)
{ {
return rom_present(L"roms/video/s3/stealt64.bin"); return rom_present(ROM_DIAMOND_STEALTH64);
} }
static void s3_close(void *p) static void s3_close(void *p)
@@ -3067,8 +3080,8 @@ const device_t s3_bahamas64_vlb_device =
{ {
"Paradise Bahamas 64 (S3 Vision864) VLB", "Paradise Bahamas 64 (S3 Vision864) VLB",
DEVICE_VLB, DEVICE_VLB,
0, S3_PARADISE_BAHAMAS64,
s3_bahamas64_init, s3_init,
s3_close, s3_close,
NULL, NULL,
s3_bahamas64_available, s3_bahamas64_available,
@@ -3081,8 +3094,8 @@ const device_t s3_bahamas64_pci_device =
{ {
"Paradise Bahamas 64 (S3 Vision864) PCI", "Paradise Bahamas 64 (S3 Vision864) PCI",
DEVICE_PCI, DEVICE_PCI,
0, S3_PARADISE_BAHAMAS64,
s3_bahamas64_init, s3_init,
s3_close, s3_close,
NULL, NULL,
s3_bahamas64_available, s3_bahamas64_available,
@@ -3095,8 +3108,8 @@ const device_t s3_9fx_vlb_device =
{ {
"Number 9 9FX (S3 Trio64) VLB", "Number 9 9FX (S3 Trio64) VLB",
DEVICE_VLB, DEVICE_VLB,
0, S3_NUMBER9_9FX,
s3_9fx_init, s3_init,
s3_close, s3_close,
NULL, NULL,
s3_9fx_available, s3_9fx_available,
@@ -3109,8 +3122,8 @@ const device_t s3_9fx_pci_device =
{ {
"Number 9 9FX (S3 Trio64) PCI", "Number 9 9FX (S3 Trio64) PCI",
DEVICE_PCI, DEVICE_PCI,
0, S3_NUMBER9_9FX,
s3_9fx_init, s3_init,
s3_close, s3_close,
NULL, NULL,
s3_9fx_available, s3_9fx_available,
@@ -3123,8 +3136,8 @@ const device_t s3_phoenix_trio32_vlb_device =
{ {
"Phoenix S3 Trio32 VLB", "Phoenix S3 Trio32 VLB",
DEVICE_VLB, DEVICE_VLB,
0, S3_PHOENIX_TRIO32,
s3_phoenix_trio32_init, s3_init,
s3_close, s3_close,
NULL, NULL,
s3_phoenix_trio32_available, s3_phoenix_trio32_available,
@@ -3137,8 +3150,8 @@ const device_t s3_phoenix_trio32_pci_device =
{ {
"Phoenix S3 Trio32 PCI", "Phoenix S3 Trio32 PCI",
DEVICE_PCI, DEVICE_PCI,
0, S3_PHOENIX_TRIO32,
s3_phoenix_trio32_init, s3_init,
s3_close, s3_close,
NULL, NULL,
s3_phoenix_trio32_available, s3_phoenix_trio32_available,
@@ -3151,8 +3164,8 @@ const device_t s3_phoenix_trio64_vlb_device =
{ {
"Phoenix S3 Trio64 VLB", "Phoenix S3 Trio64 VLB",
DEVICE_VLB, DEVICE_VLB,
0, S3_PHOENIX_TRIO64,
s3_phoenix_trio64_init, s3_init,
s3_close, s3_close,
NULL, NULL,
s3_phoenix_trio64_available, s3_phoenix_trio64_available,
@@ -3165,8 +3178,8 @@ const device_t s3_phoenix_trio64_onboard_pci_device =
{ {
"Phoenix S3 Trio64 On-Board PCI", "Phoenix S3 Trio64 On-Board PCI",
DEVICE_PCI, DEVICE_PCI,
1, S3_PHOENIX_TRIO64_ONBOARD,
s3_phoenix_trio64_onboard_init, s3_init,
s3_close, s3_close,
NULL, NULL,
NULL, NULL,
@@ -3179,8 +3192,8 @@ const device_t s3_phoenix_trio64_pci_device =
{ {
"Phoenix S3 Trio64 PCI", "Phoenix S3 Trio64 PCI",
DEVICE_PCI, DEVICE_PCI,
0, S3_PHOENIX_TRIO64,
s3_phoenix_trio64_init, s3_init,
s3_close, s3_close,
NULL, NULL,
s3_phoenix_trio64_available, s3_phoenix_trio64_available,
@@ -3193,8 +3206,8 @@ const device_t s3_phoenix_vision864_vlb_device =
{ {
"Phoenix S3 Vision864 VLB", "Phoenix S3 Vision864 VLB",
DEVICE_VLB, DEVICE_VLB,
0, S3_PHOENIX_VISION864,
s3_phoenix_vision864_init, s3_init,
s3_close, s3_close,
NULL, NULL,
s3_phoenix_vision864_available, s3_phoenix_vision864_available,
@@ -3207,8 +3220,8 @@ const device_t s3_phoenix_vision864_pci_device =
{ {
"Phoenix S3 Vision864 PCI", "Phoenix S3 Vision864 PCI",
DEVICE_PCI, DEVICE_PCI,
0, S3_PHOENIX_VISION864,
s3_phoenix_vision864_init, s3_init,
s3_close, s3_close,
NULL, NULL,
s3_phoenix_vision864_available, s3_phoenix_vision864_available,
@@ -3221,8 +3234,8 @@ const device_t s3_diamond_stealth64_vlb_device =
{ {
"S3 Trio64 (Diamond Stealth64 DRAM) VLB", "S3 Trio64 (Diamond Stealth64 DRAM) VLB",
DEVICE_PCI, DEVICE_PCI,
0, S3_DIAMOND_STEALTH64,
s3_diamond_stealth64_init, s3_init,
s3_close, s3_close,
NULL, NULL,
s3_diamond_stealth64_available, s3_diamond_stealth64_available,
@@ -3235,8 +3248,8 @@ const device_t s3_diamond_stealth64_pci_device =
{ {
"S3 Trio64 (Diamond Stealth64 DRAM) PCI", "S3 Trio64 (Diamond Stealth64 DRAM) PCI",
DEVICE_PCI, DEVICE_PCI,
0, S3_DIAMOND_STEALTH64,
s3_diamond_stealth64_init, s3_init,
s3_close, s3_close,
NULL, NULL,
s3_diamond_stealth64_available, s3_diamond_stealth64_available,