80486DX2-66/86Box-fork
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Added the version of PIIX3 for boards with I/O APIC that wires secondary IDE IRQ directly to legacy IRQ 15 instead of MIRQ0.

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This commit is contained in:
OBattler 2022-02-05 13:43:24 +01:00
parent d495665372
commit e9fbbf41d0
3 changed files with 22 additions and 4 deletions
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23
src/chipset/intel_piix.c
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@ -62,6 +62,7 @@ typedef struct _piix_ {
uint8_t cur_readout_reg, rev, uint8_t cur_readout_reg, rev,
type, func_shift, type, func_shift,
max_func, pci_slot, max_func, pci_slot,
no_mirq0, pad,
regs[4][256], regs[4][256],
readout_regs[256], board_config[2]; readout_regs[256], board_config[2];
uint16_t func0_id, nvr_io_base, uint16_t func0_id, nvr_io_base,
@ -1412,7 +1413,7 @@ piix_reset(void *p)
sff_set_irq_mode(dev->bm[0], 0, 0); sff_set_irq_mode(dev->bm[0], 0, 0);
sff_set_irq_mode(dev->bm[1], 0, 0); sff_set_irq_mode(dev->bm[1], 0, 0);
if (dev->type >= 4) { if (dev->no_mirq0 || (dev->type >= 4)) {
sff_set_irq_mode(dev->bm[0], 1, 0); sff_set_irq_mode(dev->bm[0], 1, 0);
sff_set_irq_mode(dev->bm[1], 1, 0); sff_set_irq_mode(dev->bm[1], 1, 0);
} else { } else {
@ -1458,7 +1459,8 @@ static void
dev->type = info->local & 0x0f; dev->type = info->local & 0x0f;
/* If (dev->type == 4) and (dev->rev & 0x08), then this is PIIX4E. */ /* If (dev->type == 4) and (dev->rev & 0x08), then this is PIIX4E. */
dev->rev = (info->local >> 4) & 0x0f; dev->rev = (info->local >> 4) & 0x0f;
dev->func_shift = info->local >> 8; dev->func_shift = (info->local >> 8) & 0x0f;
dev->no_mirq0 = (info->local >> 12) & 0x0f;
dev->func0_id = info->local >> 16; dev->func0_id = info->local >> 16;
dev->pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, piix_read, piix_write, dev); dev->pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, piix_read, piix_write, dev);
@ -1477,7 +1479,7 @@ static void
sff_set_irq_mode(dev->bm[0], 0, 0); sff_set_irq_mode(dev->bm[0], 0, 0);
sff_set_irq_mode(dev->bm[1], 0, 0); sff_set_irq_mode(dev->bm[1], 0, 0);
if (dev->type >= 4) { if (dev->no_mirq0 || (dev->type >= 4)) {
sff_set_irq_mode(dev->bm[0], 1, 0); sff_set_irq_mode(dev->bm[0], 1, 0);
sff_set_irq_mode(dev->bm[1], 1, 0); sff_set_irq_mode(dev->bm[1], 1, 0);
} else { } else {
@ -1643,6 +1645,21 @@ const device_t piix3_device =
NULL NULL
}; };
const device_t piix3_ioapic_device =
{
"Intel 82371SB (PIIX3) (Boards with I/O APIC)",
"piix3",
DEVICE_PCI,
0x70001403,
piix_init,
piix_close,
piix_reset,
{ NULL },
piix_speed_changed,
NULL,
NULL
};
const device_t piix4_device = const device_t piix4_device =
{ {
"Intel 82371AB/EB (PIIX4/PIIX4E)", "Intel 82371AB/EB (PIIX4/PIIX4E)",

1
src/include/86box/chipset.h
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@ -92,6 +92,7 @@ extern const device_t piix_device;
extern const device_t piix_old_device; extern const device_t piix_old_device;
extern const device_t piix_rev02_device; extern const device_t piix_rev02_device;
extern const device_t piix3_device; extern const device_t piix3_device;
extern const device_t piix3_ioapic_device;
extern const device_t piix4_device; extern const device_t piix4_device;
extern const device_t piix4e_device; extern const device_t piix4e_device;
extern const device_t slc90e66_device; extern const device_t slc90e66_device;

2
src/machine/m_at_socket8.c
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@ -281,7 +281,7 @@ machine_at_m6mi_init(const machine_t *model)
pci_register_slot(0x10, PCI_CARD_NORMAL, 3, 4, 1, 2); pci_register_slot(0x10, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 1, 2, 3); pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i440fx_device); device_add(&i440fx_device);
device_add(&piix3_device); device_add(&piix3_ioapic_device);
device_add(&keyboard_ps2_ami_pci_device); device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c935_device); device_add(&fdc37c935_device);
device_add(&intel_flash_bxt_device); device_add(&intel_flash_bxt_device);