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Added the Diamond Stealth 64 VRAM (S3 Vision964) and its Brooktree BT485 RAM DAC;

Browse Source 
Removed the ExpertColor S3 Vision868 card;
Rewritten the ICD2061 clock chip and moved the Diamond Stealth 32 back to the main branch as it's now fixed;
Fixed the Y offset of the 64x64 hardware cursor of the Cirrus Logic cards.
This commit is contained in:
OBattler
2018-09-30 20:29:44 +02:00
parent f1796e8d1d
commit eba4ca376e
11 changed files with 3101 additions and 2831 deletions
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419
src/video/vid_bt485_ramdac.c
View File

@@ -8,16 +8,14 @@
*
* Brooktree BT485 true colour RAMDAC emulation.
*
* Currently only a dummy stub for logging and passing output
* to the generic SVGA handler.
*
* Version: @(#)vid_bt485_ramdac.c 1.0.2 2017/11/04
* Version: @(#)vid_bt485_ramdac.c 1.0.4 2018/09/30
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Authors: Miran Grca, <mgrca8@gmail.com>
* TheCollector1995,
*
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016,2017 Miran Grca.
* Copyright 2016-2018 Miran Grca.
* Copyright 2018 TheCollector1995.
*/
#include <stdio.h>
#include <stdint.h>
@@ -30,163 +28,294 @@
#include "vid_bt485_ramdac.h"
int bt485_get_clock_divider(bt485_ramdac_t *ramdac)
void
bt485_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, bt485_ramdac_t *ramdac, svga_t *svga)
{
return 1; /* Will be implemented later. */
}
uint32_t o32;
uint8_t *cd;
void bt485_set_rs2(uint8_t rs2, bt485_ramdac_t *ramdac)
{
ramdac->rs2 = rs2 ? 1 : 0;
}
void bt485_set_rs3(uint8_t rs3, bt485_ramdac_t *ramdac)
{
ramdac->rs3 = rs3 ? 1 : 0;
}
void bt485_ramdac_out(uint16_t addr, uint8_t val, bt485_ramdac_t *ramdac, svga_t *svga)
{
// /*if (CS!=0xC000) */pclog("OUT RAMDAC %04X %02X %i %04X:%04X %i\n",addr,val,sdac_ramdac.magic_count,CS,pc, sdac_ramdac.rs2);
uint8_t reg = addr & 3;
reg |= (ramdac->rs2 ? 4 : 0);
reg |= (ramdac->rs3 ? 8 : 0);
pclog("BT485 RAMDAC: Writing %02X to register %02X\n", val, reg);
svga_out(addr, val, svga);
return;
switch (addr)
{
switch (addr) {
case 0x3C6:
if (val == 0xff)
{
ramdac->rs2 = 0;
ramdac->magic_count = 0;
if (rs2) {
if (rs3) { /*REG0E, Hardware Cursor Y-position*/
ramdac->hwc_y = (ramdac->hwc_y & 0x0f00) | val;
svga->hwcursor.y = ramdac->hwc_y - svga->hwcursor.ysize;
/* pclog("BT485 0E Y=%d\n", ramdac->hwc_y); */
break;
} else { /*REG06, Command Reg 0*/
ramdac->cr0 = val;
svga->ramdac_type = (val & 0x01) ? RAMDAC_8BIT : RAMDAC_6BIT;
break;
}
if (ramdac->magic_count < 4) break;
if (ramdac->magic_count == 4)
{
ramdac->command = val;
// pclog("RAMDAC command reg now %02X\n", val);
switch (val >> 4)
{
case 0x2: case 0x3: case 0xa: svga->bpp = 15; break;
case 0x4: case 0xe: svga->bpp = 24; break;
case 0x5: case 0x6: case 0xc: svga->bpp = 16; break;
case 0x7: svga->bpp = 32; break;
} else {
if (rs3) { /*REG0A*/
switch (ramdac->set_reg0a) {
case 0: /*Status, read-only*/
break;
case 0: case 1: default: svga->bpp = 8; break;
case 1: /*Command Reg 3*/
ramdac->cr3 = val;
svga->hwcursor.xsize = svga->hwcursor.ysize = (val & 4) ? 64 : 32;
svga->hwcursor.yoff = (svga->hwcursor.ysize == 32) ? 32 : 0;
svga->hwcursor.x = ramdac->hwc_x - svga->hwcursor.xsize;
svga->hwcursor.y = ramdac->hwc_y - svga->hwcursor.ysize;
if (svga->hwcursor.xsize == 64)
svga->dac_pos = (svga->dac_pos & 0x00ff) | ((val & 0x03) << 8);
svga_recalctimings(svga);
break;
}
break;
} else { /*REG02*/
svga_out(addr, val, svga);
break;
}
}
break;
case 0x3C7:
if (!rs2 && !rs3) { /*REG03*/
svga_out(addr, val, svga);
break;
} else if (rs2 && !rs3) { /*REG07, Cursor/Overscan Read Address*/
svga->dac_read = val;
svga->dac_pos = 0;
break;
} else if (!rs2 && rs3) { /*REG0B, Cursor Ram Data*/
if (svga->hwcursor.xsize == 64)
cd = (uint8_t *) ramdac->cursor64_data;
else
cd = (uint8_t *) ramdac->cursor32_data;
cd[svga->dac_pos] = val;
svga->dac_pos++;
if (svga->hwcursor.xsize == 32)
svga->dac_pos &= 0x00ff;
else
svga->dac_pos &= 0x03ff;
break;
} else { /*REG0F, Hardware Cursor Y-position*/
ramdac->hwc_y = (ramdac->hwc_y & 0x00ff) | ((val & 0x0f) << 8);
svga->hwcursor.y = ramdac->hwc_y - svga->hwcursor.ysize;
/* pclog("BT485 0F Y=%d\n", ramdac->hwc_y); */
break;
}
break;
case 0x3C8:
ramdac->set_reg0a = (ramdac->cr0 & 0x80) ? 1 : 0;
if (rs2) {
if (rs3) { /*REG0C, Hardware Cursor X-position*/
ramdac->hwc_x = (ramdac->hwc_x & 0x0f00) | val;
svga->hwcursor.x = ramdac->hwc_x - svga->hwcursor.xsize;
/* pclog("BT485 0C X=%d\n", ramdac->hwc_x); */
break;
}
else { /*REG04, Cursor/Overscan Write Address*/
svga->dac_write = val;
svga->dac_read = val - 1;
svga->dac_pos = 0;
break;
}
} else {
if (rs3) { /*REG08, Command Reg 1*/
ramdac->cr1 = val;
switch (val >> 5) {
case 0:
if ((svga->gdcreg[5] & 0x40) && (svga->crtc[0x3a] & 0x10))
svga->bpp = 32;
else
svga->bpp = 8;
break;
case 1:
if (ramdac->cr1 & 8)
svga->bpp = 16;
else
svga->bpp = 15;
break;
case 2:
svga->bpp = 8;
break;
case 3:
svga->bpp = 4;
break;
}
svga_recalctimings(svga);
}
//ramdac->magic_count = 0;
break;
case 0x3C7:
ramdac->magic_count = 0;
if (ramdac->rs2)
ramdac->rindex = val;
break;
case 0x3C8:
ramdac->magic_count = 0;
if (ramdac->rs2)
ramdac->windex = val;
break;
case 0x3C9:
ramdac->magic_count = 0;
if (ramdac->rs2)
{
if (!ramdac->reg_ff) ramdac->regs[ramdac->windex] = (ramdac->regs[ramdac->windex] & 0xff00) | val;
else ramdac->regs[ramdac->windex] = (ramdac->regs[ramdac->windex] & 0x00ff) | (val << 8);
ramdac->reg_ff = !ramdac->reg_ff;
// pclog("RAMDAC reg %02X now %04X\n", ramdac->windex, ramdac->regs[ramdac->windex]);
if (!ramdac->reg_ff) ramdac->windex++;
}
break;
}
else { /*REG00*/
svga_out(addr, val, svga);
}
uint8_t bt485_ramdac_in(uint16_t addr, bt485_ramdac_t *ramdac, svga_t *svga)
{
uint8_t temp;
// /*if (CS!=0xC000) */pclog("IN RAMDAC %04X %04X:%04X %i\n",addr,CS,pc, ramdac->rs2);
uint8_t reg = addr & 3;
reg |= (ramdac->rs2 ? 4 : 0);
reg |= (ramdac->rs3 ? 8 : 0);
pclog("BT485 RAMDAC: Reading register %02X\n", reg);
return svga_in(addr, svga);
switch (addr)
{
case 0x3C6:
ramdac->reg_ff = 0;
if (ramdac->magic_count < 5)
ramdac->magic_count++;
if (ramdac->magic_count == 4)
{
temp = 0x70; /*SDAC ID*/
ramdac->rs2 = 1;
}
if (ramdac->magic_count == 5)
{
temp = ramdac->command;
ramdac->magic_count = 0;
}
return temp;
case 0x3C7:
// if (ramdac->magic_count < 4)
// {
ramdac->magic_count=0;
// break;
// }
if (ramdac->rs2) return ramdac->rindex;
break;
case 0x3C8:
// if (ramdac->magic_count < 4)
// {
ramdac->magic_count=0;
// break;
// }
if (ramdac->rs2) return ramdac->windex;
}
}
break;
case 0x3C9:
// if (ramdac->magic_count < 4)
// {
ramdac->magic_count=0;
// break;
// }
if (ramdac->rs2)
{
if (!ramdac->reg_ff) temp = ramdac->regs[ramdac->rindex] & 0xff;
else temp = ramdac->regs[ramdac->rindex] >> 8;
ramdac->reg_ff = !ramdac->reg_ff;
if (!ramdac->reg_ff)
{
ramdac->rindex++;
ramdac->magic_count = 0;
if (rs2) {
if (rs3) { /*REG0D, Hardware Cursor X-position*/
ramdac->hwc_x = (ramdac->hwc_x & 0x00ff) | ((val & 0x0f) << 8);
svga->hwcursor.x = ramdac->hwc_x - svga->hwcursor.xsize;
/* pclog("BT485 0D X=%d\n", ramdac->hwc_x); */
break;
} else { /*REG05, Cursor/Overscan Data*/
svga->dac_status = 0;
svga->fullchange = changeframecount;
switch (svga->dac_pos) {
case 0:
svga->dac_r = val;
svga->dac_pos++;
break;
case 1:
svga->dac_g = val;
svga->dac_pos++;
break;
case 2:
ramdac->extpal[svga->dac_write].r = svga->dac_r;
ramdac->extpal[svga->dac_write].g = svga->dac_g;
ramdac->extpal[svga->dac_write].b = val;
if (svga->ramdac_type == RAMDAC_8BIT)
ramdac->extpallook[svga->dac_write & 3] = makecol32(ramdac->extpal[svga->dac_write].r & 0x3f, ramdac->extpal[svga->dac_write].g & 0x3f, ramdac->extpal[svga->dac_write].b & 0x3f);
else
ramdac->extpallook[svga->dac_write & 3] = makecol32(video_6to8[ramdac->extpal[svga->dac_write].r & 0x3f], video_6to8[ramdac->extpal[svga->dac_write].g & 0x3f], video_6to8[ramdac->extpal[svga->dac_write].b & 0x3f]);
if ((svga->crtc[0x33] & 0x40) && ((svga->dac_write & 3) == 0)) {
o32 = svga->overscan_color;
svga->overscan_color = ramdac->extpallook[0];
if (o32 != svga->overscan_color)
svga_recalctimings(svga);
}
return temp;
svga->dac_write = (svga->dac_write + 1) & 15;
svga->dac_pos = 0;
break;
}
break;
}
return svga_in(addr, svga);
}
else {
if (rs3) { /*REG09, Command Reg 2*/
ramdac->cr2 = val;
svga->hwcursor.ena = ramdac->cr2 & 0x03;
svga_recalctimings(svga);
break;
} else { /*REG01*/
svga_out(addr, val, svga);
break;
}
}
break;
}
return;
}
float bt485_getclock(int clock, void *p)
uint8_t
bt485_ramdac_in(uint16_t addr, int rs2, int rs3, bt485_ramdac_t *ramdac, svga_t *svga)
{
bt485_ramdac_t *ramdac = (bt485_ramdac_t *)p;
float t;
int m, n1, n2;
// pclog("SDAC_Getclock %i %04X\n", clock, ramdac->regs[clock]);
if (clock == 0) return 25175000.0;
if (clock == 1) return 28322000.0;
clock ^= 1; /*Clocks 2 and 3 seem to be reversed*/
m = (ramdac->regs[clock] & 0x7f) + 2;
n1 = ((ramdac->regs[clock] >> 8) & 0x1f) + 2;
n2 = ((ramdac->regs[clock] >> 13) & 0x07);
t = (14318184.0 * ((float)m / (float)n1)) / (float)(1 << n2);
// pclog("BT485 clock %i %i %i %f %04X %f %i\n", m, n1, n2, t, ramdac->regs[2], 14318184.0 * ((float)m / (float)n1), 1 << n2);
return t;
uint8_t temp = 0xff;
uint8_t *cd;
switch (addr) {
case 0x3C6:
if (rs2) {
if (rs3) /*REG0E, Hardware Cursor Y-position, write only*/
return 0xff;
else /*REG06, Command Reg 0*/
return ramdac->cr0;
} else {
if (rs3) { /*REG0A*/
switch (ramdac->set_reg0a) {
case 0: /*Status, read-only*/
return 0x0b; /*Bt485*/
case 1: /*Command Reg 3*/
if (ramdac->cr2 & 4) {
if (ramdac->cr3 & 2)
temp = 0xa9;
else
temp = 0xa8;
} else
temp = ramdac->cr3;
temp &= 0xfc;
if (svga->hwcursor.xsize == 64)
temp |= (svga->dac_pos >> 8) & 0x03;
return temp;
}
return 0xff;
} else /*REG02*/
return svga_in(addr, svga);
}
break;
case 0x3C7:
if (rs2) {
if (rs3) /*REG0F, Hardware Cursor Y-position, write only*/
return 0xff;
else /*REG07, Cursor/Overscan Read Address*/
return svga->dac_status;
} else {
if (rs3) { /*REG0B, Cursor Ram Data*/
if (svga->hwcursor.xsize == 64)
cd = (uint8_t *) ramdac->cursor64_data;
else
cd = (uint8_t *) ramdac->cursor32_data;
temp = cd[svga->dac_pos];
svga->dac_pos++;
if (svga->hwcursor.xsize == 32)
svga->dac_pos &= 0x00ff;
else
svga->dac_pos &= 0x03ff;
return temp;
} else /*REG03*/
return svga_in(addr, svga);
}
break;
case 0x3C8:
if (rs2) {
if (rs3) /*REG0C, Hardware Cursor X-position, write only*/
return 0xff;
else /*REG04, Cursor/Overscan Write Address*/
return svga->dac_write;
} else {
if (rs3) /*REG08, Command Reg 1*/
return ramdac->cr1;
else /*REG00*/
return svga_in(addr, svga);
}
break;
case 0x3C9:
if (rs2) {
if (rs3) /*REG0D, Hardware Cursor X-position, write only*/
return 0xff;
else { /*REG05, Cursor/Overscan Data*/
svga->dac_status = 0;
switch (svga->dac_pos) {
case 0:
svga->dac_pos++;
return ramdac->extpal[svga->dac_read].r & 0x3f;
case 1:
svga->dac_pos++;
return ramdac->extpal[svga->dac_read].g & 0x3f;
case 2:
svga->dac_pos=0;
svga->dac_read = (svga->dac_read + 1) & 15;
return ramdac->extpal[(svga->dac_read - 1) & 15].b & 0x3f;
}
return 0xff;
}
} else {
if (rs3) /*REG09, Command Reg 2*/
return ramdac->cr2;
else /*REG01*/
return svga_in(addr, svga);
}
break;
}
return temp;
}

22
src/video/vid_bt485_ramdac.h
View File

@@ -3,16 +3,18 @@
*/
typedef struct bt485_ramdac_t
{
int magic_count;
uint8_t command;
int windex, rindex;
uint16_t regs[256];
int reg_ff;
int rs2;
int rs3;
PALETTE extpal;
uint32_t extpallook[256];
uint8_t cursor32_data[256];
uint8_t cursor64_data[1024];
int set_reg0a;
int hwc_y, hwc_x;
uint8_t cr0;
uint8_t cr1;
uint8_t cr2;
uint8_t cr3;
} bt485_ramdac_t;
void bt485_ramdac_out(uint16_t addr, uint8_t val, bt485_ramdac_t *ramdac, svga_t *svga);
uint8_t bt485_ramdac_in(uint16_t addr, bt485_ramdac_t *ramdac, svga_t *svga);
void bt485_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, bt485_ramdac_t *ramdac, svga_t *svga);
uint8_t bt485_ramdac_in(uint16_t addr, int rs2, int rs3, bt485_ramdac_t *ramdac, svga_t *svga);
float bt485_getclock(int clock, void *p);

3
src/video/vid_cl54xx.c
View File

@@ -9,7 +9,7 @@
* Emulation of select Cirrus Logic cards (CL-GD 5428,
* CL-GD 5429, CL-GD 5430, CL-GD 5434 and CL-GD 5436 are supported).
*
* Version: @(#)vid_cl_54xx.c 1.0.21 2018/09/19
* Version: @(#)vid_cl_54xx.c 1.0.22 2018/09/30
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Barry Rodewald,
@@ -308,6 +308,7 @@ gd54xx_out(uint16_t addr, uint8_t val, void *p)
svga_recalctimings(svga);
svga->hwcursor.ena = val & CIRRUS_CURSOR_SHOW;
svga->hwcursor.xsize = svga->hwcursor.ysize = (val & CIRRUS_CURSOR_LARGE) ? 64 : 32;
svga->hwcursor.yoff = (svga->hwcursor.ysize == 32) ? 32 : 0;
if (val & CIRRUS_CURSOR_LARGE)
svga->hwcursor.addr = (((gd54xx->vram_size<<20)-0x4000) + ((svga->seqregs[0x13] & 0x3c) * 256));
else

32
src/video/vid_et4000w32.c
View File

@@ -10,7 +10,7 @@
*
* Known bugs: Accelerator doesn't work in planar modes
*
* Version: @(#)vid_et4000w32.c 1.0.17 2018/09/19
* Version: @(#)vid_et4000w32.c 1.0.18 2018/09/30
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -35,15 +35,11 @@
#include "../plat.h"
#include "video.h"
#include "vid_svga.h"
#if defined(DEV_BRANCH) && defined(USE_STEALTH32)
#include "vid_icd2061.h"
#endif
#include "vid_stg_ramdac.h"
#if defined(DEV_BRANCH) && defined(USE_STEALTH32)
#define BIOS_ROM_PATH_DIAMOND L"roms/video/et4000w32/et4000w32.bin"
#endif
#define BIOS_ROM_PATH_CARDEX L"roms/video/et4000w32/cardex.vbi"
@@ -61,9 +57,7 @@
enum
{
ET4000W32_CARDEX = 0,
#if defined(DEV_BRANCH) && defined(USE_STEALTH32)
ET4000W32_DIAMOND
#endif
};
enum
@@ -88,9 +82,7 @@ typedef struct et4000w32p_t
svga_t svga;
stg_ramdac_t ramdac;
#if defined(DEV_BRANCH) && defined(USE_STEALTH32)
icd2061_t icd2061;
#endif
int index;
int pci;
@@ -196,12 +188,10 @@ void et4000w32p_out(uint16_t addr, uint8_t val, void *p)
switch (addr)
{
#if defined(DEV_BRANCH) && defined(USE_STEALTH32)
case 0x3c2:
if (et4000->type == ET4000W32_DIAMOND)
icd2061_write(&et4000->icd2061, (val >> 2) & 3);
break;
#endif
case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9:
stg_ramdac_out(addr, val, &et4000->ramdac, svga);
@@ -366,22 +356,12 @@ void et4000w32p_recalctimings(svga_t *svga)
if (svga->crtc[0x3F] & 0x01) svga->htotal += 256;
if (svga->attrregs[0x16] & 0x20) svga->hdisp <<= 1;
#if defined(DEV_BRANCH) && defined(USE_STEALTH32)
if (et4000->type == ET4000W32_DIAMOND)
{
switch ((svga->miscout >> 2) & 3)
{
case 0: case 1: break;
case 2: case 3: svga->clock = cpuclock / icd2061_getfreq(&et4000->icd2061, 2); break;
}
svga->clock = cpuclock / icd2061_getclock((svga->miscout >> 2) & 3, &et4000->icd2061);
}
else
{
#endif
svga->clock = cpuclock / stg_getclock((svga->miscout >> 2) & 3, &et4000->ramdac);
#if defined(DEV_BRANCH) && defined(USE_STEALTH32)
}
#endif
switch (svga->bpp)
{
@@ -1275,12 +1255,12 @@ void *et4000w32p_init(const device_t *info)
rom_init(&et4000->bios_rom, BIOS_ROM_PATH_CARDEX, 0xc0000, 0x8000, 0x7fff, 0,
MEM_MAPPING_EXTERNAL);
break;
#if defined(DEV_BRANCH) && defined(USE_STEALTH32)
case ET4000W32_DIAMOND:
rom_init(&et4000->bios_rom, BIOS_ROM_PATH_DIAMOND, 0xc0000, 0x8000, 0x7fff, 0,
MEM_MAPPING_EXTERNAL);
icd2061_init(&et4000->icd2061);
break;
#endif
}
et4000->pci = !!(info->flags & DEVICE_PCI);
if (info->flags & DEVICE_PCI)
@@ -1316,12 +1296,10 @@ void *et4000w32p_init(const device_t *info)
return et4000;
}
#if defined(DEV_BRANCH) && defined(USE_STEALTH32)
int et4000w32p_available(void)
{
return rom_present(BIOS_ROM_PATH_DIAMOND);
}
#endif
int et4000w32p_cardex_available(void)
{
@@ -1398,7 +1376,6 @@ const device_t et4000w32p_cardex_pci_device =
et4000w32p_config
};
#if defined(DEV_BRANCH) && defined(USE_STEALTH32)
const device_t et4000w32p_vlb_device =
{
"Tseng Labs ET4000/w32p VLB (Diamond)",
@@ -1420,4 +1397,3 @@ const device_t et4000w32p_pci_device =
et4000w32p_force_redraw,
et4000w32p_config
};
#endif

2
src/video/vid_et4000w32.h
View File

@@ -1,7 +1,5 @@
#if defined(DEV_BRANCH) && defined(USE_STEALTH32)
extern const device_t et4000w32p_vlb_device;
extern const device_t et4000w32p_pci_device;
#endif
extern const device_t et4000w32p_cardex_vlb_device;
extern const device_t et4000w32p_cardex_pci_device;

123
src/video/vid_icd2061.c
View File

@@ -10,71 +10,106 @@
*
* Used by ET4000w32/p (Diamond Stealth 32)
*
* Version: @(#)vid_icd2061.c 1.0.2 2017/11/04
* Version: @(#)vid_icd2061.c 1.0.3 2018/09/30
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016,2017 Miran Grca.
* Copyright 2016-2018 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../mem.h"
#include "video.h"
#include "vid_svga.h"
#include "vid_icd2061.h"
void icd2061_write(icd2061_t *icd2061, int val)
void
icd2061_write(icd2061_t *icd2061, int val)
{
int q, p, m, a;
if ((val & 1) && !(icd2061->state & 1))
{
if (!icd2061->status)
{
if (val & 2)
icd2061->unlock++;
else
{
if (icd2061->unlock >= 5)
{
icd2061->status = 1;
icd2061->pos = 0;
}
else
icd2061->unlock = 0;
int /*od, */nd, oc, nc;
int a/*, i*/, qa, q, pa, p, m;
#if 0
od = (icd2061->state & 2) >> 1; /* Old data. */
#endif
nd = (val & 2) >> 1; /* Old data. */
oc = icd2061->state & 1; /* Old clock. */
nc = val & 1; /* New clock. */
icd2061->state = val;
if (nc && !oc) { /* Low-to-high transition of CLK. */
if (!icd2061->unlocked) {
if (nd) { /* DATA high. */
icd2061->count++;
/* pclog("Low-to-high transition of CLK with DATA high, %i total\n", icd2061->count); */
} else { /* DATA low. */
if (icd2061->count >= 5) {
icd2061->unlocked = 1;
icd2061->bit_count = icd2061->data = 0;
/* pclog("ICD2061 unlocked\n"); */
} else {
icd2061->count = 0;
/* pclog("ICD2061 locked\n"); */
}
}
else if (val & 1)
{
icd2061->data = (icd2061->data >> 1) | (((val & 2) ? 1 : 0) << 24);
icd2061->pos++;
if (icd2061->pos == 26)
{
a = (icd2061->data >> 21) & 0x7;
if (!(a & 4))
{
q = (icd2061->data & 0x7f) - 2;
m = 1 << ((icd2061->data >> 7) & 0x7);
p = ((icd2061->data >> 10) & 0x7f) - 3;
} else if (nc) {
icd2061->data |= (nd << icd2061->bit_count);
icd2061->bit_count++;
if (icd2061->bit_count == 26) {
icd2061->data >>= 1;
/* pclog("26 bits received, data = %08X\n", icd2061->data); */
a = ((icd2061->data >> 21) & 0x07); /* A */
if (a < 3) {
#if 0
i = ((icd2061->data >> 17) & 0x0f); /* I */
#endif
pa = ((icd2061->data >> 10) & 0x7f); /* P' */
m = ((icd2061->data >> 7) & 0x07); /* M */
qa = (icd2061->data & 0x7f); /* Q' */
p = pa + 3; /* P */
m = 1 << m;
q = qa + 2; /* Q */
if (icd2061->ctrl & (1 << a))
p <<= 1;
icd2061->freq[a] = ((double)p / (double)q) * 2.0 * 14318184.0 / (double)m;
}
else if (a == 6)
{
icd2061->freq[a] = ((float)p / (float)q) * 2.0 * 14318184.0 / (float)m;
/* pclog("P = %02X, M = %01X, Q = %02X, freq[%i] = %f\n", p, m, q, a, icd2061->freq[a]); */
} else if (a == 6) {
icd2061->ctrl = val;
/* pclog("ctrl = %02X\n", icd2061->ctrl); */
}
icd2061->unlock = icd2061->data = 0;
icd2061->status = 0;
icd2061->count = icd2061->bit_count = icd2061->data = 0;
}
}
}
icd2061->state = val;
}
double icd2061_getfreq(icd2061_t *icd2061, int i)
void
icd2061_init(icd2061_t *icd2061)
{
return icd2061->freq[i];
icd2061->freq[0] = 25175000.0;
icd2061->freq[1] = 28322000.0;
icd2061->freq[2] = 28322000.0;
}
float
icd2061_getclock(int clock, void *p)
{
icd2061_t *icd2061 = (icd2061_t *) p;
if (clock > 2)
clock = 2;
return icd2061->freq[clock];
}

36
src/video/vid_icd2061.h
View File

@@ -1,17 +1,31 @@
/* Copyright holders: Sarah Walker
see COPYING for more details
*/
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* ICD2061 clock generator emulation header.
*
* Used by ET4000w32/p (Diamond Stealth 32)
*
* Version: @(#)vid_icd2061.h 1.0.0 2018/09/30
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2018 Miran Grca.
*/
typedef struct icd2061_t
{
int state;
int status;
int pos;
int unlock;
uint32_t data;
svga_t svga;
float freq[3];
double freq[4];
uint32_t ctrl;
int count, bit_count;
int unlocked, state;
uint32_t data, ctrl;
} icd2061_t;
void icd2061_write(icd2061_t *icd2061, int val);
double icd2061_getfreq(icd2061_t *icd2061, int i);
void icd2061_init(icd2061_t *icd2061);
float icd2061_getclock(int clock, void *p);

299
src/video/vid_s3.c
View File

@@ -8,7 +8,7 @@
*
* S3 emulation.
*
* Version: @(#)vid_s3.c 1.0.18 2018/09/22
* Version: @(#)vid_s3.c 1.0.18 2018/09/30
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -33,38 +33,40 @@
#include "vid_svga.h"
#include "vid_svga_render.h"
#include "vid_sdac_ramdac.h"
#include "vid_bt485_ramdac.h"
#include "vid_icd2061.h"
#define ROM_PARADISE_BAHAMAS64 L"roms/video/s3/bahamas64.bin"
#define ROM_PHOENIX_VISION864 L"roms/video/s3/86c864p.bin"
#define ROM_EXPERTCOLOR_DSV3868P_CF55 L"roms/video/s3/1-DSV3868.BIN"
#define ROM_DIAMOND_STEALTH64_964 L"roms/video/s3/964_107u.rom"
#define ROM_PHOENIX_TRIO32 L"roms/video/s3/86c732p.bin"
#define ROM_NUMBER9_9FX L"roms/video/s3/s3_764.bin"
#define ROM_PHOENIX_TRIO64 L"roms/video/s3/86c764x1.bin"
#define ROM_DIAMOND_STEALTH64 L"roms/video/s3/stealt64.bin"
#define ROM_DIAMOND_STEALTH64_764 L"roms/video/s3/stealt64.bin"
enum
{
S3_EXPERTCOLOR_DSV3868P_CF55,
S3_NUMBER9_9FX,
S3_PARADISE_BAHAMAS64,
S3_DIAMOND_STEALTH64_964,
S3_PHOENIX_TRIO32,
S3_PHOENIX_TRIO64,
S3_PHOENIX_TRIO64_ONBOARD,
S3_PHOENIX_VISION864,
S3_DIAMOND_STEALTH64
S3_DIAMOND_STEALTH64_764
};
enum
{
S3_VISION864,
S3_VISION868,
S3_VISION964,
S3_TRIO32,
S3_TRIO64
};
static video_timings_t timing_s3_stealth64 = {VIDEO_BUS, 2, 2, 4, 26, 26, 42};
static video_timings_t timing_s3_vision864 = {VIDEO_BUS, 4, 4, 5, 20, 20, 35};
static video_timings_t timing_s3_vision868 = {VIDEO_BUS, 2, 2, 4, 20, 20, 35};
static video_timings_t timing_s3_vision964 = {VIDEO_BUS, 2, 2, 4, 20, 20, 35};
static video_timings_t timing_s3_trio32 = {VIDEO_BUS, 4, 3, 5, 26, 26, 42};
static video_timings_t timing_s3_trio64 = {VIDEO_BUS, 3, 2, 4, 25, 25, 40};
@@ -116,6 +118,8 @@ typedef struct s3_t
svga_t svga;
sdac_ramdac_t ramdac;
bt485_ramdac_t bt485_ramdac;
icd2061_t icd2061;
uint8_t bank;
uint8_t ma_ext;
@@ -130,6 +134,8 @@ typedef struct s3_t
int packed_mmio;
int p86c911_compat;
uint32_t linear_base, linear_size;
uint8_t pci_regs[256];
@@ -1007,6 +1013,13 @@ void s3_out(uint16_t addr, uint8_t val, void *p)
switch (addr)
{
case 0x3c2:
if (s3->chip == S3_VISION964) {
if (((val >> 2) & 3) != 3)
icd2061_write(&s3->icd2061, (val >> 2) & 3);
}
break;
case 0x3c5:
if (svga->seqaddr >= 0x10 && svga->seqaddr < 0x20)
{
@@ -1030,6 +1043,17 @@ void s3_out(uint16_t addr, uint8_t val, void *p)
case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9:
if (s3->chip == S3_TRIO32 || s3->chip == S3_TRIO64)
svga_out(addr, val, svga);
else if (s3->chip == S3_VISION964)
{
if (svga->crtc[0x55] == 3)
bt485_ramdac_out(addr, 1, 1, val, &s3->bt485_ramdac, svga);
else if (svga->crtc[0x55] == 2)
bt485_ramdac_out(addr, 0, 1, val, &s3->bt485_ramdac, svga);
else if ((svga->crtc[0x55] == 1) || (svga->crtc[0x43] & 2))
bt485_ramdac_out(addr, 1, 0, val, &s3->bt485_ramdac, svga);
else
bt485_ramdac_out(addr, 0, 0, val, &s3->bt485_ramdac, svga);
}
else
{
if ((svga->crtc[0x55] & 1) || (svga->crtc[0x43] & 2))
@@ -1104,12 +1128,18 @@ void s3_out(uint16_t addr, uint8_t val, void *p)
break;
case 0x45:
if (s3->chip == S3_VISION964)
break;
svga->hwcursor.ena = val & 1;
break;
case 0x48:
if (s3->chip == S3_VISION964)
break;
svga->hwcursor.x = ((svga->crtc[0x46] << 8) | svga->crtc[0x47]) & 0x7ff;
/* pclog("X=%d\n", svga->hwcursor.x); */
if (svga->bpp == 32) svga->hwcursor.x >>= 1;
svga->hwcursor.y = ((svga->crtc[0x48] << 8) | svga->crtc[0x49]) & 0x7ff;
/* pclog("Y=%d\n", svga->hwcursor.y); */
svga->hwcursor.xoff = svga->crtc[0x4e] & 63;
svga->hwcursor.yoff = svga->crtc[0x4f] & 63;
svga->hwcursor.addr = ((((svga->crtc[0x4c] << 8) | svga->crtc[0x4d]) & 0xfff) * 1024) + (svga->hwcursor.yoff * 16);
@@ -1153,8 +1183,15 @@ void s3_out(uint16_t addr, uint8_t val, void *p)
s3_updatemapping(s3);
break;
case 0x42:
if (s3->chip == S3_VISION964) {
if (((svga->miscout >> 2) & 3) == 3)
icd2061_write(&s3->icd2061, svga->crtc[0x42] & 0x0f);
}
break;
case 0x67:
if (s3->chip == S3_TRIO32 || s3->chip == S3_TRIO64 || s3->chip == S3_VISION868)
if (s3->chip == S3_TRIO32 || s3->chip == S3_TRIO64)
{
switch (val >> 4)
{
@@ -1203,9 +1240,23 @@ uint8_t s3_in(uint16_t addr, void *p)
case 0x3c6: case 0x3c7: case 0x3c8: case 0x3c9:
if (s3->chip == S3_TRIO32 || s3->chip == S3_TRIO64)
return svga_in(addr, svga);
if (s3->chip == S3_VISION964)
{
if (svga->crtc[0x55] == 3)
return bt485_ramdac_in(addr, 1, 1, &s3->bt485_ramdac, svga);
else if (svga->crtc[0x55] == 2)
return bt485_ramdac_in(addr, 0, 1, &s3->bt485_ramdac, svga);
else if ((svga->crtc[0x55] == 1) || (svga->crtc[0x43] & 2))
return bt485_ramdac_in(addr, 1, 0, &s3->bt485_ramdac, svga);
return bt485_ramdac_in(addr, 0, 0, &s3->bt485_ramdac, svga);
}
else
{
if ((svga->crtc[0x55] & 1) || (svga->crtc[0x43] & 2))
return sdac_ramdac_in(addr, 1, &s3->ramdac, svga);
return sdac_ramdac_in(addr, 0, &s3->ramdac, svga);
}
break;
case 0x3d4:
return svga->crtcreg;
@@ -1215,11 +1266,7 @@ uint8_t s3_in(uint16_t addr, void *p)
case 0x2d: return 0x88; /*Extended chip ID*/
case 0x2e: return s3->id_ext; /*New chip ID*/
case 0x2f: return 0; /*Revision level*/
case 0x30:
if (s3->chip == S3_VISION868)
return 0xe1; /*Vision868 hardwires it to E1h*/
else
return s3->id; /*Chip ID*/
case 0x30: return s3->id; /*Chip ID*/
case 0x31: return (svga->crtc[0x31] & 0xcf) | ((s3->ma_ext & 3) << 4);
case 0x35: return (svga->crtc[0x35] & 0xf0) | (s3->bank & 0xf);
case 0x45: s3->hwc_col_stack_pos = 0; break;
@@ -1252,8 +1299,19 @@ void s3_recalctimings(svga_t *svga)
if (svga->crtc[0x51] & 0x30) svga->rowoffset += (svga->crtc[0x51] & 0x30) << 4;
else if (svga->crtc[0x43] & 0x04) svga->rowoffset += 0x100;
if (!svga->rowoffset) svga->rowoffset = 256;
if (s3->chip == S3_VISION964) {
svga->interlace = s3->bt485_ramdac.cr2 & 0x08;
if (s3->bt485_ramdac.cr3 & 0x08)
svga->hdisp *= 2; /* x2 clock multiplier */
if (((svga->miscout >> 2) & 3) == 3)
svga->clock = cpuclock / s3->getclock(svga->crtc[0x42] & 0x0f, s3->getclock_p);
else
svga->clock = cpuclock / s3->getclock((svga->miscout >> 2) & 3, s3->getclock_p);
} else {
svga->interlace = svga->crtc[0x42] & 0x20;
svga->clock = cpuclock / s3->getclock((svga->miscout >> 2) & 3, s3->getclock_p);
}
switch (svga->crtc[0x67] >> 4)
{
@@ -1272,10 +1330,12 @@ void s3_recalctimings(svga_t *svga)
break;
case 15:
svga->render = svga_render_15bpp_highres;
if (s3->chip != S3_VISION964)
svga->hdisp /= 2;
break;
case 16:
svga->render = svga_render_16bpp_highres;
if (s3->chip != S3_VISION964)
svga->hdisp /= 2;
break;
case 24:
@@ -1284,10 +1344,8 @@ void s3_recalctimings(svga_t *svga)
break;
case 32:
svga->render = svga_render_32bpp_highres;
if (s3->chip != S3_TRIO32 && s3->chip != S3_TRIO64 && s3->chip != S3_VISION868)
if ((s3->chip != S3_TRIO32) && (s3->chip != S3_TRIO64) && (s3->chip != S3_VISION964))
svga->hdisp /= 4;
if (s3->chip == S3_VISION868)
svga->hdisp /= 2;
break;
}
}
@@ -1382,16 +1440,8 @@ void s3_updatemapping(s3_t *s3)
/* Old MMIO. */
mem_mapping_disable(&svga->mapping);
mem_mapping_enable(&s3->mmio_mapping);
/* New MMIO. */
if ((svga->crtc[0x53] & 0x08) && (s3->chip == S3_VISION868))
mem_mapping_set_addr(&s3->new_mmio_mapping, s3->linear_base + 0x1000000, 0x10000);
else
mem_mapping_disable(&s3->new_mmio_mapping);
} else {
} else
mem_mapping_disable(&s3->mmio_mapping);
mem_mapping_disable(&s3->new_mmio_mapping);
}
}
static float s3_trio64_getclock(int clock, void *p)
@@ -2513,7 +2563,7 @@ void s3_hwcursor_draw(svga_t *svga, int displine)
int xx;
int offset = svga->hwcursor_latch.x - svga->hwcursor_latch.xoff;
int y_add, x_add;
uint32_t fg = 0, bg = 0;
uint32_t fg, bg;
y_add = (enable_overscan && !suppress_overscan) ? (overscan_y >> 1) : 0;
x_add = (enable_overscan && !suppress_overscan) ? 8 : 0;
@@ -2576,6 +2626,104 @@ void s3_hwcursor_draw(svga_t *svga, int displine)
svga->hwcursor_latch.addr += 16;
}
void s3_bt485_hwcursor_draw(svga_t *svga, int displine)
{
s3_t *s3 = (s3_t *)svga->p;
int x, xx, comb, b0, b1;
uint16_t dat[2];
int offset = svga->hwcursor_latch.x - svga->hwcursor_latch.xoff;
int y_add, x_add;
int pitch, bppl, mode, x_pos, y_pos;
uint32_t clr1, clr2, clr3, *p;
uint8_t *cd;
clr1 = s3->bt485_ramdac.extpallook[1];
clr2 = s3->bt485_ramdac.extpallook[2];
clr3 = s3->bt485_ramdac.extpallook[3];
y_add = (enable_overscan && !suppress_overscan) ? (overscan_y >> 1) : 0;
x_add = (enable_overscan && !suppress_overscan) ? 8 : 0;
/* The planes come in two parts, and each plane is 1bpp,
so a 32x32 cursor has 4 bytes per line, and a 64x64
cursor has 8 bytes per line. */
pitch = (svga->hwcursor_latch.xsize >> 3); /* Bytes per line. */
/* A 32x32 cursor has 128 bytes per line, and a 64x64
cursor has 512 bytes per line. */
bppl = (pitch * svga->hwcursor_latch.ysize); /* Bytes per plane. */
mode = s3->bt485_ramdac.cr2 & 0x03;
if (svga->interlace && svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += pitch;
if (svga->hwcursor_latch.xsize == 64)
cd = (uint8_t *) s3->bt485_ramdac.cursor64_data;
else
cd = (uint8_t *) s3->bt485_ramdac.cursor32_data;
for (x = 0; x < svga->hwcursor_latch.xsize; x += 16) {
dat[0] = (cd[svga->hwcursor_latch.addr] << 8) |
cd[svga->hwcursor_latch.addr + 1];
dat[1] = (cd[svga->hwcursor_latch.addr + bppl] << 8) |
cd[svga->hwcursor_latch.addr + bppl + 1];
for (xx = 0; xx < 16; xx++) {
b0 = (dat[0] >> (15 - xx)) & 1;
b1 = (dat[1] >> (15 - xx)) & 1;
comb = (b0 | (b1 << 1));
y_pos = displine + y_add;
x_pos = offset + 32 + x_add;
p = ((uint32_t *)buffer32->line[y_pos]);
if (offset >= svga->hwcursor_latch.x) {
switch (mode) {
case 1: /* Three Color */
switch (comb) {
case 1:
p[x_pos] = clr1;
break;
case 2:
p[x_pos] = clr2;
break;
case 3:
p[x_pos] = clr3;
break;
}
break;
case 2: /* PM/Windows */
switch (comb) {
case 0:
p[x_pos] = clr1;
break;
case 1:
p[x_pos] = clr2;
break;
case 3:
p[x_pos] ^= 0xffffff;
break;
}
break;
case 3: /* X-Windows */
switch (comb) {
case 2:
p[x_pos] = clr1;
break;
case 3:
p[x_pos] = clr2;
break;
}
break;
}
}
offset++;
}
svga->hwcursor_latch.addr += 2;
}
if (svga->interlace && !svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += pitch;
}
static void s3_io_remove(s3_t *s3)
{
@@ -2761,10 +2909,10 @@ static void *s3_init(const device_t *info)
chip = S3_VISION864;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision864);
break;
case S3_EXPERTCOLOR_DSV3868P_CF55:
bios_fn = ROM_EXPERTCOLOR_DSV3868P_CF55;
chip = S3_VISION868;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision868);
case S3_DIAMOND_STEALTH64_964:
bios_fn = ROM_DIAMOND_STEALTH64_964;
chip = S3_VISION964;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision964);
break;
case S3_PHOENIX_TRIO32:
bios_fn = ROM_PHOENIX_TRIO32;
@@ -2781,8 +2929,8 @@ static void *s3_init(const device_t *info)
chip = S3_TRIO64;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64);
break;
case S3_DIAMOND_STEALTH64:
bios_fn = ROM_DIAMOND_STEALTH64;
case S3_DIAMOND_STEALTH64_764:
bios_fn = ROM_DIAMOND_STEALTH64_764;
chip = S3_TRIO64;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_stealth64);
break;
@@ -2798,6 +2946,7 @@ static void *s3_init(const device_t *info)
memset(s3, 0, sizeof(s3_t));
vram = device_get_config_int("memory");
if (vram)
vram_size = vram << 20;
else
@@ -2828,6 +2977,13 @@ static void *s3_init(const device_t *info)
mem_mapping_disable(&s3->mmio_mapping);
mem_mapping_disable(&s3->new_mmio_mapping);
if (chip == S3_VISION964)
svga_init(&s3->svga, s3, vram_size,
s3_recalctimings,
s3_in, s3_out,
s3_bt485_hwcursor_draw,
NULL);
else
svga_init(&s3->svga, s3, vram_size,
s3_recalctimings,
s3_in, s3_out,
@@ -2907,16 +3063,16 @@ static void *s3_init(const device_t *info)
sdac_init(&s3->ramdac);
break;
case S3_EXPERTCOLOR_DSV3868P_CF55:
case S3_DIAMOND_STEALTH64_964:
svga->decode_mask = (8 << 20) - 1;
s3->id = 0xe1; /*Vision868*/
s3->id_ext = 0x90;
s3->id_ext_pci = 0x80;
s3->id = 0xd1; /*Vision964P*/
s3->id_ext = 0xd1;
s3->id_ext_pci = 0xd1;
s3->packed_mmio = 1;
s3->getclock = sdac_getclock;
s3->getclock_p = &s3->ramdac;
sdac_init(&s3->ramdac);
icd2061_init(&s3->icd2061);
s3->getclock = icd2061_getclock;
s3->getclock_p = &s3->icd2061;
break;
case S3_PHOENIX_TRIO32:
@@ -2932,7 +3088,7 @@ static void *s3_init(const device_t *info)
case S3_PHOENIX_TRIO64:
case S3_PHOENIX_TRIO64_ONBOARD:
case S3_DIAMOND_STEALTH64:
case S3_DIAMOND_STEALTH64_764:
if (device_get_config_int("memory") == 1)
s3->svga.vram_max = 1 << 20; /* Phoenix BIOS does not expect VRAM to be mirrored. */
/* Fall over. */
@@ -2964,9 +3120,9 @@ static int s3_phoenix_vision864_available(void)
return rom_present(ROM_PHOENIX_VISION864);
}
static int s3_expertcolor_dsv3868p_cf55_available(void)
static int s3_diamond_stealth64_964_available(void)
{
return rom_present(ROM_EXPERTCOLOR_DSV3868P_CF55);
return rom_present(ROM_DIAMOND_STEALTH64_964);
}
static int s3_phoenix_trio32_available(void)
@@ -2984,9 +3140,9 @@ static int s3_phoenix_trio64_available(void)
return rom_present(ROM_PHOENIX_TRIO64);
}
static int s3_diamond_stealth64_available(void)
static int s3_diamond_stealth64_764_available(void)
{
return rom_present(ROM_DIAMOND_STEALTH64);
return rom_present(ROM_DIAMOND_STEALTH64_764);
}
static void s3_close(void *p)
@@ -3110,33 +3266,6 @@ static const device_config_t s3_config[] =
}
};
static const device_config_t s3_expertcolor_config[] =
{
{
"memory", "Memory size", CONFIG_SELECTION, "", 4,
{
{
"1 MB", 1
},
{
"2 MB", 2
},
{
"4 MB", 4
},
{
"8 MB", 8
},
{
""
}
}
},
{
"", "", -1
}
};
const device_t s3_bahamas64_vlb_device =
{
"Paradise Bahamas 64 (S3 Vision864) VLB",
@@ -3165,32 +3294,32 @@ const device_t s3_bahamas64_pci_device =
s3_config
};
const device_t s3_expertcolor_vlb_device =
const device_t s3_diamond_stealth64_964_vlb_device =
{
"ExpertColor DSV3868P CF55 (S3 Vision868) VLB",
"S3 Vision964 (Diamond Stealth64 VRAM) VLB",
DEVICE_VLB,
S3_EXPERTCOLOR_DSV3868P_CF55,
S3_DIAMOND_STEALTH64_964,
s3_init,
s3_close,
NULL,
s3_expertcolor_dsv3868p_cf55_available,
s3_diamond_stealth64_964_available,
s3_speed_changed,
s3_force_redraw,
s3_expertcolor_config
s3_config
};
const device_t s3_expertcolor_pci_device =
const device_t s3_diamond_stealth64_964_pci_device =
{
"ExpertColor DSV3868P CF55 (S3 Vision868) PCI",
"S3 Vision964 (Diamond Stealth64 VRAM) PCI",
DEVICE_PCI,
S3_EXPERTCOLOR_DSV3868P_CF55,
S3_DIAMOND_STEALTH64_964,
s3_init,
s3_close,
NULL,
s3_expertcolor_dsv3868p_cf55_available,
s3_diamond_stealth64_964_available,
s3_speed_changed,
s3_force_redraw,
s3_expertcolor_config
s3_config
};
const device_t s3_9fx_vlb_device =
@@ -3323,11 +3452,11 @@ const device_t s3_diamond_stealth64_vlb_device =
{
"S3 Trio64 (Diamond Stealth64 DRAM) VLB",
DEVICE_PCI,
S3_DIAMOND_STEALTH64,
S3_DIAMOND_STEALTH64_764,
s3_init,
s3_close,
NULL,
s3_diamond_stealth64_available,
s3_diamond_stealth64_764_available,
s3_speed_changed,
s3_force_redraw,
s3_config
@@ -3337,11 +3466,11 @@ const device_t s3_diamond_stealth64_pci_device =
{
"S3 Trio64 (Diamond Stealth64 DRAM) PCI",
DEVICE_PCI,
S3_DIAMOND_STEALTH64,
S3_DIAMOND_STEALTH64_764,
s3_init,
s3_close,
NULL,
s3_diamond_stealth64_available,
s3_diamond_stealth64_764_available,
s3_speed_changed,
s3_force_redraw,
s3_config

4
src/video/vid_s3.h
View File

@@ -19,8 +19,6 @@
const device_t s3_bahamas64_vlb_device;
const device_t s3_bahamas64_pci_device;
const device_t s3_expertcolor_vlb_device;
const device_t s3_expertcolor_pci_device;
const device_t s3_9fx_vlb_device;
const device_t s3_9fx_pci_device;
const device_t s3_phoenix_trio32_vlb_device;
@@ -32,4 +30,6 @@ const device_t s3_phoenix_vision864_pci_device;
const device_t s3_phoenix_vision864_vlb_device;
const device_t s3_diamond_stealth64_pci_device;
const device_t s3_diamond_stealth64_vlb_device;
const device_t s3_diamond_stealth64_964_pci_device;
const device_t s3_diamond_stealth64_964_vlb_device;
/* const device_t s3_miro_vision964_device; */

10
src/video/vid_table.c
View File

@@ -8,7 +8,7 @@
*
* Define all known video cards.
*
* Version: @(#)vid_table.c 1.0.38 2018/09/19
* Version: @(#)vid_table.c 1.0.39 2018/09/30
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
@@ -124,13 +124,11 @@ video_cards[] = {
{"[PCI] Cirrus Logic CL-GD 5440", "cl_gd5440_pci", &gd5440_pci_device },
{"[PCI] Cirrus Logic CL-GD 5446", "cl_gd5446_pci", &gd5446_pci_device },
{"[PCI] Cirrus Logic CL-GD 5480", "cl_gd5480_pci", &gd5480_pci_device },
#if defined(DEV_BRANCH) && defined(USE_STEALTH32)
{"[PCI] Diamond Stealth 32 (Tseng ET4000/w32p)", "stealth32_pci", &et4000w32p_pci_device },
#endif
{"[PCI] Diamond Stealth 3D 2000 (S3 ViRGE)", "stealth3d_2000_pci", &s3_virge_pci_device },
{"[PCI] Diamond Stealth 3D 3000 (S3 ViRGE/VX)", "stealth3d_3000_pci", &s3_virge_988_pci_device },
{"[PCI] Diamond Stealth 64 DRAM (S3 Trio64)", "stealth64d_pci", &s3_diamond_stealth64_pci_device },
{"[PCI] ExpertColor DSV3868P CF55 (S3 Vision868)", "expertcolor_pci", &s3_expertcolor_pci_device },
{"[PCI] Diamond Stealth 64 VRAM (S3 Vision964)", "stealth64v_pci", &s3_diamond_stealth64_964_pci_device },
{"[PCI] Number Nine 9FX (S3 Trio64)", "n9_9fx_pci", &s3_9fx_pci_device },
{"[PCI] Paradise Bahamas 64 (S3 Vision864)", "bahamas64_pci", &s3_bahamas64_pci_device },
{"[PCI] Phoenix S3 Vision864", "px_vision864_pci", &s3_phoenix_vision864_pci_device },
@@ -145,15 +143,13 @@ video_cards[] = {
{"[VLB] Cirrus Logic CL-GD 5428", "cl_gd5428_vlb", &gd5428_vlb_device },
{"[VLB] Cirrus Logic CL-GD 5429", "cl_gd5429_vlb", &gd5429_vlb_device },
{"[VLB] Cirrus Logic CL-GD 5434", "cl_gd5434_vlb", &gd5434_vlb_device },
#if defined(DEV_BRANCH) && defined(USE_STEALTH32)
{"[VLB] Diamond Stealth 32 (Tseng ET4000/w32p)", "stealth32_vlb", &et4000w32p_vlb_device },
#endif
{"[VLB] Diamond SpeedStar PRO (CL-GD 5426)", "cl_gd5426_vlb", &gd5426_vlb_device },
{"[VLB] Diamond SpeedStar PRO SE (CL-GD 5430)", "cl_gd5430_vlb", &gd5430_vlb_device },
{"[VLB] Diamond Stealth 3D 2000 (S3 ViRGE)", "stealth3d_2000_vlb", &s3_virge_vlb_device },
{"[VLB] Diamond Stealth 3D 3000 (S3 ViRGE/VX)", "stealth3d_3000_vlb", &s3_virge_988_vlb_device },
{"[VLB] Diamond Stealth 64 DRAM (S3 Trio64)", "stealth64d_vlb", &s3_diamond_stealth64_vlb_device },
{"[VLB] ExpertColor DSV3868P CF55 (S3 Vision868)", "expertcolor_vlb", &s3_expertcolor_vlb_device },
{"[VLB] Diamond Stealth 64 VRAM (S3 Vision964)", "stealth64v_vlb", &s3_diamond_stealth64_964_vlb_device },
{"[VLB] Number Nine 9FX (S3 Trio64)", "n9_9fx_vlb", &s3_9fx_vlb_device },
{"[VLB] Paradise Bahamas 64 (S3 Vision864)", "bahamas64_vlb", &s3_bahamas64_vlb_device },
{"[VLB] Phoenix S3 Vision864", "px_vision864_vlb", &s3_phoenix_vision864_vlb_device },

16
src/win/Makefile.mingw
View File

@@ -8,7 +8,7 @@
#
# Makefile for Win32 (MinGW32) environment.
#
# Version: @(#)Makefile.mingw 1.0.126 2018/09/15
# Version: @(#)Makefile.mingw 1.0.127 2018/09/30
#
# Authors: Miran Grca, <mgrca8@gmail.com>
# Fred N. van Kempen, <decwiz@yahoo.com>
@@ -62,9 +62,6 @@ ifeq ($(DEV_BUILD), y)
ifndef PS2M70T4
PS2M70T4 := y
endif
ifndef STEALTH32
STEALTH32 := y
endif
ifndef VNC
VNC := y
endif
@@ -105,9 +102,6 @@ else
ifndef PS2M70T4
PS2M70T4 := n
endif
ifndef STEALTH32
STEALTH32 := n
endif
ifndef VGAWONDER
VGAWONDER := n
endif
@@ -389,11 +383,6 @@ ifeq ($(PS2M70T4), y)
OPTS += -DUSE_PS2M70T4
endif
ifeq ($(STEALTH32), y)
OPTS += -DUSE_STEALTH32
DEVBROBJ += vid_icd2061.o
endif
ifeq ($(VGAWONDER), y)
OPTS += -DUSE_VGAWONDER
endif
@@ -541,7 +530,8 @@ VIDOBJ := video.o \
vid_ati_eeprom.o \
vid_ati18800.o vid_ati28800.o \
vid_ati_mach64.o vid_ati68860_ramdac.o \
vid_ics2595.o \
vid_bt485_ramdac.o \
vid_icd2061.o vid_ics2595.o \
vid_cl54xx.o \
vid_et4000.o vid_sc1502x_ramdac.o \
vid_et4000w32.o vid_stg_ramdac.o \