From ed6193abc987aaec30bb0025f6e0af1aed19a9f2 Mon Sep 17 00:00:00 2001 From: Jasmine Iwanek Date: Sun, 21 Jul 2024 18:00:52 -0400 Subject: [PATCH] Named initializers for soclet 3's --- src/cpu/cpu_table.c | 332 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 312 insertions(+), 20 deletions(-) diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 6ae963c79..2ec9a3304 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -2543,8 +2543,40 @@ const cpu_family_t cpu_families[] = { .name = "Pentium OverDrive", .internal_name = "pentium_p24t", .cpus = (const CPU[]) { - {"63", CPU_P24T, fpus_internal, 62500000, 2.5, 5000, 0x1531, 0x1531, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2}, - {"83", CPU_P24T, fpus_internal, 83333333, 2.5, 5000, 0x1532, 0x1532, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10}, + { + .name = "63", + .cpu_type = CPU_P24T, + .fpus = fpus_internal, + .rspeed = 62500000, + .multi = 2.5, + .voltage = 5000, + .edx_reset = 0x1531, + .cpuid_model = 0x1531, + .cyrix_id = 0x0000, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 10, + .mem_write_cycles = 10, + .cache_read_cycles = 7, + .cache_write_cycles = 7, + .atclk_div = 15/2 + }, + { + .name = "83", + .cpu_type = CPU_P24T, + .fpus = fpus_internal, + .rspeed = 83333333, + .multi = 2.5, + .voltage = 5000, + .edx_reset = 0x1532, + .cpuid_model = 0x1532, + .cyrix_id = 0x0000, + .cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 8, + .cache_write_cycles = 8, + .atclk_div = 10 + }, { .name = "", 0 } } }, @@ -2846,10 +2878,74 @@ const cpu_family_t cpu_families[] = { .name = "Am486DX4", .internal_name = "am486dx4", .cpus = (const CPU[]) { - {"75", CPU_Am486DX, fpus_internal, 75000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"90", CPU_Am486DX, fpus_internal, 90000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"100", CPU_Am486DX, fpus_internal, 100000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"120", CPU_Am486DX, fpus_internal, 120000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, + { + .name = "75", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 9 + }, + { + .name = "90", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 90000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 + }, + { + .name = "100", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 + }, + { + .name = "120", + .cpu_type = CPU_Am486DX, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x432, + .cpuid_model = 0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 15 + }, { .name = "", 0 } } }, @@ -2859,8 +2955,40 @@ const cpu_family_t cpu_families[] = { .name = "Am486DX2 (Enhanced)", .internal_name = "am486dx2_slenh", .cpus = (const CPU[]) { - {"66", CPU_ENH_Am486DX, fpus_internal, 66666666, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"80", CPU_ENH_Am486DX, fpus_internal, 80000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + { + .name = "66", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 66666666, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x435, + .cpuid_model = 0x435, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 8 + }, + { + .name = "80", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2, + .voltage = 5000, + .edx_reset = 0x435, + .cpuid_model = 0x435, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 10 + }, { .name = "", 0 } } }, @@ -2870,9 +2998,57 @@ const cpu_family_t cpu_families[] = { .name = "Am486DX4 (Enhanced)", .internal_name = "am486dx4_slenh", .cpus = (const CPU[]) { - {"75", CPU_ENH_Am486DX, fpus_internal, 75000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"100", CPU_ENH_Am486DX, fpus_internal, 100000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"120", CPU_ENH_Am486DX, fpus_internal, 120000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, + { + .name = "75", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 75000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x482, + .cpuid_model = 0x482, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 12, + .mem_write_cycles = 12, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 9 + }, + { + .name = "100", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x482, + .cpuid_model = 0x482, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 + }, + { + .name = "120", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x482, + .cpuid_model = 0x482, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 15 + }, { .name = "", 0 } } }, @@ -2882,9 +3058,57 @@ const cpu_family_t cpu_families[] = { .name = "Am5x86", .internal_name = "am5x86", .cpus = (const CPU[]) { - {"133 (P75)", CPU_ENH_Am486DX, fpus_internal, 133333333, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, - {"150 (P75+)", CPU_ENH_Am486DX, fpus_internal, 150000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/ - {"160 (P90)", CPU_ENH_Am486DX, fpus_internal, 160000000, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ + { + .name = "133 (P75)", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 4.0, + .voltage = 5000, + .edx_reset = 0x4e0, + .cpuid_model = 0x4e0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 16 + }, + { /*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/ + .name = "150 (P75+)", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 150000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x482, + .cpuid_model = 0x482, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 28, + .mem_write_cycles = 28, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 20 + }, + { /*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ + .name = "160 (P90)", + .cpu_type = CPU_ENH_Am486DX, + .fpus = fpus_internal, + .rspeed = 160000000, + .multi = 4.0, + .voltage = 5000, + .edx_reset = 0x4e0, + .cpuid_model = 0x4e0, + .cyrix_id = 0, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 28, + .mem_write_cycles = 28, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 20 + }, { .name = "", 0 } } }, @@ -3057,8 +3281,12 @@ const cpu_family_t cpu_families[] = { .name = "Cx486DX4", .internal_name = "cx486dx4", .cpus = (const CPU[]) { - {"75", CPU_Cx486DX, fpus_internal, 75000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"100", CPU_Cx486DX, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + { + .name = "75", .cpu_type = CPU_Cx486DX, .fpus = fpus_internal, .rspeed = 75000000, .multi = 3.0, .voltage = 5000, .edx_reset = 0x480, .cpuid_model = 0, .cyrix_id = 0x361f, .cpu_flags = CPU_SUPPORTS_DYNAREC, .mem_read_cycles = 12,.mem_write_cycles = 12, .cache_read_cycles = 9, .cache_write_cycles = 9, .atclk_div = 9 + }, + { + .name = "100", .cpu_type = CPU_Cx486DX, .fpus = fpus_internal, .rspeed = 100000000, .multi = 3.0, .voltage = 5000, .edx_reset = 0x480, .cpuid_model = 0, .cyrix_id = 0x361f, .cpu_flags = CPU_SUPPORTS_DYNAREC, .mem_read_cycles = 15,.mem_write_cycles = 15, .cache_read_cycles = 9, .cache_write_cycles = 9, .atclk_div = 12 + }, { .name = "", 0 } } }, @@ -3068,10 +3296,74 @@ const cpu_family_t cpu_families[] = { .name = "Cx5x86", .internal_name = "cx5x86", .cpus = (const CPU[]) { - {"80", CPU_Cx5x86, fpus_internal, 80000000, 2.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, /*If we're including the Pentium 50, might as well include this*/ - {"100", CPU_Cx5x86, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"120", CPU_Cx5x86, fpus_internal, 120000000, 3.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, - {"133", CPU_Cx5x86, fpus_internal, 133333333, 4.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, + { /*If we're including the Pentium 50, might as well include this*/ + .name = "80", + .cpu_type = CPU_Cx5x86, + .fpus = fpus_internal, + .rspeed = 80000000, + .multi = 2.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x002f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 14, + .mem_write_cycles = 14, + .cache_read_cycles = 6, + .cache_write_cycles = 6, + .atclk_div = 10 + }, + { + .name = "100", + .cpu_type = CPU_Cx5x86, + .fpus = fpus_internal, + .rspeed = 100000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x002f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 15, + .mem_write_cycles = 15, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 12 + }, + { + .name = "120", + .cpu_type = CPU_Cx5x86, + .fpus = fpus_internal, + .rspeed = 120000000, + .multi = 3.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x002f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 21, + .mem_write_cycles = 21, + .cache_read_cycles = 9, + .cache_write_cycles = 9, + .atclk_div = 15 + }, + { + .name = "133", + .cpu_type = CPU_Cx5x86, + .fpus = fpus_internal, + .rspeed = 133333333, + .multi = 4.0, + .voltage = 5000, + .edx_reset = 0x480, + .cpuid_model = 0, + .cyrix_id = 0x002f, + .cpu_flags = CPU_SUPPORTS_DYNAREC, + .mem_read_cycles = 24, + .mem_write_cycles = 24, + .cache_read_cycles = 12, + .cache_write_cycles = 12, + .atclk_div = 16 + }, { .name = "", 0 } } },