Merge pull request #1200 from tiseno100/master
Properly implemented the ACC 2046/2168
This commit is contained in:
@@ -6,19 +6,23 @@
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*
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*
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* This file is part of the 86Box distribution.
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* This file is part of the 86Box distribution.
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*
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*
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* Implementation of the ACC 2168 chipset
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* Implementation of the ACC 2046/2168 chipset
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*
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*
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*
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*
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*
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Tiseno100
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*
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*
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* Copyright 2019 Sarah Walker.
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* Copyright 2019 Sarah Walker.
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* Copyright 2021 Tiseno100.
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*/
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*/
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#include <stdio.h>
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdlib.h>
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#include <string.h>
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#include <string.h>
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#include <wchar.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/86box.h>
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#include "cpu.h"
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/timer.h>
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@@ -28,84 +32,174 @@
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#include <86box/port_92.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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#include <86box/chipset.h>
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#define enabled_shadow (MEM_READ_INTERNAL | ((dev->regs[0x02] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL))
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#define ENABLED_SHADOW (MEM_READ_INTERNAL | ((dev->regs[0x02] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL))
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#define disabled_shadow (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
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#define DISABLED_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
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#define SHADOW_ADDR ((i <= 1) ? (0xc0000 + (i << 15)) : (0xd0000 + ((i - 2) << 16)))
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#define SHADOW_SIZE ((i <= 1) ? 0x8000 : 0x10000)
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#define SHADOW_RECALC ((dev->regs[0x02] & (1 << i)) ? ENABLED_SHADOW : DISABLED_SHADOW)
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#ifdef ENABLE_ACC2168_LOG
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int acc2168_do_log = ENABLE_ACC2168_LOG;
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static void
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acc2168_log(const char *fmt, ...)
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{
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va_list ap;
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if (acc2168_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define acc2168_log(fmt, ...)
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#endif
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typedef struct acc2168_t
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typedef struct acc2168_t
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{
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{
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int reg_idx;
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uint8_t reg_idx, regs[256];
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uint8_t regs[256];
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} acc2168_t;
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} acc2168_t;
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static void
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static void
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acc2168_shadow_recalc(acc2168_t *dev)
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acc2168_shadow_recalc(acc2168_t *dev)
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{
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{
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mem_set_mem_state_both(0xc0000, 0x8000, ((dev->regs[0x02] & 0x01) ? enabled_shadow : disabled_shadow));
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for (uint32_t i = 0; i < 5; i++)
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mem_set_mem_state_both(0xc8000, 0x8000, ((dev->regs[0x02] & 0x02) ? enabled_shadow : disabled_shadow));
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mem_set_mem_state_both(SHADOW_ADDR, SHADOW_SIZE, SHADOW_RECALC);
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mem_set_mem_state_both(0xd0000, 0x10000, ((dev->regs[0x02] & 0x04) ? enabled_shadow : disabled_shadow));
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mem_set_mem_state_both(0xe0000, 0x10000, ((dev->regs[0x02] & 0x08) ? enabled_shadow : disabled_shadow));
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mem_set_mem_state_both(0xf0000, 0x10000, ((dev->regs[0x02] & 0x10) ? enabled_shadow : disabled_shadow));
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}
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}
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static void
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static void
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acc2168_write(uint16_t addr, uint8_t val, void *p)
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acc2168_write(uint16_t addr, uint8_t val, void *p)
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{
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{
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acc2168_t *dev = (acc2168_t *)p;
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acc2168_t *dev = (acc2168_t *)p;
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if (!(addr & 1))
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switch (addr)
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dev->reg_idx = val;
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{
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else {
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case 0xf2:
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dev->regs[dev->reg_idx] = val;
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dev->reg_idx = val;
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break;
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case 0xf3:
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acc2168_log("ACC2168: dev->regs[%02x] = %02x\n", dev->reg_idx, val);
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switch (dev->reg_idx)
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{
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case 0x00:
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dev->regs[dev->reg_idx] = val;
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break;
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switch (dev->reg_idx) {
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case 0x01:
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case 0x02:
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dev->regs[dev->reg_idx] = val & 0xd3;
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acc2168_shadow_recalc(dev);
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cpu_update_waitstates();
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break;
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break;
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}
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case 0x02:
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dev->regs[dev->reg_idx] = val & 0x7f;
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acc2168_shadow_recalc(dev);
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break;
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case 0x03:
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dev->regs[dev->reg_idx] = val & 0x1f;
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break;
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case 0x04:
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dev->regs[dev->reg_idx] = val;
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cpu_cache_ext_enabled = !!(val & 0x01);
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cpu_update_waitstates();
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break;
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case 0x05:
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dev->regs[dev->reg_idx] = val & 0xf3;
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break;
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case 0x06:
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case 0x07:
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dev->regs[dev->reg_idx] = val & 0x1f;
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break;
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case 0x08:
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dev->regs[dev->reg_idx] = val & 0x0f;
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break;
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case 0x09:
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dev->regs[dev->reg_idx] = val & 0x03;
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break;
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case 0x0a:
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case 0x0b:
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case 0x0c:
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case 0x0d:
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case 0x0e:
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case 0x0f:
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case 0x10:
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case 0x11:
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dev->regs[dev->reg_idx] = val;
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break;
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case 0x12:
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dev->regs[dev->reg_idx] = val & 0xbb;
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break;
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case 0x18:
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dev->regs[dev->reg_idx] = val & 0x77;
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break;
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case 0x19:
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dev->regs[dev->reg_idx] = val & 0xfb;
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break;
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case 0x1a:
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dev->regs[dev->reg_idx] = val;
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cpu_cache_int_enabled = !(val & 0x40);
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cpu_update_waitstates();
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break;
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case 0x1b:
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dev->regs[dev->reg_idx] = val & 0xef;
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break;
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default: /* ACC 2168 has way more registers which we haven't documented */
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dev->regs[dev->reg_idx] = val;
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break;
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}
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break;
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}
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}
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}
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}
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static uint8_t
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static uint8_t
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acc2168_read(uint16_t addr, void *p)
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acc2168_read(uint16_t addr, void *p)
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{
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{
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acc2168_t *dev = (acc2168_t *)p;
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acc2168_t *dev = (acc2168_t *)p;
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if (!(addr & 1))
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return (addr == 0xf3) ? dev->regs[dev->reg_idx] : dev->reg_idx;
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return dev->reg_idx;
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return dev->regs[dev->reg_idx];
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}
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}
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static void
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static void
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acc2168_close(void *priv)
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acc2168_close(void *priv)
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{
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{
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acc2168_t *dev = (acc2168_t *) priv;
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acc2168_t *dev = (acc2168_t *)priv;
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free(dev);
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free(dev);
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}
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}
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static void *
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static void *
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acc2168_init(const device_t *info)
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acc2168_init(const device_t *info)
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{
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{
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acc2168_t *dev = (acc2168_t *)malloc(sizeof(acc2168_t));
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acc2168_t *dev = (acc2168_t *)malloc(sizeof(acc2168_t));
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memset(dev, 0, sizeof(acc2168_t));
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memset(dev, 0, sizeof(acc2168_t));
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io_sethandler(0x00f2, 0x0002,
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acc2168_read, NULL, NULL, acc2168_write, NULL, NULL, dev);
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device_add(&port_92_inv_device);
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device_add(&port_92_device);
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io_sethandler(0x00f2, 0x0002, acc2168_read, NULL, NULL, acc2168_write, NULL, NULL, dev);
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return dev;
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return dev;
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}
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}
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const device_t acc2168_device = {
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const device_t acc2168_device = {
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"ACC 2168",
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"ACC 2046/2168",
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0,
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0,
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0,
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0,
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acc2168_init, acc2168_close, NULL,
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acc2168_init,
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{ NULL }, NULL, NULL,
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acc2168_close,
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NULL
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NULL,
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};
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{NULL},
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NULL,
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NULL,
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NULL};
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