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Fixes and small rework on the ALi M1489

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This commit is contained in:
Panagiotis
2020-12-27 18:51:08 +02:00
committed by GitHub
parent 57d0c7d5ae
commit f190c8ec7d
1 changed files with 218 additions and 229 deletions
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165
src/chipset/ali1489.c
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@@ -28,19 +28,19 @@
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/pci.h>
#include <86box/dma.h>
#include <86box/smram.h>
#include <86box/apm.h>
#include <86box/hdc_ide.h>
#include <86box/hdc.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/chipset.h>
#define disabled_shadow (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
#define ENABLE_ALI1489_LOG 0
#define DEFINE_SHADOW_PROCEDURE (((dev->regs[0x14] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x14] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))
#define DISABLED_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
#ifdef ENABLE_ALI1489_LOG
int ali1489_do_log = ENABLE_ALI1489_LOG;
@@ -49,7 +49,8 @@ ali1489_log(const char *fmt, ...)
{
va_list ap;
if (ali1489_do_log) {
if (ali1489_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
@@ -63,6 +64,10 @@ typedef struct
{
uint8_t index, ide_index, ide_chip_id,
regs[256], pci_conf[256], ide_regs[256];
uint8_t pci_slot;
apm_t *apm;
port_92_t *port_92;
smram_t *smram;
} ali1489_t;
@@ -73,6 +78,7 @@ ali1489_defaults(void *priv)
ali1489_t *dev = (ali1489_t *)priv;
/* IDE registers */
dev->ide_regs[0x00] = 0x57;
dev->ide_regs[0x01] = 0x02;
dev->ide_regs[0x08] = 0xff;
dev->ide_regs[0x09] = 0x41;
@@ -104,36 +110,27 @@ ali1489_defaults(void *priv)
dev->regs[0x3c] = 0x03;
dev->regs[0x3d] = 0x01;
dev->regs[0x40] = 0x03;
}
static void ali1489_shadow_recalc(ali1489_t *dev)
{
uint32_t base, i;
for(i = 0; i < 8; i++){
base = 0xc0000 + (i << 14);
for (uint32_t i = 0; i < 8; i++)
{
if (dev->regs[0x13] & (1 << i))
mem_set_mem_state_both(base, 0x4000, ((dev->regs[0x14] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x14] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, DEFINE_SHADOW_PROCEDURE);
else
mem_set_mem_state_both(base, 0x4000, disabled_shadow);
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, DISABLED_SHADOW);
}
for(i = 0; i < 4; i++){
base = 0xe0000 + (i << 15);
for (uint32_t i = 0; i < 4; i++)
{
shadowbios = (dev->regs[0x14] & 0x10);
shadowbios_write = (dev->regs[0x14] & 0x20);
if (dev->regs[0x14] & (1 << i))
mem_set_mem_state_both(base, 0x8000, ((dev->regs[0x14] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x14] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xe0000 + (i << 15), 0x8000, DEFINE_SHADOW_PROCEDURE);
else
mem_set_mem_state_both(base, 0x8000, disabled_shadow);
mem_set_mem_state_both(0xe0000 + (i << 15), 0x8000, DISABLED_SHADOW);
}
flushmmucache();
@@ -143,28 +140,47 @@ static void ali1489_smram_recalc(ali1489_t *dev)
{
/* The datasheet documents SMM behavior quite terribly.
Everything were done according to the M1489 programming guide. */
switch(dev->regs[0x19] & 0x30) {
switch (dev->regs[0x19] & 0x30)
{
case 0:
smram_disable_all();
break;
case 1:
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, (dev->regs[0x19] & 0x08), !(dev->regs[0x19] & 0x08));
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, (dev->regs[0x19] & 0x08), 1);
break;
case 2:
smram_enable(dev->smram, 0xe0000, 0xe0000, 0x10000, (dev->regs[0x19] & 0x08), !(dev->regs[0x19] & 0x08));
if (dev->regs[0x14] == 0)
smram_enable(dev->smram, 0xe0000, 0xe0000, 0x10000, (dev->regs[0x19] & 0x08), 1);
break;
case 3:
smram_enable(dev->smram, 0x30000, 0xa0000, 0x20000, (dev->regs[0x19] & 0x08), !(dev->regs[0x19] & 0x08));
smram_enable(dev->smram, 0x30000, 0xa0000, 0x20000, (dev->regs[0x19] & 0x08), 1);
break;
}
}
static void
ali1489_ide_handler(ali1489_t *dev)
{
ide_set_base(0, 0x1f0);
ide_set_side(0, 0x3f6);
ide_pri_enable();
if (dev->ide_regs[0x35] & 0x01)
{
ide_set_base(1, 0x170);
ide_set_side(1, 0x376);
ide_sec_enable();
if (dev->ide_regs[0x35] & 0x04)
ide_sec_disable();
}
}
static void
ali1489_write(uint16_t addr, uint8_t val, void *priv)
{
ali1489_t *dev = (ali1489_t *)priv;
switch (addr) {
switch (addr)
{
case 0x22:
dev->index = val;
break;
@@ -174,7 +190,8 @@ ali1489_write(uint16_t addr, uint8_t val, void *priv)
if (dev->regs[0x03] == 0xc5) /* Check if the configuration registers are unlocked */
{
switch(dev->index){
switch (dev->index)
{
case 0x10: /* DRAM Configuration Register I */
case 0x11: /* DRAM Configuration Register II */
@@ -203,6 +220,7 @@ ali1489_write(uint16_t addr, uint8_t val, void *priv)
dev->regs[dev->index] = val;
cpu_cache_int_enabled = (val & 0x01);
cpu_cache_ext_enabled = (val & 0x02);
cpu_update_waitstates();
break;
case 0x17: /* Cache Control Register II */
@@ -258,6 +276,10 @@ ali1489_write(uint16_t addr, uint8_t val, void *priv)
break;
case 0x30: /* Power Management Unit Control Register */
dev->regs[dev->index] = val;
apm_set_do_smi(dev->apm, val & 0x1c);
break;
case 0x31: /* Mode Timer Monitoring Events Selection Register I */
case 0x32: /* Mode Timer Monitoring Events Selection Register II */
case 0x33: /* SMI Triggered Events Selection Register I */
@@ -267,8 +289,6 @@ ali1489_write(uint16_t addr, uint8_t val, void *priv)
case 0x35: /* SMI Status Register */
dev->regs[dev->index] = val;
if(dev->regs[dev->index] & 0x30)
smi_line = 1;
break;
case 0x36: /* IRQ Channel Group Selected Control Register I */
@@ -304,54 +324,38 @@ ali1489_write(uint16_t addr, uint8_t val, void *priv)
break;
case 0x42: /* PCI INTx Routing Table Mapping Register I */
if((val & 0x0f) != 0)
pci_set_irq(PCI_INTA, (val & 0x0f));
else
pci_set_irq(PCI_INTA, PCI_IRQ_DISABLED);
if(((val & 0x0f) << 4) != 0)
pci_set_irq(PCI_INTB, ((val & 0x0f) << 4));
else
pci_set_irq(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTA, ((val & 0x0f) != 0) ? (val & 0x0f) : PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, ((val & 0xf0) != 0) ? (val & 0xf0) : PCI_IRQ_DISABLED);
break;
case 0x43: /* PCI INTx Routing Table Mapping Register II */
if((val & 0x0f) != 0)
pci_set_irq(PCI_INTC, (val & 0x0f));
else
pci_set_irq(PCI_INTC, PCI_IRQ_DISABLED);
if(((val & 0x0f) << 4) != 0)
pci_set_irq(PCI_INTD, ((val & 0x0f) << 4));
else
pci_set_irq(PCI_INTD, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, ((val & 0x0f) != 0) ? (val & 0x0f) : PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, ((val & 0xf0) != 0) ? (val & 0xf0) : PCI_IRQ_DISABLED);
break;
case 0x44: /* PCI INTx Sensitivity Register */
dev->regs[dev->index] = val;
break;
}
if (dev->index != 0x03)
{
ali1489_log("M1489: dev->regs[%02x] = %02x\n", dev->index, val);
}
}
break;
}
}
static uint8_t
ali1489_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
ali1489_t *dev = (ali1489_t *)priv;
switch (addr) {
switch (addr)
{
case 0x23:
if (((dev->index == 0x20) || (dev->index >= 0xc0)) && cpu_iscyrix) /* Avoid conflict with Cyrix CPU registers */
@@ -363,7 +367,7 @@ ali1489_read(uint16_t addr, void *priv)
break;
}
ali1489_log("M1489: dev->regs[%02x] (%02x)\n", dev->index, ret);
return ret;
}
@@ -373,7 +377,7 @@ ali1489_pci_write(int func, int addr, uint8_t val, void *priv)
ali1489_t *dev = (ali1489_t *)priv;
ali1489_log("M1489-PCI: dev->regs[%02x] = %02x\n", addr, val);
ali1489_log("M1489-PCI: dev->pci_conf[%02x] = %02x\n", addr, val);
switch (addr)
{
@@ -387,7 +391,6 @@ switch (addr)
dev->pci_conf[0x07] &= ~(val & 0xfe);
break;
}
}
static uint8_t
@@ -397,7 +400,7 @@ ali1489_pci_read(int func, int addr, void *priv)
uint8_t ret = 0xff;
ret = dev->pci_conf[addr];
ali1489_log("M1489-PCI: dev->pci_conf[%02x] (%02x)\n", addr, ret);
return ret;
}
@@ -407,7 +410,8 @@ ali1489_ide_write(uint16_t addr, uint8_t val, void *priv)
ali1489_t *dev = (ali1489_t *)priv;
switch (addr) {
switch (addr)
{
case 0xf4: /* Usually it writes 30h here */
dev->ide_chip_id = val;
break;
@@ -417,28 +421,16 @@ ali1489_t *dev = (ali1489_t *) priv;
break;
case 0xfc:
ali1489_log("M1489-IDE: dev->regs[%02x] = %02x\n", dev->ide_index, val);
dev->ide_regs[dev->ide_index] = val;
if (dev->ide_regs[0x01] & 0x01) // Internal IDE Enabled
{
ali1489_log("M1489-IDE: dev->regs[%02x] = %02x\n", dev->ide_index, val);
ide_pri_disable();
ide_sec_disable();
if(dev->ide_regs[0x01] & 0x01){ /*The datasheet doesn't clearly explain the channel selection */
ide_pri_enable(); /*So we treat it according to the chipset programming manual. */
ide_set_base(0, 0x1f0);
ide_set_side(0, 0x3f6);
if(!(dev->ide_regs[0x35] & 0x41)){
ide_sec_enable();
ide_set_base(1, 0x170);
ide_set_side(1, 0x376);
ali1489_ide_handler(dev);
}
}
break;
}
}
static uint8_t
@@ -448,12 +440,14 @@ ali1489_ide_read(uint16_t addr, void *priv)
uint8_t ret = 0xff;
ali1489_t *dev = (ali1489_t *)priv;
switch (addr) {
switch (addr)
{
case 0xf4:
ret = dev->ide_chip_id;
break;
case 0xfc:
ret = dev->ide_regs[dev->ide_index];
ali1489_log("M1489-IDE: dev->regs[%02x] (%02x)\n", dev->ide_index, ret);
break;
}
@@ -466,16 +460,12 @@ ali1489_reset(void *priv)
ali1489_t *dev = (ali1489_t *)priv;
ide_pri_disable();
ide_sec_disable();
pci_set_irq(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq(PCI_INTD, PCI_IRQ_DISABLED);
ali1489_defaults(dev);
}
static void
@@ -487,7 +477,6 @@ ali1489_close(void *priv)
free(dev);
}
static void *
ali1489_init(const device_t *info)
{
@@ -512,11 +501,13 @@ ali1489_init(const device_t *info)
io_sethandler(0x0fc, 0x0001, ali1489_ide_read, NULL, NULL, ali1489_ide_write, NULL, NULL, dev);
/* Dummy M1489 PCI device */
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1489_pci_read, ali1489_pci_write, dev);
dev->pci_slot = pci_add_card(PCI_ADD_NORTHBRIDGE, ali1489_pci_read, ali1489_pci_write, dev);
ide_pri_disable();
ide_sec_disable();
dev->apm = device_add(&apm_pci_device);
device_add(&ide_pci_2ch_device);
dev->port_92 = device_add(&port_92_pci_device);
dev->smram = smram_add();
@@ -532,7 +523,6 @@ ali1489_init(const device_t *info)
return dev;
}
const device_t ali1489_device = {
"ALi M1489",
0,
@@ -543,5 +533,4 @@ const device_t ali1489_device = {
{NULL},
NULL,
NULL,
NULL
};
NULL};