80486DX2-66/86Box-fork
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Improved the SCO Xenix fix, fixes OS/2 booting, fixes #4762.

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This commit is contained in:
OBattler
2024-08-29 01:26:32 +02:00
parent 447374bd65
commit f19a5447be
6 changed files with 37 additions and 37 deletions
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3
src/cpu/386_dynarec.c
View File

@@ -937,8 +937,7 @@ exec386(int32_t cycs)
cpu_flush_pending++;
else if (cpu_flush_pending == 2) {
cpu_flush_pending = 0;
cr0 ^= 0x80000000;
flushmmucache();
flushmmucache_pc();
}
#ifndef USE_NEW_DYNAREC

18
src/cpu/x86_ops_mov_ctrl.h
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@@ -189,16 +189,15 @@ opMOV_CRx_r_a16(uint32_t fetchdat)
else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
if (is_p6 || cpu_use_dynarec)
flushmmucache();
else
else {
flushmmucache_nopc();
cpu_flush_pending = 1;
}
}
/* Make sure CPL = 0 when switching from real mode to protected mode. */
if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01))
cpu_state.seg_cs.access &= 0x9f;
if (!is_p6 && !cpu_use_dynarec && ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000))
cr0 = (cr0 & 0x80000000) | (cpu_state.regs[cpu_rm].l & 0x7fffffff);
else
cr0 = cpu_state.regs[cpu_rm].l;
cr0 = cpu_state.regs[cpu_rm].l;
if (cpu_16bitbus)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))
@@ -255,16 +254,15 @@ opMOV_CRx_r_a32(uint32_t fetchdat)
else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
if (is_p6 || cpu_use_dynarec)
flushmmucache();
else
else {
flushmmucache_nopc();
cpu_flush_pending = 1;
}
}
/* Make sure CPL = 0 when switching from real mode to protected mode. */
if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01))
cpu_state.seg_cs.access &= 0x9f;
if (!is_p6 && !cpu_use_dynarec && ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000))
cr0 = (cr0 & 0x80000000) | (cpu_state.regs[cpu_rm].l & 0x7fffffff);
else
cr0 = cpu_state.regs[cpu_rm].l;
cr0 = cpu_state.regs[cpu_rm].l;
if (cpu_16bitbus)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))

18
src/cpu/x86_ops_mov_ctrl_2386.h
View File

@@ -182,15 +182,14 @@ opMOV_CRx_r_a16(uint32_t fetchdat)
case 0:
if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x00000001)
flushmmucache();
else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000)
else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
flushmmucache_nopc();
cpu_flush_pending = 1;
}
/* Make sure CPL = 0 when switching from real mode to protected mode. */
if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01))
cpu_state.seg_cs.access &= 0x9f;
if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000)
cr0 = (cr0 & 0x80000000) | (cpu_state.regs[cpu_rm].l & 0x7fffffff);
else
cr0 = cpu_state.regs[cpu_rm].l;
cr0 = cpu_state.regs[cpu_rm].l;
if (cpu_16bitbus)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))
@@ -244,15 +243,14 @@ opMOV_CRx_r_a32(uint32_t fetchdat)
case 0:
if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x00000001)
flushmmucache();
else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000)
else if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000) {
flushmmucache_nopc();
cpu_flush_pending = 1;
}
/* Make sure CPL = 0 when switching from real mode to protected mode. */
if ((cpu_state.regs[cpu_rm].l & 0x01) && !(cr0 & 0x01))
cpu_state.seg_cs.access &= 0x9f;
if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000000)
cr0 = (cr0 & 0x80000000) | (cpu_state.regs[cpu_rm].l & 0x7fffffff);
else
cr0 = cpu_state.regs[cpu_rm].l;
cr0 = cpu_state.regs[cpu_rm].l;
if (cpu_16bitbus)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))

21
src/cpu/x86_ops_pmode.h
View File

@@ -431,21 +431,12 @@ op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
if (cpu_mod != 3)
SEG_CHECK_WRITE(cpu_state.ea_seg);
if (is386 && is32 && (cpu_mod == 3)) {
if (cpu_flush_pending) {
if (is486 || isibm486)
seteaw(cr0 ^ 0x80000000);
else if (is386 && !cpu_16bitbus)
seteaw((cr0 ^ 0x80000000) | /* 0x7FFFFF00 */ 0x7FFFFFE0);
else
seteaw((cr0 ^ 0x80000000) | 0x7FFFFFF0);
} else {
if (is486 || isibm486)
seteaw(cr0);
else if (is386 && !cpu_16bitbus)
seteaw(cr0 | /* 0x7FFFFF00 */ 0x7FFFFFE0);
else
seteaw(cr0 | 0x7FFFFFF0);
}
if (is486 || isibm486)
seteaw(cr0);
else if (is386 && !cpu_16bitbus)
seteaw(cr0 | /* 0x7FFFFF00 */ 0x7FFFFFE0);
else
seteaw(cr0 | 0x7FFFFFF0);
} else {
if (is486 || isibm486)
seteaw(msw);

1
src/include/86box/mem.h
View File

@@ -446,6 +446,7 @@ extern void mem_flush_write_page(uint32_t addr, uint32_t virt);
extern void mem_reset_page_blocks(void);
extern void flushmmucache(void);
extern void flushmmucache_pc(void);
extern void flushmmucache_nopc(void);
extern void mem_debug_check_addr(uint32_t addr, int write);

13
src/mem/mem.c
View File

@@ -225,6 +225,19 @@ flushmmucache(void)
#endif
}
void
flushmmucache_pc(void)
{
mmuflush++;
pccache = (uint32_t) 0xffffffff;
pccache2 = (uint8_t *) 0xffffffff;
#ifdef USE_DYNAREC
codegen_flush();
#endif
}
void
flushmmucache_nopc(void)
{