Named-initializers for 8088 CPU's
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@@ -76,14 +76,128 @@ const cpu_family_t cpu_families[] = {
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.name = "8088",
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.internal_name = "8088",
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.cpus = (const CPU[]) {
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{"4.77", CPU_8088, fpus_8088, 4772728, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
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{"7.16", CPU_8088, fpus_8088, 7159092, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
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{"8", CPU_8088, fpus_8088, 8000000, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
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// {"9.54", CPU_8088, fpus_8088, 9545456, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
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{"10", CPU_8088, fpus_8088, 10000000, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
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{"12", CPU_8088, fpus_8088, 12000000, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
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{"16", CPU_8088, fpus_8088, 16000000, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
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{"", 0}
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{
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.name = "4.77",
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.cpu_type = CPU_8088,
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.fpus = fpus_8088,
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.rspeed = 4772728,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 0,
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.mem_write_cycles = 0,
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.cache_read_cycles = 0,
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.cache_write_cycles = 0,
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.atclk_div = 1
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},
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{
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.name = "7.16",
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.cpu_type = CPU_8088,
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.fpus = fpus_8088,
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.rspeed = 7159092,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 0,
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.mem_write_cycles = 0,
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.cache_read_cycles = 0,
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.cache_write_cycles = 0,
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.atclk_div = 1
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},
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{
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.name = "8",
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.cpu_type = CPU_8088,
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.fpus = fpus_8088,
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.rspeed = 8000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 0,
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.mem_write_cycles = 0,
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.cache_read_cycles = 0,
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.cache_write_cycles = 0,
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.atclk_div = 1
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},
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#if 0
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{
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.name = "9.54",
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.cpu_type = CPU_8088,
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.fpus = fpus_8088,
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.rspeed = 9545456,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 0,
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.mem_write_cycles = 0,
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.cache_read_cycles = 0,
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.cache_write_cycles = 0,
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.atclk_div = 1
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},
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#endif
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{
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.name = "10",
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.cpu_type = CPU_8088,
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.fpus = fpus_8088,
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.rspeed = 10000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 0,
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.mem_write_cycles = 0,
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.cache_read_cycles = 0,
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.cache_write_cycles = 0,
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.atclk_div = 1
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},
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{
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.name = "12",
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.cpu_type = CPU_8088,
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.fpus = fpus_8088,
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.rspeed = 12000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 0,
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.mem_write_cycles = 0,
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.cache_read_cycles = 0,
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.cache_write_cycles = 0,
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.atclk_div = 1
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},
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{
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.name = "16",
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.cpu_type = CPU_8088,
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.fpus = fpus_8088,
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.rspeed = 16000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 0,
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.mem_write_cycles = 0,
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.cache_read_cycles = 0,
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.cache_write_cycles = 0,
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.atclk_div = 1
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},
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{ .name = "", 0 }
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}
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}, {
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.package = CPU_PKG_8088_EUROPC,
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@@ -91,10 +205,58 @@ const cpu_family_t cpu_families[] = {
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.name = "8088",
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.internal_name = "8088_europc",
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.cpus = (const CPU[]) {
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{"4.77", CPU_8088, fpus_8088, 4772728, 1, 5000, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1},
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{"7.16", CPU_8088, fpus_8088, 7159092, 1, 5000, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1},
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{"9.54", CPU_8088, fpus_8088, 9545456, 1, 5000, 0, 0, 0, 0, 0,0,0,0, 1},
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{"", 0}
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{
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.name = "4.77",
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.cpu_type = CPU_8088,
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.fpus = fpus_8088,
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.rspeed = 4772728,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = CPU_ALTERNATE_XTAL,
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.mem_read_cycles = 0,
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.mem_write_cycles = 0,
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.cache_read_cycles = 0,
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.cache_write_cycles = 0,
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.atclk_div = 1
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},
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{
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.name = "7.16",
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.cpu_type = CPU_8088,
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.fpus = fpus_8088,
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.rspeed = 7159092,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = CPU_ALTERNATE_XTAL,
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.mem_read_cycles = 0,
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.mem_write_cycles = 0,
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.cache_read_cycles = 0,
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.cache_write_cycles = 0,
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.atclk_div = 1
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},
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{
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.name = "9.54",
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.cpu_type = CPU_8088,
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.fpus = fpus_8088,
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.rspeed = 9545456,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 0,
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.mem_write_cycles = 0,
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.cache_read_cycles = 0,
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.cache_write_cycles = 0,
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.atclk_div = 1
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},
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{ .name = "", 0 }
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}
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}, {
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.package = CPU_PKG_8086,
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