80486DX2-66/86Box-fork
1
0
Fork 0
Code Issues Pull Requests Activity

Merge pull request #659 from 86Box/bugfix/mga_win9x_os2

Browse Source 
Ported the latest Win9x MGA fix from PCem.
This commit is contained in:
OBattler
2020-04-01 01:10:26 +02:00
committed by GitHub
parent 998cdc3bb5 77140b874a
commit fb42a3417d
1 changed files with 10 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/video/vid_mga.c
View File

@@ -1860,28 +1860,28 @@ mystique_accel_ctrl_write_l(uint32_t addr, uint32_t val, void *p)
case REG_SRC0: case REG_SRC0:
mystique->dwgreg.src[0] = val; mystique->dwgreg.src[0] = val;
if ((mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD) if (mystique->busy && (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD)
blit_iload_write(mystique, mystique->dwgreg.src[0], 32); blit_iload_write(mystique, mystique->dwgreg.src[0], 32);
break; break;
case REG_SRC1: case REG_SRC1:
mystique->dwgreg.src[1] = val; mystique->dwgreg.src[1] = val;
if ((mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD) if (mystique->busy && (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD)
blit_iload_write(mystique, mystique->dwgreg.src[1], 32); blit_iload_write(mystique, mystique->dwgreg.src[1], 32);
break; break;
case REG_SRC2: case REG_SRC2:
mystique->dwgreg.src[2] = val; mystique->dwgreg.src[2] = val;
if ((mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD) if (mystique->busy && (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD)
blit_iload_write(mystique, mystique->dwgreg.src[2], 32); blit_iload_write(mystique, mystique->dwgreg.src[2], 32);
break; break;
case REG_SRC3: case REG_SRC3:
mystique->dwgreg.src[3] = val; mystique->dwgreg.src[3] = val;
if ((mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD) if (mystique->busy && (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD)
blit_iload_write(mystique, mystique->dwgreg.src[3], 32); blit_iload_write(mystique, mystique->dwgreg.src[3], 32);
break; break;
case REG_DMAPAD: case REG_DMAPAD:
if ((mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD) if (mystique->busy && (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD)
blit_iload_write(mystique, mystique->dwgreg.src[0], 32); blit_iload_write(mystique, val, 32);
break; break;
case REG_AR0: case REG_AR0:
@@ -2249,10 +2249,9 @@ run_dma(mystique_t *mystique)
else else
reg_addr += 0x1c00; reg_addr += 0x1c00;
if ((reg_addr & 0x300) == 0x100 && reg_addr != REG_DMAPAD) if ((reg_addr & 0x300) == 0x100)
mystique->blitter_submit_dma_refcount++; mystique->blitter_submit_dma_refcount++;
if (reg_addr != REG_DMAPAD)
mystique_accel_ctrl_write_l(reg_addr, val, mystique); mystique_accel_ctrl_write_l(reg_addr, val, mystique);
} }
@@ -2292,10 +2291,9 @@ run_dma(mystique_t *mystique)
else else
reg_addr += 0x1c00; reg_addr += 0x1c00;
if ((reg_addr & 0x300) == 0x100 && reg_addr != REG_DMAPAD) if ((reg_addr & 0x300) == 0x100)
mystique->blitter_submit_dma_refcount++; mystique->blitter_submit_dma_refcount++;
if (reg_addr != REG_DMAPAD)
mystique_accel_ctrl_write_l(reg_addr, val, mystique); mystique_accel_ctrl_write_l(reg_addr, val, mystique);
mystique->dma.sec_header >>= 8; mystique->dma.sec_header >>= 8;