From ff7e0880d1369545ca3c054155fd9b61e6994773 Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 25 Jul 2016 01:15:51 +0200 Subject: [PATCH] Sierra RAMDAC now correctly ignores writes of 0xFF to the command register; BT485 dummy code now passes reads and writes to the generic SVGA handler; Minor S3 changes; ATI Mach64/GX now has an 8 MB RAM option. --- src/vid_ati_mach64.c | 4 ++++ src/vid_bt485_ramdac.c | 3 ++- src/vid_et4000w32.c | 5 ++--- src/vid_s3.c | 12 +++--------- src/vid_unk_ramdac.c | 17 +++++++++++------ 5 files changed, 22 insertions(+), 19 deletions(-) diff --git a/src/vid_ati_mach64.c b/src/vid_ati_mach64.c index 2add828ce..04b2d4dc9 100644 --- a/src/vid_ati_mach64.c +++ b/src/vid_ati_mach64.c @@ -2706,6 +2706,10 @@ static device_config_t mach64gx_config[] = .description = "4 MB", .value = 4 }, + { + .description = "8 MB", + .value = 8 + }, { .description = "" } diff --git a/src/vid_bt485_ramdac.c b/src/vid_bt485_ramdac.c index 174a67243..d64bf912e 100644 --- a/src/vid_bt485_ramdac.c +++ b/src/vid_bt485_ramdac.c @@ -28,6 +28,7 @@ void bt485_ramdac_out(uint16_t addr, uint8_t val, bt485_ramdac_t *ramdac, svga_t reg |= (ramdac->rs2 ? 4 : 0); reg |= (ramdac->rs3 ? 8 : 0); pclog("BT485 RAMDAC: Writing %02X to register %02X\n", val, reg); + svga_out(addr, val, svga); return; switch (addr) @@ -91,7 +92,7 @@ uint8_t bt485_ramdac_in(uint16_t addr, bt485_ramdac_t *ramdac, svga_t *svga) reg |= (ramdac->rs2 ? 4 : 0); reg |= (ramdac->rs3 ? 8 : 0); pclog("BT485 RAMDAC: Reading register %02X\n", reg); - return 0xFF; + return svga_in(addr, svga); switch (addr) { diff --git a/src/vid_et4000w32.c b/src/vid_et4000w32.c index 3d9d5161a..1db1ff156 100644 --- a/src/vid_et4000w32.c +++ b/src/vid_et4000w32.c @@ -272,7 +272,6 @@ uint8_t et4000w32p_in(uint16_t addr, void *p) return svga->crtc[svga->crtcreg]; case 0x3DA: - if (gfxcard == GFX_ET4000W32C) break; svga->attrff = 0; svga->cgastat ^= 0x30; temp = svga->cgastat & 0x39; @@ -476,8 +475,8 @@ static void et4000w32p_accel_write_fifo(et4000w32p_t *et4000, uint32_t addr, uin { et4000w32_blit(0xFFFFFF, ~0, 0, 0, et4000); } - if ((et4000->acl.queued.ctrl_routing & 0x40) && !(et4000->acl.internal.ctrl_routing & 3)) - et4000w32_blit(4, ~0, 0, 0, et4000); + /* if ((et4000->acl.queued.ctrl_routing & 0x40) && !(et4000->acl.internal.ctrl_routing & 3)) + et4000w32_blit(4, ~0, 0, 0, et4000); */ break; case 0x7fa4: et4000->acl.queued.mix_addr = (et4000->acl.queued.mix_addr & 0xFFFFFF00) | val; break; case 0x7fa5: et4000->acl.queued.mix_addr = (et4000->acl.queued.mix_addr & 0xFFFF00FF) | (val << 8); break; diff --git a/src/vid_s3.c b/src/vid_s3.c index 33fe1c5e0..84608b16b 100644 --- a/src/vid_s3.c +++ b/src/vid_s3.c @@ -921,7 +921,9 @@ uint8_t s3_in(uint16_t addr, void *p) switch (svga->crtcreg) { case 0x2d: return 0x88; /*Extended chip ID*/ - case 0x2e: return s3->id_ext; /*New chip ID*/ + case 0x2e: + if ((s3->chip != S3_TRIO32) && (s3->chip != S3_TRIO64)) return 0xFF; + return s3->id_ext; /*New chip ID*/ case 0x2f: return 0; /*Revision level*/ case 0x30: return s3->id; /*Chip ID*/ case 0x31: return (svga->crtc[0x31] & 0xcf) | ((s3->ma_ext & 3) << 4); @@ -2493,18 +2495,10 @@ static device_config_t s3_miro_vision964_config[] = .description = "2 MB", .value = 2 }, - { - .description = "3 MB", - .value = 2 - }, { .description = "4 MB", .value = 4 }, - { - .description = "6 MB", - .value = 4 - }, { .description = "8 MB", .value = 8 diff --git a/src/vid_unk_ramdac.c b/src/vid_unk_ramdac.c index d8fc35f7b..f9b9cbbf5 100644 --- a/src/vid_unk_ramdac.c +++ b/src/vid_unk_ramdac.c @@ -10,7 +10,7 @@ void unk_ramdac_out(uint16_t addr, uint8_t val, unk_ramdac_t *ramdac, svga_t *svga) { - //pclog("OUT RAMDAC %04X %02X\n",addr,val); + // pclog("OUT RAMDAC %04X %02X\n",addr,val); int oldbpp = 0; switch (addr) { @@ -18,6 +18,7 @@ void unk_ramdac_out(uint16_t addr, uint8_t val, unk_ramdac_t *ramdac, svga_t *sv if (ramdac->state == 4) { ramdac->state = 0; + if (val == 0xFF) break; ramdac->ctrl = val; #if 0 switch ((val&1)|((val&0xE0)>>4)) @@ -45,8 +46,12 @@ void unk_ramdac_out(uint16_t addr, uint8_t val, unk_ramdac_t *ramdac, svga_t *sv case 0: svga->bpp = 8; break; - case 2: case 3: - svga->bpp = 24; + case 2: case 3: case 7: + switch(val & 0x20) + { + case 0x00: svga->bpp = 32; break; + case 0x20: svga->bpp = 24; break; + } break; case 4: case 5: svga->bpp = 15; @@ -54,14 +59,14 @@ void unk_ramdac_out(uint16_t addr, uint8_t val, unk_ramdac_t *ramdac, svga_t *sv case 6: svga->bpp = 16; break; - case 1: case 7: default: + case 1: default: break; } if (oldbpp != svga->bpp) { svga_recalctimings(svga); - pclog("unk_ramdac: set to %02X, %i bpp\n", (val&1)|((val&0xE0)>>4), svga->bpp); } + // pclog("unk_ramdac: set to %02X (b5 = %i), %i bpp\n", (val&1)|((val&0xC0)>>5), val & 0x20 ? 1 : 0, svga->bpp); return; } ramdac->state = 0; @@ -75,7 +80,7 @@ void unk_ramdac_out(uint16_t addr, uint8_t val, unk_ramdac_t *ramdac, svga_t *sv uint8_t unk_ramdac_in(uint16_t addr, unk_ramdac_t *ramdac, svga_t *svga) { - //pclog("IN RAMDAC %04X\n",addr); + // pclog("IN RAMDAC %04X\n",addr); switch (addr) { case 0x3C6: