390 lines
13 KiB
C
390 lines
13 KiB
C
#include "ibm.h"
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#include "dma.h"
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#include "fdc.h"
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#include "io.h"
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#include "mem.h"
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#include "video.h"
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static uint8_t dmaregs[16];
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static int dmaon[4];
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static uint8_t dma16regs[16];
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static int dma16on[4];
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static uint8_t dmapages[16];
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void dma_reset()
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{
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int c;
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dma.wp = 0;
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for (c = 0; c < 16; c++)
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dmaregs[c] = 0;
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for (c = 0; c < 4; c++)
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{
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dma.mode[c] = 0;
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dma.ac[c] = 0;
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dma.cc[c] = 0;
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dma.ab[c] = 0;
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dma.cb[c] = 0;
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}
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dma.m = 0;
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dma16.wp = 0;
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for (c = 0; c < 16; c++)
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dma16regs[c] = 0;
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for (c = 0; c < 4; c++)
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{
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dma16.mode[c] = 0;
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dma16.ac[c] = 0;
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dma16.cc[c] = 0;
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dma16.ab[c] = 0;
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dma16.cb[c] = 0;
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}
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dma16.m = 0;
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}
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uint8_t dma_read(uint16_t addr, void *priv)
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{
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uint8_t temp;
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// printf("Read DMA %04X %04X:%04X %i %02X\n",addr,CS,pc, pic_intpending, pic.pend);
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switch (addr & 0xf)
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{
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case 0: case 2: case 4: case 6: /*Address registers*/
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dma.wp ^= 1;
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if (dma.wp)
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return dma.ac[(addr >> 1) & 3] & 0xff;
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return dma.ac[(addr >> 1) & 3] >> 8;
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case 1: case 3: case 5: case 7: /*Count registers*/
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dma.wp ^= 1;
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if (dma.wp) temp = dma.cc[(addr >> 1) & 3] & 0xff;
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else temp = dma.cc[(addr >> 1) & 3] >> 8;
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return temp;
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case 8: /*Status register*/
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temp = dma.stat;
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dma.stat = 0;
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return temp;
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case 0xd:
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return 0;
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}
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// printf("Bad DMA read %04X %04X:%04X\n",addr,CS,pc);
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return dmaregs[addr & 0xf];
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}
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void dma_write(uint16_t addr, uint8_t val, void *priv)
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{
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// printf("Write DMA %04X %02X %04X:%04X\n",addr,val,CS,pc);
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dmaregs[addr & 0xf] = val;
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switch (addr & 0xf)
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{
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case 0: case 2: case 4: case 6: /*Address registers*/
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dma.wp ^= 1;
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if (dma.wp) dma.ab[(addr >> 1) & 3] = (dma.ab[(addr >> 1) & 3] & 0xff00) | val;
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else dma.ab[(addr >> 1) & 3] = (dma.ab[(addr >> 1) & 3] & 0x00ff) | (val << 8);
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dma.ac[(addr >> 1) & 3] = dma.ab[(addr >> 1) & 3];
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dmaon[(addr >> 1) & 3] = 1;
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return;
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case 1: case 3: case 5: case 7: /*Count registers*/
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dma.wp ^= 1;
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if (dma.wp) dma.cb[(addr >> 1) & 3] = (dma.cb[(addr >> 1) & 3] & 0xff00) | val;
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else dma.cb[(addr >> 1) & 3] = (dma.cb[(addr >> 1) & 3] & 0x00ff) | (val << 8);
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dma.cc[(addr >> 1) & 3] = dma.cb[(addr >> 1) & 3];
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dmaon[(addr >> 1) & 3] = 1;
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return;
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case 8: /*Control register*/
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dma.command = val;
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return;
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case 0xa: /*Mask*/
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if (val & 4) dma.m |= (1 << (val & 3));
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else dma.m &= ~(1 << (val & 3));
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return;
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case 0xb: /*Mode*/
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dma.mode[val & 3] = val;
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return;
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case 0xc: /*Clear FF*/
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dma.wp = 0;
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return;
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case 0xd: /*Master clear*/
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dma.wp = 0;
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dma.m = 0xf;
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return;
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case 0xf: /*Mask write*/
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dma.m = val & 0xf;
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return;
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}
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}
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uint8_t dma16_read(uint16_t addr, void *priv)
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{
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uint8_t temp;
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// printf("Read DMA %04X %04X:%04X\n",addr,cs>>4,pc);
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addr >>= 1;
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switch (addr & 0xf)
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{
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case 0: case 2: case 4: case 6: /*Address registers*/
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dma16.wp ^= 1;
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if (dma16.wp)
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return dma16.ac[(addr >> 1) & 3] & 0xff;
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return dma16.ac[(addr >> 1) & 3] >> 8;
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case 1: case 3: case 5: case 7: /*Count registers*/
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dma16.wp ^= 1;
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if (dma16.wp) temp = dma16.cc[(addr >> 1) & 3] & 0xff;
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else temp = dma16.cc[(addr >> 1) & 3] >> 8;
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return temp;
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case 8: /*Status register*/
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temp = dma16.stat;
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dma16.stat = 0;
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return temp;
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}
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return dma16regs[addr & 0xf];
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}
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void dma16_write(uint16_t addr, uint8_t val, void *priv)
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{
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// printf("Write dma16 %04X %02X %04X:%04X\n",addr,val,CS,pc);
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addr >>= 1;
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dma16regs[addr & 0xf] = val;
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switch (addr & 0xf)
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{
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case 0: case 2: case 4: case 6: /*Address registers*/
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dma16.wp ^= 1;
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if (dma16.wp) dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0xff00) | val;
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else dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0x00ff) | (val << 8);
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dma16.ac[(addr >> 1) & 3] = dma16.ab[(addr >> 1) & 3];
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dma16on[(addr >> 1) & 3] = 1;
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return;
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case 1: case 3: case 5: case 7: /*Count registers*/
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dma16.wp ^= 1;
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if (dma16.wp) dma16.cb[(addr >> 1) & 3] = (dma16.cb[(addr >> 1) & 3] & 0xff00) | val;
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else dma16.cb[(addr >> 1) & 3] = (dma16.cb[(addr >> 1) & 3] & 0x00ff) | (val << 8);
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dma16.cc[(addr >> 1) & 3] = dma16.cb[(addr >> 1) & 3];
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dma16on[(addr >> 1) & 3] = 1;
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return;
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case 8: /*Control register*/
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return;
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case 0xa: /*Mask*/
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if (val & 4) dma16.m |= (1 << (val & 3));
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else dma16.m &= ~(1 << (val & 3));
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return;
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case 0xb: /*Mode*/
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dma16.mode[val & 3] = val;
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return;
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case 0xc: /*Clear FF*/
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dma16.wp = 0;
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return;
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case 0xd: /*Master clear*/
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dma16.wp = 0;
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dma16.m = 0xf;
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return;
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case 0xf: /*Mask write*/
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dma16.m = val&0xf;
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return;
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}
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}
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void dma_page_write(uint16_t addr, uint8_t val, void *priv)
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{
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dmapages[addr & 0xf] = val;
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switch (addr & 0xf)
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{
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case 1:
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dma.page[2] = (AT) ? val : val & 0xf;
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break;
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case 2:
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dma.page[3] = (AT) ? val : val & 0xf;
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break;
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case 3:
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dma.page[1] = (AT) ? val : val & 0xf;
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break;
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case 0xb:
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dma16.page[1] = val;
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break;
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}
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}
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uint8_t dma_page_read(uint16_t addr, void *priv)
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{
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return dmapages[addr & 0xf];
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}
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void dma_init()
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{
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io_sethandler(0x0000, 0x0010, dma_read, NULL, NULL, dma_write, NULL, NULL, NULL);
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io_sethandler(0x0080, 0x0008, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
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}
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void dma16_init()
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{
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io_sethandler(0x00C0, 0x0020, dma16_read, NULL, NULL, dma16_write, NULL, NULL, NULL);
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io_sethandler(0x0088, 0x0008, dma_page_read, NULL, NULL, dma_page_write, NULL, NULL, NULL);
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}
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uint8_t _dma_read(uint32_t addr)
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{
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return mem_readb_phys(addr);
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}
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void _dma_write(uint32_t addr, uint8_t val)
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{
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mem_writeb_phys(addr, val);
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mem_invalidate_range(addr, addr);
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}
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int dma_channel_read(int channel)
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{
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uint16_t temp;
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int tc = 0;
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if (dma.command & 0x04)
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return DMA_NODATA;
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if (!AT)
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refreshread();
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if (channel < 4)
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{
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if (dma.m & (1 << channel))
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return DMA_NODATA;
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if ((dma.mode[channel] & 0xC) != 8)
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return DMA_NODATA;
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temp = _dma_read(dma.ac[channel] + (dma.page[channel] << 16)); //ram[(dma.ac[2]+(dma.page[2]<<16))&rammask];
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if (dma.mode[channel] & 0x20) dma.ac[channel]--;
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else dma.ac[channel]++;
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dma.cc[channel]--;
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if (dma.cc[channel] < 0)
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{
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tc = 1;
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if (dma.mode[channel] & 0x10) /*Auto-init*/
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{
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dma.cc[channel] = dma.cb[channel];
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dma.ac[channel] = dma.ab[channel];
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}
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else
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dma.m |= (1 << channel);
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dma.stat |= (1 << channel);
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}
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if (tc)
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return temp | DMA_OVER;
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return temp;
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}
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else
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{
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channel &= 3;
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if (dma16.m & (1 << channel))
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return DMA_NODATA;
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if ((dma16.mode[channel] & 0xC) != 8)
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return DMA_NODATA;
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temp = _dma_read((dma16.ac[channel] << 1) + ((dma16.page[channel] & ~1) << 16)) |
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(_dma_read((dma16.ac[channel] << 1) + ((dma16.page[channel] & ~1) << 16) + 1) << 8);
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if (dma16.mode[channel] & 0x20) dma16.ac[channel]--;
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else dma16.ac[channel]++;
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dma16.cc[channel]--;
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if (dma16.cc[channel] < 0)
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{
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tc = 1;
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if (dma16.mode[channel] & 0x10) /*Auto-init*/
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{
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dma16.cc[channel] = dma16.cb[channel];
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dma16.ac[channel] = dma16.ab[channel];
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}
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else
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dma16.m |= (1 << channel);
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dma16.stat |= (1 << channel);
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}
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if (tc)
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return temp | DMA_OVER;
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return temp;
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}
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}
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int dma_channel_write(int channel, uint16_t val)
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{
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if (dma.command & 0x04)
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return DMA_NODATA;
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if (!AT)
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refreshread();
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if (channel < 4)
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{
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if (dma.m & (1 << channel))
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return DMA_NODATA;
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if ((dma.mode[channel] & 0xC) != 4)
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return DMA_NODATA;
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_dma_write(dma.ac[channel] + (dma.page[channel] << 16), val);
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if (dma.mode[channel]&0x20) dma.ac[channel]--;
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else dma.ac[channel]++;
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dma.cc[channel]--;
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if (dma.cc[channel] < 0)
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{
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if (dma.mode[channel] & 0x10) /*Auto-init*/
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{
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dma.cc[channel] = dma.cb[channel];
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dma.ac[channel] = dma.ab[channel];
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}
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else
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dma.m |= (1 << channel);
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dma.stat |= (1 << channel);
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}
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if (dma.m & (1 << channel))
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return DMA_OVER;
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}
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else
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{
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channel &= 3;
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if (dma16.m & (1 << channel))
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return DMA_NODATA;
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if ((dma16.mode[channel] & 0xC) != 4)
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return DMA_NODATA;
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_dma_write((dma16.ac[channel] << 1) + ((dma16.page[channel] & ~1) << 16), val);
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_dma_write((dma16.ac[channel] << 1) + ((dma16.page[channel] & ~1) << 16) + 1, val >> 8);
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if (dma16.mode[channel]&0x20) dma16.ac[channel]--;
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else dma16.ac[channel]++;
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dma16.cc[channel]--;
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if (dma16.cc[channel] < 0)
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{
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if (dma16.mode[channel] & 0x10) /*Auto-init*/
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{
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dma16.cc[channel] = dma16.cb[channel] + 1;
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dma16.ac[channel] = dma16.ab[channel];
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}
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dma16.m |= (1 << channel);
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dma16.stat |= (1 << channel);
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}
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if (dma.m & (1 << channel))
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return DMA_OVER;
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}
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return 0;
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}
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