426 lines
9.6 KiB
C
426 lines
9.6 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Universal Serial Bus emulation (currently dummy UHCI and
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* OHCI).
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2020 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/device.h>
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#include <86box/io.h>
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#include <86box/mem.h>
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#include <86box/usb.h>
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#include "cpu.h"
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#ifdef ENABLE_USB_LOG
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int usb_do_log = ENABLE_USB_LOG;
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static void
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usb_log(const char *fmt, ...)
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{
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va_list ap;
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if (usb_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define usb_log(fmt, ...)
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#endif
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static uint8_t
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uhci_reg_read(uint16_t addr, void *p)
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{
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usb_t *dev = (usb_t *) p;
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uint8_t ret, *regs = dev->uhci_io;
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addr &= 0x0000001f;
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ret = regs[addr];
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return ret;
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}
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static void
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uhci_reg_write(uint16_t addr, uint8_t val, void *p)
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{
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usb_t *dev = (usb_t *) p;
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uint8_t *regs = dev->uhci_io;
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addr &= 0x0000001f;
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switch (addr) {
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case 0x02:
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regs[0x02] &= ~(val & 0x3f);
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break;
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case 0x04:
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regs[0x04] = (val & 0x0f);
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break;
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case 0x09:
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regs[0x09] = (val & 0xf0);
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break;
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case 0x0a: case 0x0b:
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regs[addr] = val;
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break;
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case 0x0c:
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regs[0x0c] = (val & 0x7f);
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break;
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}
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}
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static void
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uhci_reg_writew(uint16_t addr, uint16_t val, void *p)
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{
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usb_t *dev = (usb_t *) p;
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uint16_t *regs = (uint16_t *) dev->uhci_io;
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addr &= 0x0000001f;
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switch (addr) {
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case 0x00:
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if ((val & 0x0001) && !(regs[0x00] & 0x0001))
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regs[0x01] &= ~0x20;
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else if (!(val & 0x0001))
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regs[0x01] |= 0x20;
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regs[0x00] = (val & 0x00ff);
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break;
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case 0x06:
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regs[0x03] = (val & 0x07ff);
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break;
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case 0x10: case 0x12:
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regs[addr >> 1] = ((regs[addr >> 1] & 0xedbb) | (val & 0x1244)) & ~(val & 0x080a);
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break;
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default:
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uhci_reg_write(addr, val & 0xff, p);
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uhci_reg_write(addr + 1, (val >> 8) & 0xff, p);
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break;
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}
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}
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void
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uhci_update_io_mapping(usb_t *dev, uint8_t base_l, uint8_t base_h, int enable)
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{
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if (dev->uhci_enable && (dev->uhci_io_base != 0x0000))
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io_removehandler(dev->uhci_io_base, 0x20, uhci_reg_read, NULL, NULL, uhci_reg_write, uhci_reg_writew, NULL, dev);
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dev->uhci_io_base = base_l | (base_h << 8);
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dev->uhci_enable = enable;
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if (dev->uhci_enable && (dev->uhci_io_base != 0x0000))
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io_sethandler(dev->uhci_io_base, 0x20, uhci_reg_read, NULL, NULL, uhci_reg_write, uhci_reg_writew, NULL, dev);
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}
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static uint8_t
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ohci_mmio_read(uint32_t addr, void *p)
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{
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usb_t *dev = (usb_t *) p;
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uint8_t ret = 0x00;
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addr &= 0x00000fff;
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ret = dev->ohci_mmio[addr];
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if (addr == 0x101)
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ret = (ret & 0xfe) | (!!mem_a20_key);
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return ret;
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}
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static void
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ohci_mmio_write(uint32_t addr, uint8_t val, void *p)
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{
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usb_t *dev = (usb_t *) p;
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uint8_t old;
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addr &= 0x00000fff;
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switch (addr) {
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case 0x04:
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if ((val & 0xc0) == 0x00) {
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/* UsbReset */
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dev->ohci_mmio[0x56] = dev->ohci_mmio[0x5a] = 0x16;
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}
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break;
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case 0x08: /* HCCOMMANDSTATUS */
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/* bit OwnershipChangeRequest triggers an ownership change (SMM <-> OS) */
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if (val & 0x08) {
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dev->ohci_mmio[0x0f] = 0x40;
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if ((dev->ohci_mmio[0x13] & 0xc0) == 0xc0)
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smi_line = 1;
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}
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/* bit HostControllerReset must be cleared for the controller to be seen as initialized */
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if (val & 0x01) {
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memset(dev->ohci_mmio, 0x00, 4096);
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dev->ohci_mmio[0x00] = 0x10;
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dev->ohci_mmio[0x01] = 0x01;
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dev->ohci_mmio[0x48] = 0x02;
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val &= ~0x01;
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}
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break;
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case 0x0c:
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dev->ohci_mmio[addr] &= ~(val & 0x7f);
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return;
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case 0x0d: case 0x0e:
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return;
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case 0x0f:
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dev->ohci_mmio[addr] &= ~(val & 0x40);
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return;
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case 0x3b:
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dev->ohci_mmio[addr] = (val & 0x80);
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return;
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case 0x39: case 0x41:
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dev->ohci_mmio[addr] = (val & 0x3f);
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return;
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case 0x45:
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dev->ohci_mmio[addr] = (val & 0x0f);
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return;
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case 0x3a:
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case 0x3e: case 0x3f: case 0x42: case 0x43:
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case 0x46: case 0x47: case 0x48: case 0x4a:
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return;
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case 0x49:
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dev->ohci_mmio[addr] = (val & 0x1b);
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if (val & 0x02) {
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dev->ohci_mmio[0x55] |= 0x01;
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dev->ohci_mmio[0x59] |= 0x01;
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}
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return;
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case 0x4b:
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dev->ohci_mmio[addr] = (val & 0x03);
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return;
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case 0x4c: case 0x4e:
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dev->ohci_mmio[addr] = (val & 0x06);
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if ((addr == 0x4c) && !(val & 0x04)) {
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if (!(dev->ohci_mmio[0x58] & 0x01))
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dev->ohci_mmio[0x5a] |= 0x01;
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dev->ohci_mmio[0x58] |= 0x01;
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} if ((addr == 0x4c) && !(val & 0x02)) {
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if (!(dev->ohci_mmio[0x54] & 0x01))
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dev->ohci_mmio[0x56] |= 0x01;
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dev->ohci_mmio[0x54] |= 0x01;
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}
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return;
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case 0x4d: case 0x4f:
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return;
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case 0x50:
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if (val & 0x01) {
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if ((dev->ohci_mmio[0x49] & 0x03) == 0x00) {
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dev->ohci_mmio[0x55] &= ~0x01;
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dev->ohci_mmio[0x54] &= ~0x17;
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dev->ohci_mmio[0x56] &= ~0x17;
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dev->ohci_mmio[0x59] &= ~0x01;
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dev->ohci_mmio[0x58] &= ~0x17;
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dev->ohci_mmio[0x5a] &= ~0x17;
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} else if ((dev->ohci_mmio[0x49] & 0x03) == 0x01) {
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if (!(dev->ohci_mmio[0x4e] & 0x02)) {
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dev->ohci_mmio[0x55] &= ~0x01;
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dev->ohci_mmio[0x54] &= ~0x17;
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dev->ohci_mmio[0x56] &= ~0x17;
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}
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if (!(dev->ohci_mmio[0x4e] & 0x04)) {
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dev->ohci_mmio[0x59] &= ~0x01;
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dev->ohci_mmio[0x58] &= ~0x17;
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dev->ohci_mmio[0x5a] &= ~0x17;
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}
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}
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}
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return;
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case 0x51:
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if (val & 0x80)
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dev->ohci_mmio[addr] |= 0x80;
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return;
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case 0x52:
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dev->ohci_mmio[addr] &= ~(val & 0x02);
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if (val & 0x01) {
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if ((dev->ohci_mmio[0x49] & 0x03) == 0x00) {
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dev->ohci_mmio[0x55] |= 0x01;
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dev->ohci_mmio[0x59] |= 0x01;
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} else if ((dev->ohci_mmio[0x49] & 0x03) == 0x01) {
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if (!(dev->ohci_mmio[0x4e] & 0x02))
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dev->ohci_mmio[0x55] |= 0x01;
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if (!(dev->ohci_mmio[0x4e] & 0x04))
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dev->ohci_mmio[0x59] |= 0x01;
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}
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}
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return;
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case 0x53:
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if (val & 0x80)
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dev->ohci_mmio[0x51] &= ~0x80;
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return;
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case 0x54: case 0x58:
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old = dev->ohci_mmio[addr];
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if (val & 0x10) {
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if (old & 0x01) {
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dev->ohci_mmio[addr] |= 0x10;
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/* TODO: The clear should be on a 10 ms timer. */
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dev->ohci_mmio[addr] &= ~0x10;
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dev->ohci_mmio[addr + 2] |= 0x10;
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} else
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dev->ohci_mmio[addr + 2] |= 0x01;
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}
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if (val & 0x08)
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dev->ohci_mmio[addr] &= ~0x04;
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if (val & 0x04)
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dev->ohci_mmio[addr] |= 0x04;
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if (val & 0x02) {
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if (old & 0x01)
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dev->ohci_mmio[addr] |= 0x02;
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else
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dev->ohci_mmio[addr + 2] |= 0x01;
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}
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if (val & 0x01) {
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if (old & 0x01)
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dev->ohci_mmio[addr] &= ~0x02;
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else
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dev->ohci_mmio[addr + 2] |= 0x01;
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}
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if (!(dev->ohci_mmio[addr] & 0x04) && (old & 0x04))
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dev->ohci_mmio[addr + 2] |= 0x04;
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/* if (!(dev->ohci_mmio[addr] & 0x02))
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dev->ohci_mmio[addr + 2] |= 0x02; */
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return;
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case 0x55:
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if ((val & 0x02) && ((dev->ohci_mmio[0x49] & 0x03) == 0x00) && (dev->ohci_mmio[0x4e] & 0x02)) {
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dev->ohci_mmio[addr] &= ~0x01;
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dev->ohci_mmio[0x54] &= ~0x17;
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dev->ohci_mmio[0x56] &= ~0x17;
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} if ((val & 0x01) && ((dev->ohci_mmio[0x49] & 0x03) == 0x00) && (dev->ohci_mmio[0x4e] & 0x02)) {
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dev->ohci_mmio[addr] |= 0x01;
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dev->ohci_mmio[0x58] &= ~0x17;
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dev->ohci_mmio[0x5a] &= ~0x17;
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}
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return;
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case 0x59:
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if ((val & 0x02) && ((dev->ohci_mmio[0x49] & 0x03) == 0x00) && (dev->ohci_mmio[0x4e] & 0x04))
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dev->ohci_mmio[addr] &= ~0x01;
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if ((val & 0x01) && ((dev->ohci_mmio[0x49] & 0x03) == 0x00) && (dev->ohci_mmio[0x4e] & 0x04))
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dev->ohci_mmio[addr] |= 0x01;
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return;
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case 0x56: case 0x5a:
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dev->ohci_mmio[addr] &= ~(val & 0x1f);
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return;
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case 0x57: case 0x5b:
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return;
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}
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dev->ohci_mmio[addr] = val;
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}
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void
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ohci_update_mem_mapping(usb_t *dev, uint8_t base1, uint8_t base2, uint8_t base3, int enable)
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{
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if (dev->ohci_enable && (dev->ohci_mem_base != 0x00000000))
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mem_mapping_disable(&dev->ohci_mmio_mapping);
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dev->ohci_mem_base = ((base1 << 8) | (base2 << 16) | (base3 << 24)) & 0xfffff000;
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dev->ohci_enable = enable;
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if (dev->ohci_enable && (dev->ohci_mem_base != 0x00000000))
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mem_mapping_set_addr(&dev->ohci_mmio_mapping, dev->ohci_mem_base, 0x1000);
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}
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static void
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usb_reset(void *priv)
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{
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usb_t *dev = (usb_t *) priv;
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memset(dev->uhci_io, 0x00, 128);
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dev->uhci_io[0x0c] = 0x40;
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dev->uhci_io[0x10] = dev->uhci_io[0x12] = 0x80;
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memset(dev->ohci_mmio, 0x00, 4096);
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dev->ohci_mmio[0x00] = 0x10;
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dev->ohci_mmio[0x01] = 0x01;
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dev->ohci_mmio[0x48] = 0x02;
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io_removehandler(dev->uhci_io_base, 0x20, uhci_reg_read, NULL, NULL, uhci_reg_write, uhci_reg_writew, NULL, dev);
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dev->uhci_enable = 0;
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mem_mapping_disable(&dev->ohci_mmio_mapping);
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dev->ohci_enable = 0;
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}
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static void
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usb_close(void *priv)
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{
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usb_t *dev = (usb_t *) priv;
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free(dev);
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}
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static void *
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usb_init(const device_t *info)
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{
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usb_t *dev;
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dev = (usb_t *)malloc(sizeof(usb_t));
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if (dev == NULL) return(NULL);
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memset(dev, 0x00, sizeof(usb_t));
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memset(dev->uhci_io, 0x00, 128);
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dev->uhci_io[0x0c] = 0x40;
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dev->uhci_io[0x10] = dev->uhci_io[0x12] = 0x80;
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memset(dev->ohci_mmio, 0x00, 4096);
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dev->ohci_mmio[0x00] = 0x10;
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dev->ohci_mmio[0x01] = 0x01;
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dev->ohci_mmio[0x48] = 0x02;
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mem_mapping_add(&dev->ohci_mmio_mapping, 0, 0,
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ohci_mmio_read, NULL, NULL,
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ohci_mmio_write, NULL, NULL,
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NULL, MEM_MAPPING_EXTERNAL, dev);
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usb_reset(dev);
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return dev;
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}
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const device_t usb_device =
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{
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"Universal Serial Bus",
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DEVICE_PCI,
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0,
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usb_init,
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usb_close,
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usb_reset,
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{ NULL },
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NULL,
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NULL,
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NULL
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};
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