415 lines
12 KiB
C
415 lines
12 KiB
C
/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the Chips & Technologies F82C710 Universal Peripheral
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* Controller (UPC) and 82C606 CHIPSpak Multifunction Controller.
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*
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* Relevant literature:
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*
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* [1] Chips and Technologies, Inc.,
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* 82C605/82C606 CHIPSpak/CHIPSport MULTIFUNCTION CONTROLLERS,
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* PRELIMINARY Data Sheet, Revision 1, May 1987.
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* <https://archive.org/download/82C606/82C606.pdf>
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*
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*
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*
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* Authors: Eluan Costa Miranda <eluancm@gmail.com>
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* Lubomir Rintel <lkundrak@v3.sk>
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*
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* Copyright 2020 Eluan Costa Miranda.
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* Copyright 2021 Lubomir Rintel.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/io.h>
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#include <86box/timer.h>
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#include <86box/device.h>
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#include <86box/lpt.h>
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#include <86box/serial.h>
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#include <86box/gameport.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/nvr.h>
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#include <86box/sio.h>
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typedef struct upc_t {
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uint32_t local;
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int configuration_state; /* state of algorithm to enter configuration mode */
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int configuration_mode;
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uint16_t cri_addr; /* cri = configuration index register, addr is even */
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uint16_t cap_addr; /* cap = configuration access port, addr is odd and is cri_addr + 1 */
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uint8_t cri; /* currently indexed register */
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uint8_t last_write;
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/* these regs are not affected by reset */
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uint8_t regs[15]; /* there are 16 indexes, but there is no need to store the last one which is: R = cri_addr / 4, W = exit config mode */
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fdc_t *fdc;
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nvr_t *nvr;
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void *gameport;
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serial_t *uart[2];
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} upc_t;
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#ifdef ENABLE_F82C710_LOG
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int f82c710_do_log = ENABLE_F82C710_LOG;
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static void
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f82c710_log(const char *fmt, ...)
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{
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va_list ap;
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if (f82c710_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define f82c710_log(fmt, ...)
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#endif
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static void
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f82c710_update_ports(upc_t *dev, int set)
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{
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uint16_t com_addr = 0;
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uint16_t lpt_addr = 0;
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serial_remove(dev->uart[0]);
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serial_remove(dev->uart[1]);
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lpt1_remove();
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lpt2_remove();
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fdc_remove(dev->fdc);
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ide_pri_disable();
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if (!set)
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return;
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if (dev->regs[0] & 4) {
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com_addr = dev->regs[4] * 4;
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if (com_addr == COM1_ADDR)
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serial_setup(dev->uart[0], com_addr, COM1_IRQ);
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else if (com_addr == COM2_ADDR)
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serial_setup(dev->uart[1], com_addr, COM2_IRQ);
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}
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if (dev->regs[0] & 8) {
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lpt_addr = dev->regs[6] * 4;
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lpt1_init(lpt_addr);
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if ((lpt_addr == LPT1_ADDR) || (lpt_addr == LPT_MDA_ADDR))
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lpt1_irq(LPT1_IRQ);
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else if (lpt_addr == LPT2_ADDR)
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lpt1_irq(LPT2_IRQ);
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}
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if (dev->regs[12] & 0x80)
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ide_pri_enable();
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if (dev->regs[12] & 0x20)
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fdc_set_base(dev->fdc, FDC_PRIMARY_ADDR);
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}
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static void
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f82c606_update_ports(upc_t *dev, int set)
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{
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uint8_t uart1_int = 0xff;
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uint8_t uart2_int = 0xff;
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uint8_t lpt1_int = 0xff;
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int nvr_int = -1;
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serial_remove(dev->uart[0]);
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serial_remove(dev->uart[1]);
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lpt1_remove();
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lpt2_remove();
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nvr_at_handler(0, ((uint16_t) dev->regs[3]) << 2, dev->nvr);
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nvr_at_handler(0, 0x70, dev->nvr);
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gameport_remap(dev->gameport, 0);
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if (!set)
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return;
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switch (dev->regs[8] & 0xc0) {
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case 0x40:
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nvr_int = 3;
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break;
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case 0x80:
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uart1_int = COM2_IRQ;
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break;
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case 0xc0:
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uart2_int = COM2_IRQ;
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break;
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default:
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break;
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}
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switch (dev->regs[8] & 0x30) {
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case 0x10:
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nvr_int = 4;
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break;
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case 0x20:
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uart1_int = COM1_IRQ;
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break;
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case 0x30:
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uart2_int = COM1_IRQ;
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break;
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default:
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break;
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}
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switch (dev->regs[8] & 0x0c) {
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case 0x04:
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nvr_int = 5;
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break;
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case 0x08:
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uart1_int = 5;
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break;
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case 0x0c:
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lpt1_int = LPT2_IRQ;
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break;
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default:
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break;
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}
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switch (dev->regs[8] & 0x03) {
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case 0x01:
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nvr_int = 7;
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break;
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case 0x02:
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uart2_int = 7;
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break;
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case 0x03:
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lpt1_int = LPT1_IRQ;
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break;
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default:
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break;
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}
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if (dev->regs[0] & 1) {
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gameport_remap(dev->gameport, ((uint16_t) dev->regs[7]) << 2);
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f82c710_log("Game port at %04X\n", ((uint16_t) dev->regs[7]) << 2);
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}
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if (dev->regs[0] & 2) {
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serial_setup(dev->uart[0], ((uint16_t) dev->regs[4]) << 2, uart1_int);
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f82c710_log("UART 1 at %04X, IRQ %i\n", ((uint16_t) dev->regs[4]) << 2, uart1_int);
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}
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if (dev->regs[0] & 4) {
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serial_setup(dev->uart[1], ((uint16_t) dev->regs[5]) << 2, uart2_int);
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f82c710_log("UART 2 at %04X, IRQ %i\n", ((uint16_t) dev->regs[5]) << 2, uart2_int);
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}
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if (dev->regs[0] & 8) {
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lpt1_init(((uint16_t) dev->regs[6]) << 2);
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lpt1_irq(lpt1_int);
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f82c710_log("LPT1 at %04X, IRQ %i\n", ((uint16_t) dev->regs[6]) << 2, lpt1_int);
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}
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nvr_at_handler(1, ((uint16_t) dev->regs[3]) << 2, dev->nvr);
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nvr_irq_set(nvr_int, dev->nvr);
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f82c710_log("RTC at %04X, IRQ %i\n", ((uint16_t) dev->regs[3]) << 2, nvr_int);
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}
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static uint8_t
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f82c710_config_read(uint16_t port, void *priv)
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{
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const upc_t *dev = (upc_t *) priv;
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uint8_t temp = 0xff;
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if (dev->configuration_mode) {
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if (port == dev->cri_addr) {
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temp = dev->cri;
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} else if (port == dev->cap_addr) {
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if (dev->cri == 0xf)
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temp = dev->cri_addr / 4;
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else
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temp = dev->regs[dev->cri];
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}
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}
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return temp;
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}
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static void
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f82c710_config_write(uint16_t port, uint8_t val, void *priv)
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{
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upc_t *dev = (upc_t *) priv;
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int configuration_state_event = 0;
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switch (port) {
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case 0x2fa:
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if ((dev->configuration_state == 0) && (val != 0x00) && (val != 0xff) && (dev->local == 606)) {
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configuration_state_event = 1;
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dev->last_write = val;
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} else if ((dev->configuration_state == 0) && (val == 0x55) && (dev->local == 710))
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configuration_state_event = 1;
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else if (dev->configuration_state == 4) {
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if ((val | dev->last_write) == 0xff) {
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dev->cri_addr = ((uint16_t) dev->last_write) << 2;
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dev->cap_addr = dev->cri_addr + 1;
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dev->configuration_mode = 1;
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if (dev->local == 606)
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f82c606_update_ports(dev, 0);
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else if (dev->local == 710)
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f82c710_update_ports(dev, 0);
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/* TODO: is the value of cri reset here or when exiting configuration mode? */
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io_sethandler(dev->cri_addr, 0x0002, f82c710_config_read, NULL, NULL, f82c710_config_write, NULL, NULL, dev);
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} else
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dev->configuration_mode = 0;
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}
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break;
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case 0x3fa:
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if ((dev->configuration_state == 1) && ((val | dev->last_write) == 0xff) && (dev->local == 606))
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configuration_state_event = 1;
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else if ((dev->configuration_state == 1) && (val == 0xaa) && (dev->local == 710))
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configuration_state_event = 1;
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else if ((dev->configuration_state == 2) && (val == 0x36))
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configuration_state_event = 1;
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else if (dev->configuration_state == 3) {
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dev->last_write = val;
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configuration_state_event = 1;
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}
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break;
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default:
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break;
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}
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if (dev->configuration_mode) {
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if (port == dev->cri_addr) {
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dev->cri = val & 0xf;
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} else if (port == dev->cap_addr) {
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if (dev->cri == 0xf) {
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dev->configuration_mode = 0;
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io_removehandler(dev->cri_addr, 0x0002, f82c710_config_read, NULL, NULL, f82c710_config_write, NULL, NULL, dev);
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/* TODO: any benefit in updating at each register write instead of when exiting config mode? */
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if (dev->local == 606)
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f82c606_update_ports(dev, 1);
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else if (dev->local == 710)
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f82c710_update_ports(dev, 1);
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} else
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dev->regs[dev->cri] = val;
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}
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}
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/* TODO: is the state only reset when accessing 0x2fa and 0x3fa wrongly? */
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if ((port == 0x2fa || port == 0x3fa) && configuration_state_event)
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dev->configuration_state++;
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else
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dev->configuration_state = 0;
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}
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static void
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f82c710_reset(void *priv)
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{
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upc_t *dev = (upc_t *) priv;
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/* Set power-on defaults. */
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if (dev->local == 606) {
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dev->regs[0] = 0x00; /* Enable */
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dev->regs[1] = 0x00; /* Configuration Register */
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dev->regs[2] = 0x00; /* Ext Baud Rate Select */
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dev->regs[3] = 0xb0; /* RTC Base */
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dev->regs[4] = 0xfe; /* UART1 Base */
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dev->regs[5] = 0xbe; /* UART2 Base */
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dev->regs[6] = 0x9e; /* Parallel Base */
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dev->regs[7] = 0x80; /* Game Base */
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dev->regs[8] = 0xec; /* Interrupt Select */
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} else if (dev->local == 710) {
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dev->regs[0] = 0x0c;
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dev->regs[1] = 0x00;
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dev->regs[2] = 0x00;
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dev->regs[3] = 0x00;
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dev->regs[4] = 0xfe;
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dev->regs[5] = 0x00;
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dev->regs[6] = 0x9e;
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dev->regs[7] = 0x00;
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dev->regs[8] = 0x00;
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dev->regs[9] = 0xb0;
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dev->regs[10] = 0x00;
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dev->regs[11] = 0x00;
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dev->regs[12] = 0xa0;
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dev->regs[13] = 0x00;
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dev->regs[14] = 0x00;
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}
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if (dev->local == 606)
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f82c606_update_ports(dev, 1);
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else if (dev->local == 710)
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f82c710_update_ports(dev, 1);
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}
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static void
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f82c710_close(void *priv)
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{
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upc_t *dev = (upc_t *) priv;
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free(dev);
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}
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static void *
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f82c710_init(const device_t *info)
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{
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upc_t *dev = (upc_t *) malloc(sizeof(upc_t));
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memset(dev, 0, sizeof(upc_t));
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dev->local = info->local;
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if (dev->local == 606) {
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dev->nvr = device_add(&at_nvr_old_device);
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dev->gameport = gameport_add(&gameport_sio_device);
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} else if (dev->local == 710)
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dev->fdc = device_add(&fdc_at_device);
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dev->uart[0] = device_add_inst(&ns16450_device, 1);
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dev->uart[1] = device_add_inst(&ns16450_device, 2);
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io_sethandler(0x02fa, 0x0001, NULL, NULL, NULL, f82c710_config_write, NULL, NULL, dev);
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io_sethandler(0x03fa, 0x0001, NULL, NULL, NULL, f82c710_config_write, NULL, NULL, dev);
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f82c710_reset(dev);
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return dev;
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}
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const device_t f82c606_device = {
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.name = "82C606 CHIPSpak Multifunction Controller",
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.internal_name = "f82c606",
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.flags = 0,
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.local = 606,
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.init = f82c710_init,
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.close = f82c710_close,
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.reset = f82c710_reset,
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{ .available = NULL },
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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const device_t f82c710_device = {
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.name = "F82C710 UPC Super I/O",
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.internal_name = "f82c710",
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.flags = 0,
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.local = 710,
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.init = f82c710_init,
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.close = f82c710_close,
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.reset = f82c710_reset,
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{ .available = NULL },
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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