2022-01-03 17:30:07 +05:30
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#!/bin/sh
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# We don't regenerate it on every "make" invocation - only by hand.
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# The reason is that the changes to generated code are difficult
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# to visualize by looking only at this script, it helps when the commit
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# also contains the diff of the generated file.
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exec >hash_md5_sha_x86-64.S
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2022-01-23 13:57:30 +05:30
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# Based on http://arctic.org/~dean/crypto/sha1.html.
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# ("This SHA1 implementation is public domain.")
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#
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# x86-64 has at least SSE2 vector insns always available.
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# We can use them without any CPUID checks (and without a need
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# for a fallback code if needed insns are not available).
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# This code uses them to calculate W[] ahead of time.
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#
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# Unfortunately, results are passed from vector unit to
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# integer ALUs on the stack. MOVD/Q insns to move them directly
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# from vector to integer registers are slower than store-to-load
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# forwarding in LSU (on Skylake at least).
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#
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# The win against a purely integer code is small on Skylake,
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# only about 7-8%. We offload about 1/3 of our operations to the vector unit.
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# It can do 4 ops at once in one 128-bit register,
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# but we have to use x2 of them because of W[0] complication,
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# SSE2 has no "rotate each word by N bits" insns,
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# moving data to/from vector unit is clunky, and Skylake
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# has four integer ALUs unified with three vector ALUs,
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# which makes pure integer code rather fast, and makes
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# vector ops compete with integer ones.
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#
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# Zen3, with its separate vector ALUs, wins more, about 12%.
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xmmT1="%xmm4"
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xmmT2="%xmm5"
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xmmRCONST="%xmm6"
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T=`printf '\t'`
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# SSE instructions are longer than 4 bytes on average.
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# Intel CPUs (up to Tiger Lake at least) can't decode
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# more than 16 bytes of code in one cycle.
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# By interleaving SSE code and integer code
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# we mostly achieve a situation where 16-byte decode fetch window
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# contains 4 (or more) insns.
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#
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# However. On Skylake, there was no observed difference,
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# but on Zen3, non-interleaved code is ~3% faster
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# (822 Mb/s versus 795 Mb/s hashing speed).
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# Off for now:
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interleave=false
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INTERLEAVE() {
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$interleave || \
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{
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# Generate non-interleaved code
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# (it should work correctly too)
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echo "$1"
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echo "$2"
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return
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}
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(
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echo "$1" | grep -v '^$' >"$0.temp1"
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echo "$2" | grep -v '^$' >"$0.temp2"
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exec 3<"$0.temp1"
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exec 4<"$0.temp2"
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IFS=''
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while :; do
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line1=''
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line2=''
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while :; do
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read -r line1 <&3
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if test "${line1:0:1}" != "#" && test "${line1:0:2}" != "$T#"; then
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break
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fi
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echo "$line1"
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done
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while :; do
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read -r line2 <&4
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if test "${line2:0:4}" = "${T}lea"; then
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# We use 7-8 byte long forms of LEA.
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# Do not interleave them with SSE insns
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# which are also long.
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echo "$line2"
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read -r line2 <&4
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echo "$line2"
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continue
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fi
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if test "${line2:0:1}" != "#" && test "${line2:0:2}" != "$T#"; then
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break
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fi
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echo "$line2"
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done
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test "$line1$line2" || break
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echo "$line1"
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echo "$line2"
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done
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rm "$0.temp1" "$0.temp2"
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)
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}
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2022-01-09 03:13:24 +05:30
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2022-01-03 17:30:07 +05:30
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echo \
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2022-01-23 13:57:30 +05:30
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"### Generated by hash_md5_sha_x86-64.S.sh ###
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2022-01-03 17:30:07 +05:30
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#if CONFIG_SHA1_SMALL == 0 && defined(__GNUC__) && defined(__x86_64__)
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2022-01-25 21:30:57 +05:30
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.section .text.sha1_process_block64, \"ax\", @progbits
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2022-01-08 05:11:09 +05:30
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.globl sha1_process_block64
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.hidden sha1_process_block64
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2022-01-03 17:30:07 +05:30
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.type sha1_process_block64, @function
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2022-01-04 06:15:13 +05:30
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.balign 8 # allow decoders to fetch at least 5 first insns
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2022-01-03 17:30:07 +05:30
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sha1_process_block64:
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2022-01-04 06:15:13 +05:30
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pushq %rbp # 1 byte insn
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pushq %rbx # 1 byte insn
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2022-01-25 21:30:57 +05:30
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# pushq %r15 # 2 byte insn
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2022-01-04 06:15:13 +05:30
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pushq %r14 # 2 byte insn
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pushq %r13 # 2 byte insn
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pushq %r12 # 2 byte insn
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2022-01-03 17:30:07 +05:30
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pushq %rdi # we need ctx at the end
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#Register and stack use:
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# eax..edx: a..d
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# ebp: e
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2022-01-25 21:30:57 +05:30
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# esi,edi,r8..r14: temps
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# r15: unused
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2022-01-23 13:57:30 +05:30
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# xmm0..xmm3: W[]
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# xmm4,xmm5: temps
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# xmm6: current round constant
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# -64(%rsp): area for passing RCONST + W[] from vector to integer units
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2022-01-04 06:15:13 +05:30
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2022-01-03 17:30:07 +05:30
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movl 80(%rdi), %eax # a = ctx->hash[0]
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movl 84(%rdi), %ebx # b = ctx->hash[1]
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movl 88(%rdi), %ecx # c = ctx->hash[2]
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movl 92(%rdi), %edx # d = ctx->hash[3]
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movl 96(%rdi), %ebp # e = ctx->hash[4]
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2022-01-04 06:15:13 +05:30
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2022-01-23 13:57:30 +05:30
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movaps rconst0x5A827999(%rip), $xmmRCONST
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2022-01-25 21:30:57 +05:30
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# Load W[] to xmm registers, byteswapping on the fly.
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#
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# For iterations 0..15, we pass W[] in rsi,r8..r14
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# for use in RD1A's instead of spilling them to stack.
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# We lose parallelized addition of RCONST, but LEA
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# can do two additions at once, so it's probably a wash.
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# (We use rsi instead of rN because this makes two
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# LEAs in two first RD1A's shorter by one byte).
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2022-01-23 13:57:30 +05:30
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movq 4*0(%rdi), %rsi
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2022-01-25 21:30:57 +05:30
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movq 4*2(%rdi), %r8
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2022-01-23 13:57:30 +05:30
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bswapq %rsi
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2022-01-25 21:30:57 +05:30
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bswapq %r8
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2022-01-23 13:57:30 +05:30
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rolq \$32, %rsi # rsi = W[1]:W[0]
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2022-01-25 21:30:57 +05:30
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rolq \$32, %r8 # r8 = W[3]:W[2]
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2022-01-23 13:57:30 +05:30
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movq %rsi, %xmm0
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2022-01-25 21:30:57 +05:30
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movq %r8, $xmmT1
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punpcklqdq $xmmT1, %xmm0 # xmm0 = r8:rsi = (W[0],W[1],W[2],W[3])
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# movaps %xmm0, $xmmT1 # add RCONST, spill to stack
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# paddd $xmmRCONST, $xmmT1
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# movups $xmmT1, -64+16*0(%rsp)
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2022-01-23 13:57:30 +05:30
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2022-01-25 21:30:57 +05:30
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movq 4*4(%rdi), %r9
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2022-01-23 13:57:30 +05:30
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movq 4*6(%rdi), %r10
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2022-01-25 21:30:57 +05:30
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bswapq %r9
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2022-01-23 13:57:30 +05:30
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bswapq %r10
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2022-01-25 21:30:57 +05:30
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rolq \$32, %r9 # r9 = W[5]:W[4]
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rolq \$32, %r10 # r10 = W[7]:W[6]
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movq %r9, %xmm1
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2022-01-23 13:57:30 +05:30
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movq %r10, $xmmT1
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2022-01-25 21:30:57 +05:30
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punpcklqdq $xmmT1, %xmm1 # xmm1 = r10:r9 = (W[4],W[5],W[6],W[7])
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2022-01-23 13:57:30 +05:30
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2022-01-25 21:30:57 +05:30
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movq 4*8(%rdi), %r11
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movq 4*10(%rdi), %r12
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bswapq %r11
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bswapq %r12
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rolq \$32, %r11 # r11 = W[9]:W[8]
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rolq \$32, %r12 # r12 = W[11]:W[10]
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movq %r11, %xmm2
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movq %r12, $xmmT1
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punpcklqdq $xmmT1, %xmm2 # xmm2 = r12:r11 = (W[8],W[9],W[10],W[11])
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2022-01-23 13:57:30 +05:30
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2022-01-25 21:30:57 +05:30
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movq 4*12(%rdi), %r13
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2022-01-04 06:15:13 +05:30
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movq 4*14(%rdi), %r14
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2022-01-25 21:30:57 +05:30
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bswapq %r13
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2022-01-04 06:15:13 +05:30
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bswapq %r14
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2022-01-25 21:30:57 +05:30
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rolq \$32, %r13 # r13 = W[13]:W[12]
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2022-01-23 13:57:30 +05:30
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rolq \$32, %r14 # r14 = W[15]:W[14]
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2022-01-25 21:30:57 +05:30
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movq %r13, %xmm3
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2022-01-23 13:57:30 +05:30
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movq %r14, $xmmT1
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2022-01-25 21:30:57 +05:30
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punpcklqdq $xmmT1, %xmm3 # xmm3 = r14:r13 = (W[12],W[13],W[14],W[15])
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2022-01-23 13:57:30 +05:30
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"
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PREP() {
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local xmmW0=$1
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local xmmW4=$2
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local xmmW8=$3
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local xmmW12=$4
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# the above must be %xmm0..3 in some permutation
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local dstmem=$5
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#W[0] = rol(W[13] ^ W[8] ^ W[2] ^ W[0], 1);
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#W[1] = rol(W[14] ^ W[9] ^ W[3] ^ W[1], 1);
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#W[2] = rol(W[15] ^ W[10] ^ W[4] ^ W[2], 1);
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#W[3] = rol( 0 ^ W[11] ^ W[5] ^ W[3], 1);
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#W[3] ^= rol(W[0], 1);
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echo "# PREP $@
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movaps $xmmW12, $xmmT1
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psrldq \$4, $xmmT1 # rshift by 4 bytes: T1 = ([13],[14],[15],0)
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pshufd \$0x4e, $xmmW0, $xmmT2 # 01001110=2,3,0,1 shuffle, ([2],[3],x,x)
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punpcklqdq $xmmW4, $xmmT2 # T2 = W4[0..63]:T2[0..63] = ([2],[3],[4],[5])
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xorps $xmmW8, $xmmW0 # ([8],[9],[10],[11]) ^ ([0],[1],[2],[3])
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xorps $xmmT1, $xmmT2 # ([13],[14],[15],0) ^ ([2],[3],[4],[5])
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xorps $xmmT2, $xmmW0 # ^
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# W0 = unrotated (W[0]..W[3]), still needs W[3] fixup
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movaps $xmmW0, $xmmT2
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xorps $xmmT1, $xmmT1 # rol(W0,1):
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2022-01-25 21:30:57 +05:30
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pcmpgtd $xmmW0, $xmmT1 # ffffffff for elements <0 (ones with msb bit 1)
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paddd $xmmW0, $xmmW0 # shift left by 1
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psubd $xmmT1, $xmmW0 # add 1 to those who had msb bit 1
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2022-01-23 13:57:30 +05:30
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# W0 = rotated (W[0]..W[3]), still needs W[3] fixup
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pslldq \$12, $xmmT2 # lshift by 12 bytes: T2 = (0,0,0,unrotW[0])
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movaps $xmmT2, $xmmT1
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pslld \$2, $xmmT2
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psrld \$30, $xmmT1
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# xorps $xmmT1, $xmmT2 # rol((0,0,0,unrotW[0]),2)
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xorps $xmmT1, $xmmW0 # same result, but does not depend on/does not modify T2
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xorps $xmmT2, $xmmW0 # W0 = rol(W[0]..W[3],1) ^ (0,0,0,rol(unrotW[0],2))
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"
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# movq $xmmW0, %r8 # high latency (~6 cycles)
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# movaps $xmmW0, $xmmT1
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# psrldq \$8, $xmmT1 # rshift by 8 bytes: move upper 64 bits to lower
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# movq $xmmT1, %r10 # high latency
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# movq %r8, %r9
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# movq %r10, %r11
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# shrq \$32, %r9
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# shrq \$32, %r11
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# ^^^ slower than passing the results on stack (!!!)
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echo "
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movaps $xmmW0, $xmmT2
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paddd $xmmRCONST, $xmmT2
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movups $xmmT2, $dstmem
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"
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2022-01-03 17:30:07 +05:30
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}
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2022-01-23 13:57:30 +05:30
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# It's possible to interleave integer insns in rounds to mostly eliminate
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2022-01-04 06:15:13 +05:30
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# dependency chains, but this likely to only help old Pentium-based
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# CPUs (ones without OOO, which can only simultaneously execute a pair
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# of _adjacent_ insns).
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# Testing on old-ish Silvermont CPU (which has OOO window of only
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# about ~8 insns) shows very small (~1%) speedup.
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2022-01-03 17:30:07 +05:30
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RD1A() {
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local a=$1;local b=$2;local c=$3;local d=$4;local e=$5
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local n=$(($6))
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2022-01-03 21:32:48 +05:30
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local n0=$(((n+0) & 15))
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2022-01-25 21:30:57 +05:30
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local rN=$((7+n0/2))
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2022-01-03 21:32:48 +05:30
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echo "
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# $n
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";test $n0 = 0 && echo "
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2022-01-23 13:57:30 +05:30
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leal $RCONST(%r$e,%rsi), %e$e # e += RCONST + W[n]
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2022-01-25 21:30:57 +05:30
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shrq \$32, %rsi
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";test $n0 = 1 && echo "
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leal $RCONST(%r$e,%rsi), %e$e # e += RCONST + W[n]
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";test $n0 -ge 2 && test $((n0 & 1)) = 0 && echo "
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leal $RCONST(%r$e,%r$rN), %e$e # e += RCONST + W[n]
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shrq \$32, %r$rN
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";test $n0 -ge 2 && test $((n0 & 1)) = 1 && echo "
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leal $RCONST(%r$e,%r$rN), %e$e # e += RCONST + W[n]
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2022-01-03 17:30:07 +05:30
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";echo "
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movl %e$c, %edi # c
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xorl %e$d, %edi # ^d
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andl %e$b, %edi # &b
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xorl %e$d, %edi # (((c ^ d) & b) ^ d)
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addl %edi, %e$e # e += (((c ^ d) & b) ^ d)
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2022-01-25 21:30:57 +05:30
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movl %e$a, %edi #
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roll \$5, %edi # rotl32(a,5)
|
|
|
|
addl %edi, %e$e # e += rotl32(a,5)
|
2022-01-03 17:30:07 +05:30
|
|
|
rorl \$2, %e$b # b = rotl32(b,30)
|
|
|
|
"
|
|
|
|
}
|
|
|
|
RD1B() {
|
|
|
|
local a=$1;local b=$2;local c=$3;local d=$4;local e=$5
|
|
|
|
local n=$(($6))
|
|
|
|
local n13=$(((n+13) & 15))
|
|
|
|
local n8=$(((n+8) & 15))
|
|
|
|
local n2=$(((n+2) & 15))
|
|
|
|
local n0=$(((n+0) & 15))
|
|
|
|
echo "
|
|
|
|
# $n
|
|
|
|
movl %e$c, %edi # c
|
|
|
|
xorl %e$d, %edi # ^d
|
|
|
|
andl %e$b, %edi # &b
|
|
|
|
xorl %e$d, %edi # (((c ^ d) & b) ^ d)
|
2022-01-23 13:57:30 +05:30
|
|
|
addl -64+4*$n0(%rsp), %e$e # e += RCONST + W[n & 15]
|
2022-01-03 17:30:07 +05:30
|
|
|
addl %edi, %e$e # e += (((c ^ d) & b) ^ d)
|
|
|
|
movl %e$a, %esi #
|
|
|
|
roll \$5, %esi # rotl32(a,5)
|
|
|
|
addl %esi, %e$e # e += rotl32(a,5)
|
|
|
|
rorl \$2, %e$b # b = rotl32(b,30)
|
|
|
|
"
|
|
|
|
}
|
|
|
|
|
|
|
|
RD2() {
|
|
|
|
local a=$1;local b=$2;local c=$3;local d=$4;local e=$5
|
|
|
|
local n=$(($6))
|
|
|
|
local n13=$(((n+13) & 15))
|
|
|
|
local n8=$(((n+8) & 15))
|
|
|
|
local n2=$(((n+2) & 15))
|
|
|
|
local n0=$(((n+0) & 15))
|
|
|
|
echo "
|
|
|
|
# $n
|
|
|
|
movl %e$c, %edi # c
|
|
|
|
xorl %e$d, %edi # ^d
|
|
|
|
xorl %e$b, %edi # ^b
|
2022-01-23 13:57:30 +05:30
|
|
|
addl -64+4*$n0(%rsp), %e$e # e += RCONST + W[n & 15]
|
2022-01-03 17:30:07 +05:30
|
|
|
addl %edi, %e$e # e += (c ^ d ^ b)
|
|
|
|
movl %e$a, %esi #
|
|
|
|
roll \$5, %esi # rotl32(a,5)
|
|
|
|
addl %esi, %e$e # e += rotl32(a,5)
|
|
|
|
rorl \$2, %e$b # b = rotl32(b,30)
|
|
|
|
"
|
|
|
|
}
|
|
|
|
|
|
|
|
RD3() {
|
|
|
|
local a=$1;local b=$2;local c=$3;local d=$4;local e=$5
|
|
|
|
local n=$(($6))
|
|
|
|
local n13=$(((n+13) & 15))
|
|
|
|
local n8=$(((n+8) & 15))
|
|
|
|
local n2=$(((n+2) & 15))
|
|
|
|
local n0=$(((n+0) & 15))
|
|
|
|
echo "
|
|
|
|
# $n
|
|
|
|
movl %e$b, %edi # di: b
|
|
|
|
movl %e$b, %esi # si: b
|
|
|
|
orl %e$c, %edi # di: b | c
|
|
|
|
andl %e$c, %esi # si: b & c
|
|
|
|
andl %e$d, %edi # di: (b | c) & d
|
|
|
|
orl %esi, %edi # ((b | c) & d) | (b & c)
|
|
|
|
addl %edi, %e$e # += ((b | c) & d) | (b & c)
|
2022-01-23 13:57:30 +05:30
|
|
|
addl -64+4*$n0(%rsp), %e$e # e += RCONST + W[n & 15]
|
2022-01-03 17:30:07 +05:30
|
|
|
movl %e$a, %esi #
|
|
|
|
roll \$5, %esi # rotl32(a,5)
|
|
|
|
addl %esi, %e$e # e += rotl32(a,5)
|
|
|
|
rorl \$2, %e$b # b = rotl32(b,30)
|
|
|
|
"
|
|
|
|
}
|
2022-01-23 13:57:30 +05:30
|
|
|
|
2022-01-03 17:30:07 +05:30
|
|
|
{
|
2022-01-23 13:57:30 +05:30
|
|
|
# Round 1
|
|
|
|
RCONST=0x5A827999
|
|
|
|
RD1A ax bx cx dx bp 0; RD1A bp ax bx cx dx 1; RD1A dx bp ax bx cx 2; RD1A cx dx bp ax bx 3;
|
|
|
|
RD1A bx cx dx bp ax 4; RD1A ax bx cx dx bp 5; RD1A bp ax bx cx dx 6; RD1A dx bp ax bx cx 7;
|
|
|
|
a=`PREP %xmm0 %xmm1 %xmm2 %xmm3 "-64+16*0(%rsp)"`
|
|
|
|
b=`RD1A cx dx bp ax bx 8; RD1A bx cx dx bp ax 9; RD1A ax bx cx dx bp 10; RD1A bp ax bx cx dx 11;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
|
|
|
a=`echo " movaps rconst0x6ED9EBA1(%rip), $xmmRCONST"
|
|
|
|
PREP %xmm1 %xmm2 %xmm3 %xmm0 "-64+16*1(%rsp)"`
|
|
|
|
b=`RD1A dx bp ax bx cx 12; RD1A cx dx bp ax bx 13; RD1A bx cx dx bp ax 14; RD1A ax bx cx dx bp 15;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
|
|
|
a=`PREP %xmm2 %xmm3 %xmm0 %xmm1 "-64+16*2(%rsp)"`
|
|
|
|
b=`RD1B bp ax bx cx dx 16; RD1B dx bp ax bx cx 17; RD1B cx dx bp ax bx 18; RD1B bx cx dx bp ax 19;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
|
|
|
|
|
|
|
# Round 2
|
|
|
|
RCONST=0x6ED9EBA1
|
|
|
|
a=`PREP %xmm3 %xmm0 %xmm1 %xmm2 "-64+16*3(%rsp)"`
|
|
|
|
b=`RD2 ax bx cx dx bp 20; RD2 bp ax bx cx dx 21; RD2 dx bp ax bx cx 22; RD2 cx dx bp ax bx 23;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
|
|
|
a=`PREP %xmm0 %xmm1 %xmm2 %xmm3 "-64+16*0(%rsp)"`
|
|
|
|
b=`RD2 bx cx dx bp ax 24; RD2 ax bx cx dx bp 25; RD2 bp ax bx cx dx 26; RD2 dx bp ax bx cx 27;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
|
|
|
a=`PREP %xmm1 %xmm2 %xmm3 %xmm0 "-64+16*1(%rsp)"`
|
|
|
|
b=`RD2 cx dx bp ax bx 28; RD2 bx cx dx bp ax 29; RD2 ax bx cx dx bp 30; RD2 bp ax bx cx dx 31;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
|
|
|
a=`echo " movaps rconst0x8F1BBCDC(%rip), $xmmRCONST"
|
|
|
|
PREP %xmm2 %xmm3 %xmm0 %xmm1 "-64+16*2(%rsp)"`
|
|
|
|
b=`RD2 dx bp ax bx cx 32; RD2 cx dx bp ax bx 33; RD2 bx cx dx bp ax 34; RD2 ax bx cx dx bp 35;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
|
|
|
a=`PREP %xmm3 %xmm0 %xmm1 %xmm2 "-64+16*3(%rsp)"`
|
|
|
|
b=`RD2 bp ax bx cx dx 36; RD2 dx bp ax bx cx 37; RD2 cx dx bp ax bx 38; RD2 bx cx dx bp ax 39;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
|
|
|
|
|
|
|
# Round 3
|
|
|
|
RCONST=0x8F1BBCDC
|
|
|
|
a=`PREP %xmm0 %xmm1 %xmm2 %xmm3 "-64+16*0(%rsp)"`
|
|
|
|
b=`RD3 ax bx cx dx bp 40; RD3 bp ax bx cx dx 41; RD3 dx bp ax bx cx 42; RD3 cx dx bp ax bx 43;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
|
|
|
a=`PREP %xmm1 %xmm2 %xmm3 %xmm0 "-64+16*1(%rsp)"`
|
|
|
|
b=`RD3 bx cx dx bp ax 44; RD3 ax bx cx dx bp 45; RD3 bp ax bx cx dx 46; RD3 dx bp ax bx cx 47;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
|
|
|
a=`PREP %xmm2 %xmm3 %xmm0 %xmm1 "-64+16*2(%rsp)"`
|
|
|
|
b=`RD3 cx dx bp ax bx 48; RD3 bx cx dx bp ax 49; RD3 ax bx cx dx bp 50; RD3 bp ax bx cx dx 51;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
|
|
|
a=`echo " movaps rconst0xCA62C1D6(%rip), $xmmRCONST"
|
|
|
|
PREP %xmm3 %xmm0 %xmm1 %xmm2 "-64+16*3(%rsp)"`
|
|
|
|
b=`RD3 dx bp ax bx cx 52; RD3 cx dx bp ax bx 53; RD3 bx cx dx bp ax 54; RD3 ax bx cx dx bp 55;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
|
|
|
a=`PREP %xmm0 %xmm1 %xmm2 %xmm3 "-64+16*0(%rsp)"`
|
|
|
|
b=`RD3 bp ax bx cx dx 56; RD3 dx bp ax bx cx 57; RD3 cx dx bp ax bx 58; RD3 bx cx dx bp ax 59;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
2022-01-03 17:30:07 +05:30
|
|
|
|
|
|
|
# Round 4 has the same logic as round 2, only n and RCONST are different
|
2022-01-23 13:57:30 +05:30
|
|
|
RCONST=0xCA62C1D6
|
|
|
|
a=`PREP %xmm1 %xmm2 %xmm3 %xmm0 "-64+16*1(%rsp)"`
|
|
|
|
b=`RD2 ax bx cx dx bp 60; RD2 bp ax bx cx dx 61; RD2 dx bp ax bx cx 62; RD2 cx dx bp ax bx 63;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
|
|
|
a=`PREP %xmm2 %xmm3 %xmm0 %xmm1 "-64+16*2(%rsp)"`
|
|
|
|
b=`RD2 bx cx dx bp ax 64; RD2 ax bx cx dx bp 65; RD2 bp ax bx cx dx 66; RD2 dx bp ax bx cx 67;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
|
|
|
a=`PREP %xmm3 %xmm0 %xmm1 %xmm2 "-64+16*3(%rsp)"`
|
|
|
|
b=`RD2 cx dx bp ax bx 68; RD2 bx cx dx bp ax 69; RD2 ax bx cx dx bp 70; RD2 bp ax bx cx dx 71;`
|
|
|
|
INTERLEAVE "$a" "$b"
|
|
|
|
RD2 dx bp ax bx cx 72; RD2 cx dx bp ax bx 73; RD2 bx cx dx bp ax 74; RD2 ax bx cx dx bp 75;
|
|
|
|
RD2 bp ax bx cx dx 76; RD2 dx bp ax bx cx 77; RD2 cx dx bp ax bx 78; RD2 bx cx dx bp ax 79;
|
2022-01-03 17:30:07 +05:30
|
|
|
} | grep -v '^$'
|
|
|
|
|
|
|
|
echo "
|
|
|
|
popq %rdi #
|
2022-01-04 06:15:13 +05:30
|
|
|
popq %r12 #
|
2022-01-08 05:11:09 +05:30
|
|
|
addl %eax, 80(%rdi) # ctx->hash[0] += a
|
2022-01-04 06:15:13 +05:30
|
|
|
popq %r13 #
|
2022-01-08 05:11:09 +05:30
|
|
|
addl %ebx, 84(%rdi) # ctx->hash[1] += b
|
2022-01-04 06:15:13 +05:30
|
|
|
popq %r14 #
|
2022-01-08 05:11:09 +05:30
|
|
|
addl %ecx, 88(%rdi) # ctx->hash[2] += c
|
2022-01-25 21:30:57 +05:30
|
|
|
# popq %r15 #
|
2022-01-08 05:11:09 +05:30
|
|
|
addl %edx, 92(%rdi) # ctx->hash[3] += d
|
2022-01-03 17:30:07 +05:30
|
|
|
popq %rbx #
|
2022-01-08 05:11:09 +05:30
|
|
|
addl %ebp, 96(%rdi) # ctx->hash[4] += e
|
2022-01-03 17:30:07 +05:30
|
|
|
popq %rbp #
|
|
|
|
|
|
|
|
ret
|
|
|
|
.size sha1_process_block64, .-sha1_process_block64
|
2022-01-23 13:57:30 +05:30
|
|
|
|
|
|
|
.section .rodata.cst16.sha1const, \"aM\", @progbits, 16
|
|
|
|
.align 16
|
|
|
|
rconst0x5A827999:
|
|
|
|
.long 0x5A827999
|
|
|
|
.long 0x5A827999
|
|
|
|
.long 0x5A827999
|
|
|
|
.long 0x5A827999
|
|
|
|
rconst0x6ED9EBA1:
|
|
|
|
.long 0x6ED9EBA1
|
|
|
|
.long 0x6ED9EBA1
|
|
|
|
.long 0x6ED9EBA1
|
|
|
|
.long 0x6ED9EBA1
|
|
|
|
rconst0x8F1BBCDC:
|
|
|
|
.long 0x8F1BBCDC
|
|
|
|
.long 0x8F1BBCDC
|
|
|
|
.long 0x8F1BBCDC
|
|
|
|
.long 0x8F1BBCDC
|
|
|
|
rconst0xCA62C1D6:
|
|
|
|
.long 0xCA62C1D6
|
|
|
|
.long 0xCA62C1D6
|
|
|
|
.long 0xCA62C1D6
|
|
|
|
.long 0xCA62C1D6
|
|
|
|
|
2022-01-03 17:30:07 +05:30
|
|
|
#endif"
|