When using GNU Make >=4.3, the KBUILD_STR() definition interferes badly
with dependency checks during build, and forces a complete rebuild every
time Make runs.
In if_changed_rule, Kconfig checks if the command used to build a file
has changed since last execution. The previous command is stored in the
generated .<file>.o.cmd file. For example applets/.applets.o.cmd defines
a "cmd_applets/applets.o" variable:
cmd_applets/applets.o := gcc ... -D"KBUILD_STR(s)=#s" ...
Here the '#' should be escaped with a backslash, otherwise GNU Make
interprets it as starting a comment, and ignore the rest of the
variable. As a result of this truncation, the previous command doesn't
equal the new command and Make rebuilds each target.
The problem started to appear when GNU Make 4.3 (released January 2020),
introduced a backward-incompatible fix to macros containing a '#'. While
the above use of '#', a simple Make variable, still needs to be escaped,
a '#' within a function invocation doesn't need to be escaped anymore.
As Martin Dorey explained on the GNU Make discussion [1], the above
declaration is generated from make-cmd, defined as:
make-cmd = $(subst \#,\\\#,$(subst $$,$$$$,$(call escsq,$(cmd_$(1))))
Since GNU Make 4.3, the first argument of subst should not have a
backslash. make-cmd now looks for literally \# and doesn't find it, and
as a result doesn't add the backslash when generating .o.cmd files.
[1] http://savannah.gnu.org/bugs/?20513
We could fix it by changing make-cmd to "$(subst #,\#,...)", but to
avoid compatibility headaches, simply get rid of the KBUILD_STR
definition, as done in Linux by b42841b7bb62 ("kbuild: Get rid of
KBUILD_STR"). Quote the string arguments directly rather than asking the
preprocessor to quote them.
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: Denys Vlasenko <vda.linux@googlemail.com>
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