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Linux 6.1.31 headers

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pepe
2023-06-07 11:35:51 +00:00
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156
misc/cxl.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
/*
* Copyright 2014 IBM Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef _MISC_CXL_H
#define _MISC_CXL_H
#include <linux/types.h>
#include <linux/ioctl.h>
struct cxl_ioctl_start_work {
__u64 flags;
__u64 work_element_descriptor;
__u64 amr;
__s16 num_interrupts;
__u16 tid;
__s32 reserved1;
__u64 reserved2;
__u64 reserved3;
__u64 reserved4;
__u64 reserved5;
};
#define CXL_START_WORK_AMR 0x0000000000000001ULL
#define CXL_START_WORK_NUM_IRQS 0x0000000000000002ULL
#define CXL_START_WORK_ERR_FF 0x0000000000000004ULL
#define CXL_START_WORK_TID 0x0000000000000008ULL
#define CXL_START_WORK_ALL (CXL_START_WORK_AMR |\
CXL_START_WORK_NUM_IRQS |\
CXL_START_WORK_ERR_FF |\
CXL_START_WORK_TID)
/* Possible modes that an afu can be in */
#define CXL_MODE_DEDICATED 0x1
#define CXL_MODE_DIRECTED 0x2
/* possible flags for the cxl_afu_id flags field */
#define CXL_AFUID_FLAG_SLAVE 0x1 /* In directed-mode afu is in slave mode */
struct cxl_afu_id {
__u64 flags; /* One of CXL_AFUID_FLAG_X */
__u32 card_id;
__u32 afu_offset;
__u32 afu_mode; /* one of the CXL_MODE_X */
__u32 reserved1;
__u64 reserved2;
__u64 reserved3;
__u64 reserved4;
__u64 reserved5;
__u64 reserved6;
};
/* base adapter image header is included in the image */
#define CXL_AI_NEED_HEADER 0x0000000000000001ULL
#define CXL_AI_ALL CXL_AI_NEED_HEADER
#define CXL_AI_HEADER_SIZE 128
#define CXL_AI_BUFFER_SIZE 4096
#define CXL_AI_MAX_ENTRIES 256
#define CXL_AI_MAX_CHUNK_SIZE (CXL_AI_BUFFER_SIZE * CXL_AI_MAX_ENTRIES)
struct cxl_adapter_image {
__u64 flags;
__u64 data;
__u64 len_data;
__u64 len_image;
__u64 reserved1;
__u64 reserved2;
__u64 reserved3;
__u64 reserved4;
};
/* ioctl numbers */
#define CXL_MAGIC 0xCA
/* AFU devices */
#define CXL_IOCTL_START_WORK _IOW(CXL_MAGIC, 0x00, struct cxl_ioctl_start_work)
#define CXL_IOCTL_GET_PROCESS_ELEMENT _IOR(CXL_MAGIC, 0x01, __u32)
#define CXL_IOCTL_GET_AFU_ID _IOR(CXL_MAGIC, 0x02, struct cxl_afu_id)
/* adapter devices */
#define CXL_IOCTL_DOWNLOAD_IMAGE _IOW(CXL_MAGIC, 0x0A, struct cxl_adapter_image)
#define CXL_IOCTL_VALIDATE_IMAGE _IOW(CXL_MAGIC, 0x0B, struct cxl_adapter_image)
#define CXL_READ_MIN_SIZE 0x1000 /* 4K */
/* Events from read() */
enum cxl_event_type {
CXL_EVENT_RESERVED = 0,
CXL_EVENT_AFU_INTERRUPT = 1,
CXL_EVENT_DATA_STORAGE = 2,
CXL_EVENT_AFU_ERROR = 3,
CXL_EVENT_AFU_DRIVER = 4,
};
struct cxl_event_header {
__u16 type;
__u16 size;
__u16 process_element;
__u16 reserved1;
};
struct cxl_event_afu_interrupt {
__u16 flags;
__u16 irq; /* Raised AFU interrupt number */
__u32 reserved1;
};
struct cxl_event_data_storage {
__u16 flags;
__u16 reserved1;
__u32 reserved2;
__u64 addr;
__u64 dsisr;
__u64 reserved3;
};
struct cxl_event_afu_error {
__u16 flags;
__u16 reserved1;
__u32 reserved2;
__u64 error;
};
struct cxl_event_afu_driver_reserved {
/*
* Defines the buffer passed to the cxl driver by the AFU driver.
*
* This is not ABI since the event header.size passed to the user for
* existing events is set in the read call to sizeof(cxl_event_header)
* + sizeof(whatever event is being dispatched) and the user is already
* required to use a 4K buffer on the read call.
*
* Of course the contents will be ABI, but that's up the AFU driver.
*/
__u32 data_size;
__u8 data[];
};
struct cxl_event {
struct cxl_event_header header;
union {
struct cxl_event_afu_interrupt irq;
struct cxl_event_data_storage fault;
struct cxl_event_afu_error afu_error;
struct cxl_event_afu_driver_reserved afu_driver_event;
};
};
#endif /* _MISC_CXL_H */

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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef __QCOM_FASTRPC_H__
#define __QCOM_FASTRPC_H__
#include <linux/types.h>
#define FASTRPC_IOCTL_ALLOC_DMA_BUFF _IOWR('R', 1, struct fastrpc_alloc_dma_buf)
#define FASTRPC_IOCTL_FREE_DMA_BUFF _IOWR('R', 2, __u32)
#define FASTRPC_IOCTL_INVOKE _IOWR('R', 3, struct fastrpc_invoke)
#define FASTRPC_IOCTL_INIT_ATTACH _IO('R', 4)
#define FASTRPC_IOCTL_INIT_CREATE _IOWR('R', 5, struct fastrpc_init_create)
#define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct fastrpc_req_mmap)
#define FASTRPC_IOCTL_MUNMAP _IOWR('R', 7, struct fastrpc_req_munmap)
#define FASTRPC_IOCTL_INIT_ATTACH_SNS _IO('R', 8)
#define FASTRPC_IOCTL_MEM_MAP _IOWR('R', 10, struct fastrpc_mem_map)
#define FASTRPC_IOCTL_MEM_UNMAP _IOWR('R', 11, struct fastrpc_mem_unmap)
#define FASTRPC_IOCTL_GET_DSP_INFO _IOWR('R', 13, struct fastrpc_ioctl_capability)
/**
* enum fastrpc_map_flags - control flags for mapping memory on DSP user process
* @FASTRPC_MAP_STATIC: Map memory pages with RW- permission and CACHE WRITEBACK.
* The driver is responsible for cache maintenance when passed
* the buffer to FastRPC calls. Same virtual address will be
* assigned for subsequent FastRPC calls.
* @FASTRPC_MAP_RESERVED: Reserved
* @FASTRPC_MAP_FD: Map memory pages with RW- permission and CACHE WRITEBACK.
* Mapping tagged with a file descriptor. User is responsible for
* CPU and DSP cache maintenance for the buffer. Get virtual address
* of buffer on DSP using HAP_mmap_get() and HAP_mmap_put() APIs.
* @FASTRPC_MAP_FD_DELAYED: Mapping delayed until user call HAP_mmap() and HAP_munmap()
* functions on DSP. It is useful to map a buffer with cache modes
* other than default modes. User is responsible for CPU and DSP
* cache maintenance for the buffer.
* @FASTRPC_MAP_FD_NOMAP: This flag is used to skip CPU mapping,
* otherwise behaves similar to FASTRPC_MAP_FD_DELAYED flag.
* @FASTRPC_MAP_MAX: max count for flags
*
*/
enum fastrpc_map_flags {
FASTRPC_MAP_STATIC = 0,
FASTRPC_MAP_RESERVED,
FASTRPC_MAP_FD = 2,
FASTRPC_MAP_FD_DELAYED,
FASTRPC_MAP_FD_NOMAP = 16,
FASTRPC_MAP_MAX,
};
enum fastrpc_proc_attr {
/* Macro for Debug attr */
FASTRPC_MODE_DEBUG = (1 << 0),
/* Macro for Ptrace */
FASTRPC_MODE_PTRACE = (1 << 1),
/* Macro for CRC Check */
FASTRPC_MODE_CRC = (1 << 2),
/* Macro for Unsigned PD */
FASTRPC_MODE_UNSIGNED_MODULE = (1 << 3),
/* Macro for Adaptive QoS */
FASTRPC_MODE_ADAPTIVE_QOS = (1 << 4),
/* Macro for System Process */
FASTRPC_MODE_SYSTEM_PROCESS = (1 << 5),
/* Macro for Prvileged Process */
FASTRPC_MODE_PRIVILEGED = (1 << 6),
};
/* Fastrpc attribute for memory protection of buffers */
#define FASTRPC_ATTR_SECUREMAP (1)
struct fastrpc_invoke_args {
__u64 ptr;
__u64 length;
__s32 fd;
__u32 attr;
};
struct fastrpc_invoke {
__u32 handle;
__u32 sc;
__u64 args;
};
struct fastrpc_init_create {
__u32 filelen; /* elf file length */
__s32 filefd; /* fd for the file */
__u32 attrs;
__u32 siglen;
__u64 file; /* pointer to elf file */
};
struct fastrpc_alloc_dma_buf {
__s32 fd; /* fd */
__u32 flags; /* flags to map with */
__u64 size; /* size */
};
struct fastrpc_req_mmap {
__s32 fd;
__u32 flags; /* flags for dsp to map with */
__u64 vaddrin; /* optional virtual address */
__u64 size; /* size */
__u64 vaddrout; /* dsp virtual address */
};
struct fastrpc_mem_map {
__s32 version;
__s32 fd; /* fd */
__s32 offset; /* buffer offset */
__u32 flags; /* flags defined in enum fastrpc_map_flags */
__u64 vaddrin; /* buffer virtual address */
__u64 length; /* buffer length */
__u64 vaddrout; /* [out] remote virtual address */
__s32 attrs; /* buffer attributes used for SMMU mapping */
__s32 reserved[4];
};
struct fastrpc_req_munmap {
__u64 vaddrout; /* address to unmap */
__u64 size; /* size */
};
struct fastrpc_mem_unmap {
__s32 vesion;
__s32 fd; /* fd */
__u64 vaddr; /* remote process (dsp) virtual address */
__u64 length; /* buffer size */
__s32 reserved[5];
};
struct fastrpc_ioctl_capability {
__u32 domain;
__u32 attribute_id;
__u32 capability; /* dsp capability */
__u32 reserved[4];
};
#endif /* __QCOM_FASTRPC_H__ */

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/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
/* Copyright 2017 IBM Corp. */
#ifndef _MISC_OCXL_H
#define _MISC_OCXL_H
#include <linux/types.h>
#include <linux/ioctl.h>
enum ocxl_event_type {
OCXL_AFU_EVENT_XSL_FAULT_ERROR = 0,
};
#define OCXL_KERNEL_EVENT_FLAG_LAST 0x0001 /* This is the last event pending */
struct ocxl_kernel_event_header {
__u16 type;
__u16 flags;
__u32 reserved;
};
struct ocxl_kernel_event_xsl_fault_error {
__u64 addr;
__u64 dsisr;
__u64 count;
__u64 reserved;
};
struct ocxl_ioctl_attach {
__u64 amr;
__u64 reserved1;
__u64 reserved2;
__u64 reserved3;
};
struct ocxl_ioctl_metadata {
__u16 version; /* struct version, always backwards compatible */
/* Version 0 fields */
__u8 afu_version_major;
__u8 afu_version_minor;
__u32 pasid; /* PASID assigned to the current context */
__u64 pp_mmio_size; /* Per PASID MMIO size */
__u64 global_mmio_size;
/* End version 0 fields */
__u64 reserved[13]; /* Total of 16*u64 */
};
struct ocxl_ioctl_p9_wait {
__u16 thread_id; /* The thread ID required to wake this thread */
__u16 reserved1;
__u32 reserved2;
__u64 reserved3[3];
};
#define OCXL_IOCTL_FEATURES_FLAGS0_P9_WAIT 0x01
struct ocxl_ioctl_features {
__u64 flags[4];
};
struct ocxl_ioctl_irq_fd {
__u64 irq_offset;
__s32 eventfd;
__u32 reserved;
};
/* ioctl numbers */
#define OCXL_MAGIC 0xCA
/* AFU devices */
#define OCXL_IOCTL_ATTACH _IOW(OCXL_MAGIC, 0x10, struct ocxl_ioctl_attach)
#define OCXL_IOCTL_IRQ_ALLOC _IOR(OCXL_MAGIC, 0x11, __u64)
#define OCXL_IOCTL_IRQ_FREE _IOW(OCXL_MAGIC, 0x12, __u64)
#define OCXL_IOCTL_IRQ_SET_FD _IOW(OCXL_MAGIC, 0x13, struct ocxl_ioctl_irq_fd)
#define OCXL_IOCTL_GET_METADATA _IOR(OCXL_MAGIC, 0x14, struct ocxl_ioctl_metadata)
#define OCXL_IOCTL_ENABLE_P9_WAIT _IOR(OCXL_MAGIC, 0x15, struct ocxl_ioctl_p9_wait)
#define OCXL_IOCTL_GET_FEATURES _IOR(OCXL_MAGIC, 0x16, struct ocxl_ioctl_features)
#endif /* _MISC_OCXL_H */

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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef __PVPANIC_H__
#define __PVPANIC_H__
#define PVPANIC_PANICKED (1 << 0)
#define PVPANIC_CRASH_LOADED (1 << 1)
#endif /* __PVPANIC_H__ */

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misc/uacce/hisi_qm.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
#ifndef _HISI_QM_H
#define _HISI_QM_H
#include <linux/types.h>
/**
* struct hisi_qp_ctx - User data for hisi qp.
* @id: qp_index return to user space
* @qc_type: Accelerator algorithm type
*/
struct hisi_qp_ctx {
__u16 id;
__u16 qc_type;
};
/**
* struct hisi_qp_info - User data for hisi qp.
* @sqe_size: Submission queue element size
* @sq_depth: The number of sqe
* @cq_depth: The number of cqe
* @reserved: Reserved data
*/
struct hisi_qp_info {
__u32 sqe_size;
__u16 sq_depth;
__u16 cq_depth;
__u64 reserved;
};
#define HISI_QM_API_VER_BASE "hisi_qm_v1"
#define HISI_QM_API_VER2_BASE "hisi_qm_v2"
#define HISI_QM_API_VER3_BASE "hisi_qm_v3"
/* UACCE_CMD_QM_SET_QP_CTX: Set qp algorithm type */
#define UACCE_CMD_QM_SET_QP_CTX _IOWR('H', 10, struct hisi_qp_ctx)
/* UACCE_CMD_QM_SET_QP_INFO: Set qp depth and BD size */
#define UACCE_CMD_QM_SET_QP_INFO _IOWR('H', 11, struct hisi_qp_info)
#endif

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/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
#ifndef UUACCE_H
#define UUACCE_H
#include <linux/types.h>
#include <linux/ioctl.h>
/*
* UACCE_CMD_START_Q: Start queue
*/
#define UACCE_CMD_START_Q _IO('W', 0)
/*
* UACCE_CMD_PUT_Q:
* User actively stop queue and free queue resource immediately
* Optimization method since close fd may delay
*/
#define UACCE_CMD_PUT_Q _IO('W', 1)
/*
* UACCE Device flags:
* UACCE_DEV_SVA: Shared Virtual Addresses
* Support PASID
* Support device page faults (PCI PRI or SMMU Stall)
*/
#define UACCE_DEV_SVA BIT(0)
/**
* enum uacce_qfrt: queue file region type
* @UACCE_QFRT_MMIO: device mmio region
* @UACCE_QFRT_DUS: device user share region
*/
enum uacce_qfrt {
UACCE_QFRT_MMIO = 0,
UACCE_QFRT_DUS = 1,
};
#endif

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/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
/*
* Xilinx SD-FEC
*
* Copyright (C) 2019 Xilinx, Inc.
*
* Description:
* This driver is developed for SDFEC16 IP. It provides a char device
* in sysfs and supports file operations like open(), close() and ioctl().
*/
#ifndef __XILINX_SDFEC_H__
#define __XILINX_SDFEC_H__
#include <linux/types.h>
/* Shared LDPC Tables */
#define XSDFEC_LDPC_SC_TABLE_ADDR_BASE (0x10000)
#define XSDFEC_LDPC_SC_TABLE_ADDR_HIGH (0x10400)
#define XSDFEC_LDPC_LA_TABLE_ADDR_BASE (0x18000)
#define XSDFEC_LDPC_LA_TABLE_ADDR_HIGH (0x19000)
#define XSDFEC_LDPC_QC_TABLE_ADDR_BASE (0x20000)
#define XSDFEC_LDPC_QC_TABLE_ADDR_HIGH (0x28000)
/* LDPC tables depth */
#define XSDFEC_SC_TABLE_DEPTH \
(XSDFEC_LDPC_SC_TABLE_ADDR_HIGH - XSDFEC_LDPC_SC_TABLE_ADDR_BASE)
#define XSDFEC_LA_TABLE_DEPTH \
(XSDFEC_LDPC_LA_TABLE_ADDR_HIGH - XSDFEC_LDPC_LA_TABLE_ADDR_BASE)
#define XSDFEC_QC_TABLE_DEPTH \
(XSDFEC_LDPC_QC_TABLE_ADDR_HIGH - XSDFEC_LDPC_QC_TABLE_ADDR_BASE)
/**
* enum xsdfec_code - Code Type.
* @XSDFEC_TURBO_CODE: Driver is configured for Turbo mode.
* @XSDFEC_LDPC_CODE: Driver is configured for LDPC mode.
*
* This enum is used to indicate the mode of the driver. The mode is determined
* by checking which codes are set in the driver. Note that the mode cannot be
* changed by the driver.
*/
enum xsdfec_code {
XSDFEC_TURBO_CODE = 0,
XSDFEC_LDPC_CODE,
};
/**
* enum xsdfec_order - Order
* @XSDFEC_MAINTAIN_ORDER: Maintain order execution of blocks.
* @XSDFEC_OUT_OF_ORDER: Out-of-order execution of blocks.
*
* This enum is used to indicate whether the order of blocks can change from
* input to output.
*/
enum xsdfec_order {
XSDFEC_MAINTAIN_ORDER = 0,
XSDFEC_OUT_OF_ORDER,
};
/**
* enum xsdfec_turbo_alg - Turbo Algorithm Type.
* @XSDFEC_MAX_SCALE: Max Log-Map algorithm with extrinsic scaling. When
* scaling is set to this is equivalent to the Max Log-Map
* algorithm.
* @XSDFEC_MAX_STAR: Log-Map algorithm.
* @XSDFEC_TURBO_ALG_MAX: Used to indicate out of bound Turbo algorithms.
*
* This enum specifies which Turbo Decode algorithm is in use.
*/
enum xsdfec_turbo_alg {
XSDFEC_MAX_SCALE = 0,
XSDFEC_MAX_STAR,
XSDFEC_TURBO_ALG_MAX,
};
/**
* enum xsdfec_state - State.
* @XSDFEC_INIT: Driver is initialized.
* @XSDFEC_STARTED: Driver is started.
* @XSDFEC_STOPPED: Driver is stopped.
* @XSDFEC_NEEDS_RESET: Driver needs to be reset.
* @XSDFEC_PL_RECONFIGURE: Programmable Logic needs to be recofigured.
*
* This enum is used to indicate the state of the driver.
*/
enum xsdfec_state {
XSDFEC_INIT = 0,
XSDFEC_STARTED,
XSDFEC_STOPPED,
XSDFEC_NEEDS_RESET,
XSDFEC_PL_RECONFIGURE,
};
/**
* enum xsdfec_axis_width - AXIS_WIDTH.DIN Setting for 128-bit width.
* @XSDFEC_1x128b: DIN data input stream consists of a 128-bit lane
* @XSDFEC_2x128b: DIN data input stream consists of two 128-bit lanes
* @XSDFEC_4x128b: DIN data input stream consists of four 128-bit lanes
*
* This enum is used to indicate the AXIS_WIDTH.DIN setting for 128-bit width.
* The number of lanes of the DIN data input stream depends upon the
* AXIS_WIDTH.DIN parameter.
*/
enum xsdfec_axis_width {
XSDFEC_1x128b = 1,
XSDFEC_2x128b = 2,
XSDFEC_4x128b = 4,
};
/**
* enum xsdfec_axis_word_include - Words Configuration.
* @XSDFEC_FIXED_VALUE: Fixed, the DIN_WORDS AXI4-Stream interface is removed
* from the IP instance and is driven with the specified
* number of words.
* @XSDFEC_IN_BLOCK: In Block, configures the IP instance to expect a single
* DIN_WORDS value per input code block. The DIN_WORDS
* interface is present.
* @XSDFEC_PER_AXI_TRANSACTION: Per Transaction, configures the IP instance to
* expect one DIN_WORDS value per input transaction on the DIN interface. The
* DIN_WORDS interface is present.
* @XSDFEC_AXIS_WORDS_INCLUDE_MAX: Used to indicate out of bound Words
* Configurations.
*
* This enum is used to specify the DIN_WORDS configuration.
*/
enum xsdfec_axis_word_include {
XSDFEC_FIXED_VALUE = 0,
XSDFEC_IN_BLOCK,
XSDFEC_PER_AXI_TRANSACTION,
XSDFEC_AXIS_WORDS_INCLUDE_MAX,
};
/**
* struct xsdfec_turbo - User data for Turbo codes.
* @alg: Specifies which Turbo decode algorithm to use
* @scale: Specifies the extrinsic scaling to apply when the Max Scale algorithm
* has been selected
*
* Turbo code structure to communicate parameters to XSDFEC driver.
*/
struct xsdfec_turbo {
__u32 alg;
__u8 scale;
};
/**
* struct xsdfec_ldpc_params - User data for LDPC codes.
* @n: Number of code word bits
* @k: Number of information bits
* @psize: Size of sub-matrix
* @nlayers: Number of layers in code
* @nqc: Quasi Cyclic Number
* @nmqc: Number of M-sized QC operations in parity check matrix
* @nm: Number of M-size vectors in N
* @norm_type: Normalization required or not
* @no_packing: Determines if multiple QC ops should be performed
* @special_qc: Sub-Matrix property for Circulant weight > 0
* @no_final_parity: Decide if final parity check needs to be performed
* @max_schedule: Experimental code word scheduling limit
* @sc_off: SC offset
* @la_off: LA offset
* @qc_off: QC offset
* @sc_table: Pointer to SC Table which must be page aligned
* @la_table: Pointer to LA Table which must be page aligned
* @qc_table: Pointer to QC Table which must be page aligned
* @code_id: LDPC Code
*
* This structure describes the LDPC code that is passed to the driver by the
* application.
*/
struct xsdfec_ldpc_params {
__u32 n;
__u32 k;
__u32 psize;
__u32 nlayers;
__u32 nqc;
__u32 nmqc;
__u32 nm;
__u32 norm_type;
__u32 no_packing;
__u32 special_qc;
__u32 no_final_parity;
__u32 max_schedule;
__u32 sc_off;
__u32 la_off;
__u32 qc_off;
__u32 *sc_table;
__u32 *la_table;
__u32 *qc_table;
__u16 code_id;
};
/**
* struct xsdfec_status - Status of SD-FEC core.
* @state: State of the SD-FEC core
* @activity: Describes if the SD-FEC instance is Active
*/
struct xsdfec_status {
__u32 state;
__s8 activity;
};
/**
* struct xsdfec_irq - Enabling or Disabling Interrupts.
* @enable_isr: If true enables the ISR
* @enable_ecc_isr: If true enables the ECC ISR
*/
struct xsdfec_irq {
__s8 enable_isr;
__s8 enable_ecc_isr;
};
/**
* struct xsdfec_config - Configuration of SD-FEC core.
* @code: The codes being used by the SD-FEC instance
* @order: Order of Operation
* @din_width: Width of the DIN AXI4-Stream
* @din_word_include: How DIN_WORDS are inputted
* @dout_width: Width of the DOUT AXI4-Stream
* @dout_word_include: HOW DOUT_WORDS are outputted
* @irq: Enabling or disabling interrupts
* @bypass: Is the core being bypassed
* @code_wr_protect: Is write protection of LDPC codes enabled
*/
struct xsdfec_config {
__u32 code;
__u32 order;
__u32 din_width;
__u32 din_word_include;
__u32 dout_width;
__u32 dout_word_include;
struct xsdfec_irq irq;
__s8 bypass;
__s8 code_wr_protect;
};
/**
* struct xsdfec_stats - Stats retrived by ioctl XSDFEC_GET_STATS. Used
* to buffer atomic_t variables from struct
* xsdfec_dev. Counts are accumulated until
* the user clears them.
* @isr_err_count: Count of ISR errors
* @cecc_count: Count of Correctable ECC errors (SBE)
* @uecc_count: Count of Uncorrectable ECC errors (MBE)
*/
struct xsdfec_stats {
__u32 isr_err_count;
__u32 cecc_count;
__u32 uecc_count;
};
/**
* struct xsdfec_ldpc_param_table_sizes - Used to store sizes of SD-FEC table
* entries for an individual LPDC code
* parameter.
* @sc_size: Size of SC table used
* @la_size: Size of LA table used
* @qc_size: Size of QC table used
*/
struct xsdfec_ldpc_param_table_sizes {
__u32 sc_size;
__u32 la_size;
__u32 qc_size;
};
/*
* XSDFEC IOCTL List
*/
#define XSDFEC_MAGIC 'f'
/**
* DOC: XSDFEC_START_DEV
*
* @Description
*
* ioctl to start SD-FEC core
*
* This fails if the XSDFEC_SET_ORDER ioctl has not been previously called
*/
#define XSDFEC_START_DEV _IO(XSDFEC_MAGIC, 0)
/**
* DOC: XSDFEC_STOP_DEV
*
* @Description
*
* ioctl to stop the SD-FEC core
*/
#define XSDFEC_STOP_DEV _IO(XSDFEC_MAGIC, 1)
/**
* DOC: XSDFEC_GET_STATUS
*
* @Description
*
* ioctl that returns status of SD-FEC core
*/
#define XSDFEC_GET_STATUS _IOR(XSDFEC_MAGIC, 2, struct xsdfec_status)
/**
* DOC: XSDFEC_SET_IRQ
* @Parameters
*
* @struct xsdfec_irq *
* Pointer to the &struct xsdfec_irq that contains the interrupt settings
* for the SD-FEC core
*
* @Description
*
* ioctl to enable or disable irq
*/
#define XSDFEC_SET_IRQ _IOW(XSDFEC_MAGIC, 3, struct xsdfec_irq)
/**
* DOC: XSDFEC_SET_TURBO
* @Parameters
*
* @struct xsdfec_turbo *
* Pointer to the &struct xsdfec_turbo that contains the Turbo decode
* settings for the SD-FEC core
*
* @Description
*
* ioctl that sets the SD-FEC Turbo parameter values
*
* This can only be used when the driver is in the XSDFEC_STOPPED state
*/
#define XSDFEC_SET_TURBO _IOW(XSDFEC_MAGIC, 4, struct xsdfec_turbo)
/**
* DOC: XSDFEC_ADD_LDPC_CODE_PARAMS
* @Parameters
*
* @struct xsdfec_ldpc_params *
* Pointer to the &struct xsdfec_ldpc_params that contains the LDPC code
* parameters to be added to the SD-FEC Block
*
* @Description
* ioctl to add an LDPC code to the SD-FEC LDPC codes
*
* This can only be used when:
*
* - Driver is in the XSDFEC_STOPPED state
*
* - SD-FEC core is configured as LPDC
*
* - SD-FEC Code Write Protection is disabled
*/
#define XSDFEC_ADD_LDPC_CODE_PARAMS \
_IOW(XSDFEC_MAGIC, 5, struct xsdfec_ldpc_params)
/**
* DOC: XSDFEC_GET_CONFIG
* @Parameters
*
* @struct xsdfec_config *
* Pointer to the &struct xsdfec_config that contains the current
* configuration settings of the SD-FEC Block
*
* @Description
*
* ioctl that returns SD-FEC core configuration
*/
#define XSDFEC_GET_CONFIG _IOR(XSDFEC_MAGIC, 6, struct xsdfec_config)
/**
* DOC: XSDFEC_GET_TURBO
* @Parameters
*
* @struct xsdfec_turbo *
* Pointer to the &struct xsdfec_turbo that contains the current Turbo
* decode settings of the SD-FEC Block
*
* @Description
*
* ioctl that returns SD-FEC turbo param values
*/
#define XSDFEC_GET_TURBO _IOR(XSDFEC_MAGIC, 7, struct xsdfec_turbo)
/**
* DOC: XSDFEC_SET_ORDER
* @Parameters
*
* @struct unsigned long *
* Pointer to the unsigned long that contains a value from the
* @enum xsdfec_order
*
* @Description
*
* ioctl that sets order, if order of blocks can change from input to output
*
* This can only be used when the driver is in the XSDFEC_STOPPED state
*/
#define XSDFEC_SET_ORDER _IOW(XSDFEC_MAGIC, 8, unsigned long)
/**
* DOC: XSDFEC_SET_BYPASS
* @Parameters
*
* @struct bool *
* Pointer to bool that sets the bypass value, where false results in
* normal operation and false results in the SD-FEC performing the
* configured operations (same number of cycles) but output data matches
* the input data
*
* @Description
*
* ioctl that sets bypass.
*
* This can only be used when the driver is in the XSDFEC_STOPPED state
*/
#define XSDFEC_SET_BYPASS _IOW(XSDFEC_MAGIC, 9, bool)
/**
* DOC: XSDFEC_IS_ACTIVE
* @Parameters
*
* @struct bool *
* Pointer to bool that returns true if the SD-FEC is processing data
*
* @Description
*
* ioctl that determines if SD-FEC is processing data
*/
#define XSDFEC_IS_ACTIVE _IOR(XSDFEC_MAGIC, 10, bool)
/**
* DOC: XSDFEC_CLEAR_STATS
*
* @Description
*
* ioctl that clears error stats collected during interrupts
*/
#define XSDFEC_CLEAR_STATS _IO(XSDFEC_MAGIC, 11)
/**
* DOC: XSDFEC_GET_STATS
* @Parameters
*
* @struct xsdfec_stats *
* Pointer to the &struct xsdfec_stats that will contain the updated stats
* values
*
* @Description
*
* ioctl that returns SD-FEC core stats
*
* This can only be used when the driver is in the XSDFEC_STOPPED state
*/
#define XSDFEC_GET_STATS _IOR(XSDFEC_MAGIC, 12, struct xsdfec_stats)
/**
* DOC: XSDFEC_SET_DEFAULT_CONFIG
*
* @Description
*
* ioctl that returns SD-FEC core to default config, use after a reset
*
* This can only be used when the driver is in the XSDFEC_STOPPED state
*/
#define XSDFEC_SET_DEFAULT_CONFIG _IO(XSDFEC_MAGIC, 13)
#endif /* __XILINX_SDFEC_H__ */