SiS 496/497: Fix soft reset behavior, fixes #4319.
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@@ -388,8 +388,7 @@ sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
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break;
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break;
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case 0x67: /* Miscellaneous Control */
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case 0x67: /* Miscellaneous Control */
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dev->pci_conf[addr] = val & 0xf9;
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dev->pci_conf[addr] = val & 0xf9;
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if (valxor & 0x60)
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cpu_cpurst_on_sr = ((val & 0xa0) == 0x80) && !(dev->pci_conf[0xc6] & 0x08);
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port_92_set_features(dev->port_92, !!(val & 0x20), !!(val & 0x40));
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break;
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break;
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/* 86C497 Specific Registers (80h ~ FFh) */
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/* 86C497 Specific Registers (80h ~ FFh) */
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@@ -480,7 +479,7 @@ sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
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break;
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break;
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case 0xc6: /* 85C497 Post / INIT Configuration */
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case 0xc6: /* 85C497 Post / INIT Configuration */
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dev->pci_conf[addr] = val & 0x0f;
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dev->pci_conf[addr] = val & 0x0f;
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cpu_cpurst_on_sr = !(val & 0x08);
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cpu_cpurst_on_sr = ((dev->pci_conf[0x67] & 0xa0) == 0x80) && !(val & 0x08);
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soft_reset_pci = !!(val & 0x04);
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soft_reset_pci = !!(val & 0x04);
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break;
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break;
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case 0xc8:
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case 0xc8:
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@@ -610,6 +609,9 @@ sis_85c496_reset(void *priv)
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sis_85c49x_pci_write(0, 0xd0, 0x78, dev);
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sis_85c49x_pci_write(0, 0xd0, 0x78, dev);
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sis_85c49x_pci_write(0, 0xd4, 0x00, dev);
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sis_85c49x_pci_write(0, 0xd4, 0x00, dev);
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dev->pci_conf[0x67] = 0x00;
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dev->pci_conf[0xc6] = 0x00;
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ide_pri_disable();
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ide_pri_disable();
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ide_sec_disable();
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ide_sec_disable();
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@@ -617,7 +619,7 @@ sis_85c496_reset(void *priv)
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sis_85c497_isa_reset(dev);
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sis_85c497_isa_reset(dev);
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cpu_cpurst_on_sr = 1;
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cpu_cpurst_on_sr = 0;
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soft_reset_pci = 0;
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soft_reset_pci = 0;
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}
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}
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