80486DX2-66/86Box-fork
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Whoops, patching mishap.

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This commit is contained in:
waltje
2017-09-04 02:42:48 -04:00
parent 73ef17be9e
commit 0a5ac0792f
6 changed files with 9 additions and 1295 deletions
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301
src/fdc37c665.c
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@@ -1,301 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SMC FDC37C665 Super I/O Chip.
*
* Version: @(#)fdc37c665.c 1.0.2 2017/08/24
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016-2017 Miran Grca.
*/
#include "ibm.h"
#include "disc.h"
#include "fdc.h"
#include "fdd.h"
#include "io.h"
#include "lpt.h"
#include "serial.h"
#include "hdd/hdd_ide_at.h"
#include "fdc37c665.h"
static uint8_t fdc37c665_lock[2];
static int fdc37c665_curreg;
static uint8_t fdc37c665_regs[16];
static int com3_addr, com4_addr;
static void write_lock(uint8_t val)
{
if (val == 0x55 && fdc37c665_lock[1] == 0x55)
fdc_3f1_enable(0);
if (fdc37c665_lock[0] == 0x55 && fdc37c665_lock[1] == 0x55 && val != 0x55)
fdc_3f1_enable(1);
fdc37c665_lock[0] = fdc37c665_lock[1];
fdc37c665_lock[1] = val;
}
static void ide_handler()
{
#if 0
uint16_t or_value = 0;
if ((romset == ROM_440FX) || (romset == ROM_R418) || (romset == ROM_MB500N))
{
return;
}
ide_pri_disable();
if (fdc37c665_regs[0] & 1)
{
if (fdc37c665_regs[5] & 2)
{
or_value = 0;
}
else
{
or_value = 0x800;
}
ide_set_base(0, 0x170 | or_value);
ide_set_side(0, 0x376 | or_value);
ide_pri_enable_ex();
}
#endif
}
static void set_com34_addr()
{
switch (fdc37c665_regs[1] & 0x60)
{
case 0x00:
com3_addr = 0x338;
com4_addr = 0x238;
break;
case 0x20:
com3_addr = 0x3e8;
com4_addr = 0x2e8;
break;
case 0x40:
com3_addr = 0x3e8;
com4_addr = 0x2e0;
break;
case 0x60:
com3_addr = 0x220;
com4_addr = 0x228;
break;
}
}
void set_serial1_addr()
{
if (fdc37c665_regs[2] & 4)
{
switch (fdc37c665_regs[2] & 3)
{
case 0:
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
break;
case 1:
serial_setup(1, SERIAL2_ADDR, SERIAL2_IRQ);
break;
case 2:
serial_setup(1, com3_addr, 4);
break;
case 3:
serial_setup(1, com4_addr, 3);
break;
}
}
}
void set_serial2_addr()
{
if (fdc37c665_regs[2] & 0x40)
{
switch (fdc37c665_regs[2] & 0x30)
{
case 0:
serial_setup(2, SERIAL1_ADDR, SERIAL1_IRQ);
break;
case 1:
serial_setup(2, SERIAL2_ADDR, SERIAL2_IRQ);
break;
case 2:
serial_setup(2, com3_addr, 4);
break;
case 3:
serial_setup(2, com4_addr, 3);
break;
}
}
}
static void lpt1_handler()
{
lpt1_remove();
switch (fdc37c665_regs[1] & 3)
{
case 1:
lpt1_init(0x3bc);
break;
case 2:
lpt1_init(0x378);
break;
case 3:
lpt1_init(0x278);
break;
}
}
void fdc37c665_write(uint16_t port, uint8_t val, void *priv)
{
uint8_t valxor = 0;
if (fdc37c665_lock[0] == 0x55 && fdc37c665_lock[1] == 0x55)
{
if (port == 0x3f0)
{
if (val == 0xaa)
write_lock(val);
else
if (fdc37c665_curreg != 0)
{
fdc37c665_curreg = val & 0xf;
}
else
{
/* Hardcode the IDE to AT type. */
fdc37c665_curreg = (val & 0xf) | 2;
}
}
else
{
valxor = val ^ fdc37c665_regs[fdc37c665_curreg];
fdc37c665_regs[fdc37c665_curreg] = val;
switch(fdc37c665_curreg)
{
case 0:
if (valxor & 1)
{
ide_handler();
}
break;
case 1:
if (valxor & 3)
{
lpt1_handler();
}
if (valxor & 0x60)
{
serial_remove(1);
set_com34_addr();
set_serial1_addr();
set_serial2_addr();
}
break;
case 2:
if (valxor & 7)
{
serial_remove(1);
set_serial1_addr();
}
if (valxor & 0x70)
{
serial_remove(2);
set_serial2_addr();
}
break;
case 3:
if (valxor & 2)
{
fdc_update_enh_mode((fdc37c665_regs[3] & 2) ? 1 : 0);
}
break;
case 5:
if (valxor & 2)
{
ide_handler();
}
if (valxor & 0x18)
{
fdc_update_densel_force((fdc37c665_regs[5] & 0x18) >> 3);
}
if (valxor & 0x20)
{
fdd_swap = ((fdc37c665_regs[5] & 0x20) >> 5);
}
break;
}
}
}
else
{
if (port == 0x3f0)
write_lock(val);
}
}
uint8_t fdc37c665_read(uint16_t port, void *priv)
{
if (fdc37c665_lock[0] == 0x55 && fdc37c665_lock[1] == 0x55)
{
if (port == 0x3f1)
return fdc37c665_regs[fdc37c665_curreg];
}
return 0xff;
}
void fdc37c665_reset(void)
{
com3_addr = 0x338;
com4_addr = 0x238;
fdc_remove();
fdc_add_for_superio();
fdc_update_is_nsc(0);
serial_remove(1);
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
serial_remove(2);
serial_setup(2, SERIAL2_ADDR, SERIAL2_IRQ);
lpt2_remove();
lpt1_remove();
lpt1_init(0x378);
memset(fdc37c665_lock, 0, 2);
memset(fdc37c665_regs, 0, 16);
fdc37c665_regs[0x0] = 0x3a;
fdc37c665_regs[0x1] = 0x9f;
fdc37c665_regs[0x2] = 0xdc;
fdc37c665_regs[0x3] = 0x78;
fdc37c665_regs[0x6] = 0xff;
fdc37c665_regs[0xd] = 0x65;
fdc37c665_regs[0xe] = 0x01;
fdc_update_densel_polarity(1);
fdc_update_densel_force(0);
fdd_swap = 0;
}
void fdc37c665_init()
{
io_sethandler(0x03f0, 0x0002, fdc37c665_read, NULL, NULL, fdc37c665_write, NULL, NULL, NULL);
fdc37c665_reset();
pci_reset_handler.super_io_reset = fdc37c665_reset;
}

506
src/fdc37c932fr.c
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@@ -1,506 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SMC FDC37C932FR Super I/O Chip.
*
* Version: @(#)fdc37c932fr.c 1.0.1 2017/08/24
*
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2016,2017 Miran Grca.
*/
#include "ibm.h"
#include "disc.h"
#include "fdc.h"
#include "fdd.h"
#include "io.h"
#include "lpt.h"
#include "serial.h"
#include "hdd/hdd_ide_at.h"
#include "fdc37c932fr.h"
static int fdc37c932fr_locked;
static int fdc37c932fr_curreg = 0;
static int fdc37c932fr_gpio_curreg = 0;
static uint8_t fdc37c932fr_regs[48];
static uint8_t fdc37c932fr_ld_regs[10][256];
static uint8_t fdc37c932fr_gpio_regs[16] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
static uint8_t tries;
static uint16_t ld0_valid_ports[2] = {0x3F0, 0x370};
static uint16_t ld1_valid_ports[2] = {0x1F0, 0x170};
static uint16_t ld1_valid_ports2[2] = {0x3F6, 0x376};
static uint16_t ld2_valid_ports[2] = {0x170, 0x1F0};
static uint16_t ld2_valid_ports2[2] = {0x376, 0x3F6};
static uint16_t ld3_valid_ports[3] = {0x3BC, 0x378, 0x278};
static uint16_t ld4_valid_ports[9] = {0x3F8, 0x2F8, 0x338, 0x3E8, 0x2E8, 0x220, 0x238, 0x2E0, 0x228};
static uint16_t ld5_valid_ports[9] = {0x3F8, 0x2F8, 0x338, 0x3E8, 0x2E8, 0x220, 0x238, 0x2E0, 0x228};
static uint16_t ld5_valid_ports2[9] = {0x3F8, 0x2F8, 0x338, 0x3E8, 0x2E8, 0x220, 0x238, 0x2E0, 0x228};
static uint8_t is_in_array(uint16_t *port_array, uint8_t max, uint16_t port)
{
uint8_t i = 0;
for (i = 0; i < max; i++)
{
if (port_array[i] == port) return 1;
}
return 0;
}
static uint16_t make_port(uint8_t ld)
{
uint16_t r0 = fdc37c932fr_ld_regs[ld][0x60];
uint16_t r1 = fdc37c932fr_ld_regs[ld][0x61];
uint16_t p = (r0 << 8) + r1;
switch(ld)
{
case 0:
p &= 0xFF8;
if ((p < 0x100) || (p > 0xFF8)) p = 0x3F0;
if (!(is_in_array(ld0_valid_ports, 2, p))) p = 0x3F0;
break;
case 1:
p &= 0xFF8;
if ((p < 0x100) || (p > 0xFF8)) p = 0x1F0;
if (!(is_in_array(ld1_valid_ports, 2, p))) p = 0x1F0;
break;
case 2:
p &= 0xFF8;
if ((p < 0x100) || (p > 0xFF8)) p = 0x170;
if (!(is_in_array(ld2_valid_ports, 2, p))) p = 0x170;
break;
case 3:
p &= 0xFF8;
if ((p < 0x100) || (p > 0xFF8)) p = 0x378;
if (!(is_in_array(ld3_valid_ports, 3, p))) p = 0x378;
break;
case 4:
p &= 0xFF8;
if ((p < 0x100) || (p > 0xFF8)) p = 0x3F8;
if (!(is_in_array(ld4_valid_ports, 9, p))) p = 0x3F8;
break;
case 5:
p &= 0xFF8;
if ((p < 0x100) || (p > 0xFF8)) p = 0x2F8;
if (!(is_in_array(ld5_valid_ports, 9, p))) p = 0x2F8;
break;
}
fdc37c932fr_ld_regs[ld][0x60] = (p >> 8);
fdc37c932fr_ld_regs[ld][0x61] = (p & 0xFF);
return p;
}
uint16_t make_port2(uint8_t ld)
{
uint16_t r0 = fdc37c932fr_ld_regs[ld][0x62];
uint16_t r1 = fdc37c932fr_ld_regs[ld][0x63];
uint16_t p = (r0 << 8) + r1;
switch(ld)
{
case 1:
p &= 0xFFF;
if ((p < 0x100) || (p > 0xFF8)) p = 0x3F6;
if (!(is_in_array(ld1_valid_ports2, 2, p))) p = 0x3F6;
break;
case 2:
p &= 0xFFF;
if ((p < 0x100) || (p > 0xFF8)) p = 0x376;
if (!(is_in_array(ld2_valid_ports2, 2, p))) p = 0x376;
break;
case 5:
p &= 0xFF8;
if ((p < 0x100) || (p > 0xFF8)) p = 0x3E8;
if (!(is_in_array(ld5_valid_ports2, 9, p))) p = 0x3E8;
break;
}
fdc37c932fr_ld_regs[ld][0x62] = (p >> 8);
fdc37c932fr_ld_regs[ld][0x63] = (p & 0xFF);
return p;
}
void fdc37c932fr_gpio_write(uint16_t port, uint8_t val, void *priv)
{
if (port & 1)
{
if (fdc37c932fr_gpio_curreg && (fdc37c932fr_gpio_curreg <= 0xF))
fdc37c932fr_gpio_regs[fdc37c932fr_gpio_curreg] = val;
}
else
{
fdc37c932fr_gpio_curreg = val;
}
}
void fdc37c932fr_write(uint16_t port, uint8_t val, void *priv)
{
uint8_t index = (port & 1) ? 0 : 1;
uint8_t valxor = 0;
uint16_t ld_port = 0;
if (index)
{
if ((val == 0x55) && !fdc37c932fr_locked)
{
if (tries)
{
fdc37c932fr_locked = 1;
fdc_3f1_enable(0);
tries = 0;
}
else
{
tries++;
}
}
else
{
if (fdc37c932fr_locked)
{
if (val == 0xaa)
{
fdc37c932fr_locked = 0;
fdc_3f1_enable(1);
return;
}
fdc37c932fr_curreg = val;
}
else
{
if (tries)
tries = 0;
}
}
}
else
{
if (fdc37c932fr_locked)
{
if (fdc37c932fr_curreg < 48)
{
valxor = val ^ fdc37c932fr_regs[fdc37c932fr_curreg];
fdc37c932fr_regs[fdc37c932fr_curreg] = val;
}
else
{
valxor = val ^ fdc37c932fr_ld_regs[fdc37c932fr_regs[7]][fdc37c932fr_curreg];
if (((fdc37c932fr_curreg & 0xF0) == 0x70) && (fdc37c932fr_regs[7] < 4)) return;
/* Block writes to IDE configuration. */
if (fdc37c932fr_regs[7] > 5) return;
fdc37c932fr_ld_regs[fdc37c932fr_regs[7]][fdc37c932fr_curreg] = val;
goto process_value;
}
}
}
return;
process_value:
switch(fdc37c932fr_regs[7])
{
case 0:
/* FDD */
switch(fdc37c932fr_curreg)
{
case 0x30:
/* Activate */
if (valxor)
{
if (!val)
fdc_remove();
else
{
fdc_add();
}
}
break;
case 0x60:
case 0x61:
if (valxor && fdc37c932fr_ld_regs[0][0x30])
{
fdc_remove();
ld_port = make_port(0);
fdc37c932fr_ld_regs[0][0x60] = make_port(0) >> 8;
fdc37c932fr_ld_regs[0][0x61] = make_port(0) & 0xFF;
fdc_add();
}
break;
case 0xF0:
if (valxor & 0x01) fdc_update_enh_mode(val & 0x01);
if (valxor & 0x10) fdd_swap = ((val & 0x10) >> 4);
break;
case 0xF1:
if (valxor & 0xC) fdc_update_densel_force((val & 0xC) >> 2);
break;
case 0xF2:
if (valxor & 0xC0) fdc_update_rwc(3, (valxor & 0xC0) >> 6);
if (valxor & 0x30) fdc_update_rwc(2, (valxor & 0x30) >> 4);
if (valxor & 0x0C) fdc_update_rwc(1, (valxor & 0x0C) >> 2);
if (valxor & 0x03) fdc_update_rwc(0, (valxor & 0x03));
break;
case 0xF4:
if (valxor & 0x18) fdc_update_drvrate(0, (val & 0x18) >> 3);
break;
case 0xF5:
if (valxor & 0x18) fdc_update_drvrate(1, (val & 0x18) >> 3);
break;
case 0xF6:
if (valxor & 0x18) fdc_update_drvrate(2, (val & 0x18) >> 3);
break;
case 0xF7:
if (valxor & 0x18) fdc_update_drvrate(3, (val & 0x18) >> 3);
break;
}
break;
case 3:
/* Parallel port */
switch(fdc37c932fr_curreg)
{
case 0x30:
/* Activate */
if (valxor)
{
if (!val)
lpt1_remove();
else
{
ld_port = make_port(3);
lpt1_init(ld_port);
}
}
break;
case 0x60:
case 0x61:
if (valxor && fdc37c932fr_ld_regs[3][0x30])
{
lpt1_remove();
ld_port = make_port(3);
lpt1_init(ld_port);
}
break;
}
break;
case 4:
/* Serial port 1 */
switch(fdc37c932fr_curreg)
{
case 0x30:
/* Activate */
if (valxor)
{
if (!val)
serial_remove(1);
else
{
ld_port = make_port(4);
serial_setup(1, ld_port, fdc37c932fr_ld_regs[4][0x70]);
}
}
break;
case 0x60:
case 0x61:
case 0x70:
if (valxor && fdc37c932fr_ld_regs[4][0x30])
{
ld_port = make_port(4);
serial_setup(1, ld_port, fdc37c932fr_ld_regs[4][0x70]);
}
break;
}
break;
case 5:
/* Serial port 2 */
switch(fdc37c932fr_curreg)
{
case 0x30:
/* Activate */
if (valxor)
{
if (!val)
serial_remove(2);
else
{
ld_port = make_port(5);
serial_setup(2, ld_port, fdc37c932fr_ld_regs[5][0x70]);
}
}
break;
case 0x60:
case 0x61:
case 0x70:
if (valxor && fdc37c932fr_ld_regs[5][0x30])
{
ld_port = make_port(5);
serial_setup(2, ld_port, fdc37c932fr_ld_regs[5][0x70]);
}
break;
}
break;
}
}
uint8_t fdc37c932fr_gpio_read(uint16_t port, void *priv)
{
if (port & 1)
{
if (fdc37c932fr_gpio_curreg && (fdc37c932fr_gpio_curreg <= 0xF))
return fdc37c932fr_gpio_regs[fdc37c932fr_gpio_curreg];
else
return 0xff;
}
else
{
return fdc37c932fr_gpio_curreg;
}
}
uint8_t fdc37c932fr_read(uint16_t port, void *priv)
{
uint8_t index = (port & 1) ? 0 : 1;
if (!fdc37c932fr_locked)
{
return 0xff;
}
if (index)
return fdc37c932fr_curreg;
else
{
if (fdc37c932fr_curreg < 0x30)
{
return fdc37c932fr_regs[fdc37c932fr_curreg];
}
else
{
if ((fdc37c932fr_regs[7] == 0) && (fdc37c932fr_curreg == 0xF2)) return (fdc_get_rwc(0) | (fdc_get_rwc(1) << 2));
return fdc37c932fr_ld_regs[fdc37c932fr_regs[7]][fdc37c932fr_curreg];
}
}
}
void fdc37c932fr_reset(void)
{
int i = 0;
fdc37c932fr_regs[3] = 3;
fdc37c932fr_regs[0x20] = 3;
fdc37c932fr_regs[0x21] = 1;
fdc37c932fr_regs[0x24] = 4;
fdc37c932fr_regs[0x26] = 0xF0;
fdc37c932fr_regs[0x27] = 3;
for (i = 0; i < 10; i++)
{
memset(fdc37c932fr_ld_regs[i], 0, 256);
}
/* Logical device 0: FDD */
fdc37c932fr_ld_regs[0][0x30] = 1;
fdc37c932fr_ld_regs[0][0x60] = 3;
fdc37c932fr_ld_regs[0][0x61] = 0xF0;
fdc37c932fr_ld_regs[0][0x70] = 6;
fdc37c932fr_ld_regs[0][0x74] = 2;
fdc37c932fr_ld_regs[0][0xF0] = 0xE;
fdc37c932fr_ld_regs[0][0xF2] = 0xFF;
/* Logical device 1: IDE1 */
fdc37c932fr_ld_regs[1][0x30] = 0;
fdc37c932fr_ld_regs[1][0x60] = 1;
fdc37c932fr_ld_regs[1][0x61] = 0xF0;
fdc37c932fr_ld_regs[1][0x62] = 3;
fdc37c932fr_ld_regs[1][0x63] = 0xF6;
fdc37c932fr_ld_regs[1][0x70] = 0xE;
fdc37c932fr_ld_regs[1][0xF0] = 0xC;
/* Logical device 2: IDE2 */
fdc37c932fr_ld_regs[2][0x30] = 0;
fdc37c932fr_ld_regs[2][0x60] = 1;
fdc37c932fr_ld_regs[2][0x61] = 0x70;
fdc37c932fr_ld_regs[2][0x62] = 3;
fdc37c932fr_ld_regs[2][0x63] = 0x76;
fdc37c932fr_ld_regs[2][0x70] = 0xF;
/* Logical device 3: Parallel Port */
fdc37c932fr_ld_regs[3][0x30] = 1;
fdc37c932fr_ld_regs[3][0x60] = 3;
fdc37c932fr_ld_regs[3][0x61] = 0x78;
fdc37c932fr_ld_regs[3][0x70] = 7;
fdc37c932fr_ld_regs[3][0x74] = 4;
fdc37c932fr_ld_regs[3][0xF0] = 0x3C;
/* Logical device 4: Serial Port 1 */
fdc37c932fr_ld_regs[4][0x30] = 1;
fdc37c932fr_ld_regs[4][0x60] = 3;
fdc37c932fr_ld_regs[4][0x61] = 0xf8;
fdc37c932fr_ld_regs[4][0x70] = 4;
fdc37c932fr_ld_regs[4][0xF0] = 3;
serial_setup(1, 0x3f8, fdc37c932fr_ld_regs[4][0x70]);
/* Logical device 5: Serial Port 2 */
fdc37c932fr_ld_regs[5][0x30] = 1;
fdc37c932fr_ld_regs[5][0x60] = 2;
fdc37c932fr_ld_regs[5][0x61] = 0xf8;
fdc37c932fr_ld_regs[5][0x70] = 3;
fdc37c932fr_ld_regs[5][0x74] = 4;
fdc37c932fr_ld_regs[5][0xF1] = 2;
fdc37c932fr_ld_regs[5][0xF2] = 3;
serial_setup(2, 0x2f8, fdc37c932fr_ld_regs[5][0x70]);
/* Logical device 6: RTC */
fdc37c932fr_ld_regs[6][0x63] = 0x70;
fdc37c932fr_ld_regs[6][0xF4] = 3;
/* Logical device 7: Keyboard */
fdc37c932fr_ld_regs[7][0x30] = 1;
fdc37c932fr_ld_regs[7][0x61] = 0x60;
fdc37c932fr_ld_regs[7][0x70] = 1;
/* Logical device 8: AUX I/O */
/* Logical device 9: ACCESS.bus */
fdc_update_densel_force(0);
fdd_swap = 0;
fdc_update_rwc(0, 0);
fdc_update_rwc(1, 0);
fdc_update_rwc(2, 0);
fdc_update_rwc(3, 0);
fdc_update_drvrate(0, 0);
fdc_update_drvrate(1, 0);
fdc_update_drvrate(2, 0);
fdc_update_drvrate(3, 0);
fdc_update_max_track(79);
memset(fdc37c932fr_gpio_regs, 0, sizeof(fdc37c932fr_gpio_regs));
fdc37c932fr_gpio_regs[2] = 0xfd;
fdc37c932fr_locked = 0;
}
void fdc37c932fr_init()
{
lpt2_remove();
fdc37c932fr_reset();
io_sethandler(0xe0, 0x0006, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
io_sethandler(0xe2, 0x0006, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
io_sethandler(0xe4, 0x0006, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
io_sethandler(0xea, 0x0002, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
io_sethandler(0x3f0, 0x0002, fdc37c932fr_read, NULL, NULL, fdc37c932fr_write, NULL, NULL, NULL);
pci_reset_handler.super_io_reset = fdc37c932fr_reset;
}

479
src/pc87306.c
View File

@@ -1,479 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the National Semiconductors PC87306 Super I/O
* chip.
*
* Version: @(#)pc87306.c 1.0.1 2017/08/24
*
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2016,2017 Miran Grca.
*/
#include "ibm.h"
#include "disc.h"
#include "fdc.h"
#include "fdd.h"
#include "io.h"
#include "lpt.h"
#include "serial.h"
#include "hdd/hdd_ide_at.h"
#include "pc87306.h"
static int pc87306_curreg;
static uint8_t pc87306_regs[29];
static uint8_t pc87306_gpio[2] = {0xFF, 0xFB};
static uint8_t tries;
static uint16_t lpt_port;
void pc87306_gpio_remove();
void pc87306_gpio_init();
void pc87306_gpio_write(uint16_t port, uint8_t val, void *priv)
{
pc87306_gpio[port & 1] = val;
}
uint8_t uart_int1()
{
/* 0: IRQ3, 1: IRQ4 */
return ((pc87306_regs[0x1C] >> 2) & 1) ? 4 : 3;
}
uint8_t uart_int2()
{
/* 0: IRQ3, 1: IRQ4 */
return ((pc87306_regs[0x1C] >> 6) & 1) ? 4 : 3;
}
uint8_t uart1_int()
{
uint8_t temp;
temp = ((pc87306_regs[1] >> 2) & 1) ? 3 : 4; /* 0 = COM1 (IRQ 4), 1 = COM2 (IRQ 3), 2 = COM3 (IRQ 4), 3 = COM4 (IRQ 3) */
return (pc87306_regs[0x1C] & 1) ? uart_int1() : temp;
}
uint8_t uart2_int()
{
uint8_t temp;
temp = ((pc87306_regs[1] >> 4) & 1) ? 3 : 4; /* 0 = COM1 (IRQ 4), 1 = COM2 (IRQ 3), 2 = COM3 (IRQ 4), 3 = COM4 (IRQ 3) */
return (pc87306_regs[0x1C] & 1) ? uart_int2() : temp;
}
void lpt1_handler()
{
int temp;
temp = pc87306_regs[0x01] & 3;
switch (temp)
{
case 0:
lpt_port = 0x378;
break;
case 1:
if (pc87306_regs[0x1B] & 0x40)
{
lpt_port = ((uint16_t) pc87306_regs[0x19]) << 2;
}
else
{
lpt_port = 0x3bc;
}
break;
case 2:
lpt_port = 0x278;
break;
}
lpt1_init(lpt_port);
}
void serial1_handler()
{
int temp;
temp = (pc87306_regs[1] >> 2) & 3;
switch (temp)
{
case 0: serial_setup(1, SERIAL1_ADDR, uart1_int()); break;
case 1: serial_setup(1, SERIAL2_ADDR, uart1_int()); break;
case 2:
switch ((pc87306_regs[1] >> 6) & 3)
{
case 0: serial_setup(1, 0x3e8, uart1_int()); break;
case 1: serial_setup(1, 0x338, uart1_int()); break;
case 2: serial_setup(1, 0x2e8, uart1_int()); break;
case 3: serial_setup(1, 0x220, uart1_int()); break;
}
break;
case 3:
switch ((pc87306_regs[1] >> 6) & 3)
{
case 0: serial_setup(1, 0x2e8, uart1_int()); break;
case 1: serial_setup(1, 0x238, uart1_int()); break;
case 2: serial_setup(1, 0x2e0, uart1_int()); break;
case 3: serial_setup(1, 0x228, uart1_int()); break;
}
break;
}
}
void serial2_handler()
{
int temp;
temp = (pc87306_regs[1] >> 4) & 3;
switch (temp)
{
case 0: serial_setup(2, SERIAL1_ADDR, uart2_int()); break;
case 1: serial_setup(2, SERIAL2_ADDR, uart2_int()); break;
case 2:
switch ((pc87306_regs[1] >> 6) & 3)
{
case 0: serial_setup(2, 0x3e8, uart2_int()); break;
case 1: serial_setup(2, 0x338, uart2_int()); break;
case 2: serial_setup(2, 0x2e8, uart2_int()); break;
case 3: serial_setup(2, 0x220, uart2_int()); break;
}
break;
case 3:
switch ((pc87306_regs[1] >> 6) & 3)
{
case 0: serial_setup(2, 0x2e8, uart2_int()); break;
case 1: serial_setup(2, 0x238, uart2_int()); break;
case 2: serial_setup(2, 0x2e0, uart2_int()); break;
case 3: serial_setup(2, 0x228, uart2_int()); break;
}
break;
}
}
void pc87306_write(uint16_t port, uint8_t val, void *priv)
{
uint8_t index;
uint8_t valxor;
#if 0
uint16_t or_value;
#endif
index = (port & 1) ? 0 : 1;
if (index)
{
pc87306_curreg = val & 0x1f;
tries = 0;
return;
}
else
{
if (tries)
{
if ((pc87306_curreg == 0) && (val == 8))
{
val = 0x4b;
}
if (pc87306_curreg <= 28) valxor = val ^ pc87306_regs[pc87306_curreg];
tries = 0;
if ((pc87306_curreg == 0x19) && !(pc87306_regs[0x1B] & 0x40))
{
return;
}
if ((pc87306_curreg <= 28) && (pc87306_curreg != 8)/* && (pc87306_curreg != 0x18)*/)
{
if (pc87306_curreg == 0)
{
val &= 0x5f;
}
if (((pc87306_curreg == 0x0F) || (pc87306_curreg == 0x12)) && valxor)
{
pc87306_gpio_remove();
}
pc87306_regs[pc87306_curreg] = val;
goto process_value;
}
}
else
{
tries++;
return;
}
}
return;
process_value:
switch(pc87306_curreg)
{
case 0:
if (valxor & 1)
{
lpt1_remove();
if (val & 1)
{
lpt1_handler();
}
}
if (valxor & 2)
{
serial_remove(1);
if (val & 2)
{
serial1_handler();
}
}
if (valxor & 4)
{
serial_remove(2);
if (val & 4)
{
serial2_handler();
}
}
if (valxor & 0x28)
{
fdc_remove();
if (val & 8)
{
fdc_set_base((val & 0x20) ? 0x370 : 0x3f0, 0);
}
}
if (valxor & 0xc0)
{
#if 0
ide_pri_disable();
if (val & 0x80)
{
or_value = 0;
}
else
{
or_value = 0x80;
}
ide_set_base(0, 0x170 | or_value);
ide_set_side(0, 0x376 | or_value);
if (val & 0x40)
{
ide_pri_enable_ex();
}
#endif
}
break;
case 1:
if (valxor & 3)
{
lpt1_remove();
if (pc87306_regs[0] & 1)
{
lpt1_handler();
}
}
if (valxor & 0xcc)
{
if (pc87306_regs[0] & 2)
{
serial1_handler();
}
else
{
serial_remove(1);
}
}
if (valxor & 0xf0)
{
if (pc87306_regs[0] & 4)
{
serial2_handler();
}
else
{
serial_remove(2);
}
}
break;
case 2:
if (valxor & 1)
{
if (val & 1)
{
lpt1_remove();
serial_remove(1);
serial_remove(2);
fdc_remove();
}
else
{
if (pc87306_regs[0] & 1)
{
lpt1_handler();
}
if (pc87306_regs[0] & 2)
{
serial1_handler();
}
if (pc87306_regs[0] & 4)
{
serial2_handler();
}
if (pc87306_regs[0] & 8)
{
fdc_set_base((pc87306_regs[0] & 0x20) ? 0x370 : 0x3f0, 0);
}
}
}
break;
case 9:
if (valxor & 0x44)
{
fdc_update_enh_mode((val & 4) ? 1 : 0);
fdc_update_densel_polarity((val & 0x40) ? 1 : 0);
}
break;
case 0xF:
if (valxor)
{
pc87306_gpio_init();
}
break;
case 0x12:
if (valxor & 0x30)
{
pc87306_gpio_init();
}
break;
case 0x19:
if (valxor)
{
lpt1_remove();
if (pc87306_regs[0] & 1)
{
lpt1_handler();
}
}
break;
case 0x1B:
if (valxor & 0x40)
{
lpt1_remove();
if (!(val & 0x40))
{
pc87306_regs[0x19] = 0xEF;
}
if (pc87306_regs[0] & 1)
{
lpt1_handler();
}
}
break;
case 0x1C:
if (valxor)
{
if (pc87306_regs[0] & 2)
{
serial1_handler();
}
if (pc87306_regs[0] & 4)
{
serial2_handler();
}
}
break;
}
}
uint8_t pc87306_gpio_read(uint16_t port, void *priv)
{
return pc87306_gpio[port & 1];
}
uint8_t pc87306_read(uint16_t port, void *priv)
{
uint8_t index;
index = (port & 1) ? 0 : 1;
tries = 0;
if (index)
{
return pc87306_curreg & 0x1f;
}
else
{
if (pc87306_curreg >= 28)
{
return 0xff;
}
else if (pc87306_curreg == 8)
{
return 0x70;
}
else
{
return pc87306_regs[pc87306_curreg];
}
}
}
void pc87306_gpio_remove()
{
io_removehandler(pc87306_regs[0xF] << 2, 0x0002, pc87306_gpio_read, NULL, NULL, pc87306_gpio_write, NULL, NULL, NULL);
}
void pc87306_gpio_init()
{
if ((pc87306_regs[0x12]) & 0x10)
{
io_sethandler(pc87306_regs[0xF] << 2, 0x0001, pc87306_gpio_read, NULL, NULL, pc87306_gpio_write, NULL, NULL, NULL);
}
if ((pc87306_regs[0x12]) & 0x20)
{
io_sethandler((pc87306_regs[0xF] << 2) + 1, 0x0001, pc87306_gpio_read, NULL, NULL, pc87306_gpio_write, NULL, NULL, NULL);
}
}
void pc87306_reset(void)
{
memset(pc87306_regs, 0, 29);
/* pc87306_regs[0] = 0x4B; */
pc87306_regs[0] = 0x0B;
pc87306_regs[1] = 0x01;
pc87306_regs[3] = 0x01;
pc87306_regs[5] = 0x0D;
pc87306_regs[8] = 0x70;
pc87306_regs[9] = 0xC0;
pc87306_regs[0xB] = 0x80;
pc87306_regs[0xF] = 0x1E;
pc87306_regs[0x12] = 0x30;
pc87306_regs[0x19] = 0xEF;
/*
0 = 360 rpm @ 500 kbps for 3.5"
1 = Default, 300 rpm @ 500,300,250,1000 kbps for 3.5"
*/
fdc_update_is_nsc(1);
fdc_update_enh_mode(0);
fdc_update_densel_polarity(1);
fdc_update_max_track(85);
fdc_remove();
fdc_set_base(0x3f0, 0);
fdd_swap = 0;
serial_remove(1);
serial_remove(2);
serial1_handler();
serial2_handler();
pc87306_gpio_init();
}
void pc87306_init()
{
lpt2_remove();
pc87306_reset();
io_sethandler(0x02e, 0x0002, pc87306_read, NULL, NULL, pc87306_write, NULL, NULL, NULL);
pci_reset_handler.super_io_reset = pc87306_reset;
}

4
src/sio_fdc37c665.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the SMC FDC37C665 Super I/O Chip.
*
* Version: @(#)sio_fdc37c665.c 1.0.3 2017/09/03
* Version: @(#)sio_fdc37c665.c 1.0.4 2017/09/03
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -280,7 +280,7 @@ void fdc37c665_reset(void)
memset(fdc37c665_lock, 0, 2);
memset(fdc37c665_regs, 0, 16);
fdc37c665_regs[0x0] = 0x3b;
fdc37c665_regs[0x0] = 0x3a;
fdc37c665_regs[0x1] = 0x9f;
fdc37c665_regs[0x2] = 0xdc;
fdc37c665_regs[0x3] = 0x78;

6
src/sio_fdc37c932fr.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the SMC FDC37C932FR Super I/O Chip.
*
* Version: @(#)sio_fdc37c932fr.c 1.0.2 2017/09/03
* Version: @(#)sio_fdc37c932fr.c 1.0.3 2017/09/03
*
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2016,2017 Miran Grca.
@@ -420,7 +420,7 @@ void fdc37c932fr_reset(void)
fdc37c932fr_ld_regs[0][0xF2] = 0xFF;
/* Logical device 1: IDE1 */
fdc37c932fr_ld_regs[1][0x30] = 1;
fdc37c932fr_ld_regs[1][0x30] = 0;
fdc37c932fr_ld_regs[1][0x60] = 1;
fdc37c932fr_ld_regs[1][0x61] = 0xF0;
fdc37c932fr_ld_regs[1][0x62] = 3;
@@ -429,7 +429,7 @@ void fdc37c932fr_reset(void)
fdc37c932fr_ld_regs[1][0xF0] = 0xC;
/* Logical device 2: IDE2 */
fdc37c932fr_ld_regs[2][0x30] = 1;
fdc37c932fr_ld_regs[2][0x30] = 0;
fdc37c932fr_ld_regs[2][0x60] = 1;
fdc37c932fr_ld_regs[2][0x61] = 0x70;
fdc37c932fr_ld_regs[2][0x62] = 3;

8
src/sio_pc87306.c
View File

@@ -6,10 +6,9 @@
*
* This file is part of the 86Box distribution.
*
* Emulation of the National Semiconductors PC87306 Super I/O
* chip.
* Emulation of the NatSemi PC87306 Super I/O chip.
*
* Version: @(#)sio_pc87306.c 1.0.2 2017/09/03
* Version: @(#)sio_pc87306.c 1.0.3 2017/09/03
*
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2016,2017 Miran Grca.
@@ -439,7 +438,8 @@ void pc87306_reset(void)
{
memset(pc87306_regs, 0, 29);
pc87306_regs[0] = 0x4B;
/* pc87306_regs[0] = 0x4B; */
pc87306_regs[0] = 0x0B;
pc87306_regs[1] = 0x01;
pc87306_regs[3] = 0x01;
pc87306_regs[5] = 0x0D;