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Fixes on the Aladdin IV

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This commit is contained in:
Panagiotis
2021-04-13 15:21:10 +03:00
committed by GitHub
parent 76f3f08d78
commit 0b7bec3831
3 changed files with 42 additions and 27 deletions
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27
src/chipset/ali1531.c
View File

@@ -41,23 +41,20 @@ typedef struct ali1531_t
smram_t *smram; smram_t *smram;
} ali1531_t; } ali1531_t;
void ali1531_shadow_recalc(ali1531_t *dev) void ali1531_shadow_recalc(int cur_reg, ali1531_t *dev)
{ {
for (uint32_t i = 0; i < 8; i++) for (uint32_t i = 0; i < 8; i++)
{ mem_set_mem_state_both(0xc0000 + ((cur_reg & 1) << 17) + (i << 14), 0x4000, (((dev->pci_conf[0x4c + (cur_reg & 1)] >> i) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (((dev->pci_conf[0x4e + (cur_reg & 1)] >> i) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, (((dev->pci_conf[0x4c] >> i) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (((dev->pci_conf[0x4e] >> i) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xe0000 + (i << 14), 0x4000, (((dev->pci_conf[0x4d] >> i) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (((dev->pci_conf[0x4f] >> i) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
}
shadowbios = !!(dev->pci_conf[0x4d] & 0xf0); flushmmucache_nopc();
shadowbios_write = !!(dev->pci_conf[0x4f] & 0xf0);
flushmmucache();
} }
void ali1531_smm_recalc(uint8_t smm_state, ali1531_t *dev) void ali1531_smm_recalc(uint8_t smm_state, ali1531_t *dev)
{ {
if (!!(dev->pci_conf[0x48] & 1))
smram_disable_all();
if (dev->pci_conf[0x48] & 1)
{ {
switch (smm_state) switch (smm_state)
{ {
@@ -86,12 +83,9 @@ void ali1531_smm_recalc(uint8_t smm_state, ali1531_t *dev)
smram_map(1, 0x30000, 0x10000, 1); smram_map(1, 0x30000, 0x10000, 1);
break; break;
} }
} }
else
smram_disable_all();
flushmmucache(); flushmmucache_nopc();
} }
static void static void
@@ -160,7 +154,7 @@ ali1531_write(int func, int addr, uint8_t val, void *priv)
case 0x4e: case 0x4e:
case 0x4f: case 0x4f:
dev->pci_conf[addr] = val; dev->pci_conf[addr] = val;
ali1531_shadow_recalc(dev); ali1531_shadow_recalc(addr, dev);
break; break;
case 0x57: /* H2PO */ case 0x57: /* H2PO */
@@ -202,7 +196,7 @@ ali1531_write(int func, int addr, uint8_t val, void *priv)
case 0x6e: case 0x6e:
case 0x6f: case 0x6f:
dev->pci_conf[addr] = val; dev->pci_conf[addr] = val;
spd_write_drbs(dev->pci_conf, 0x60, 0x6f, 2); spd_write_drbs(dev->pci_conf, 0x60, 0x6f, 1);
break; break;
case 0x72: case 0x72:
@@ -274,7 +268,6 @@ ali1531_reset(void *priv)
ali1531_write(0, 0x42, 0x00, dev); ali1531_write(0, 0x42, 0x00, dev);
ali1531_write(0, 0x43, 0x00, dev); ali1531_write(0, 0x43, 0x00, dev);
ali1531_write(0, 0x47, 0x00, dev); ali1531_write(0, 0x47, 0x00, dev);
ali1531_shadow_recalc(dev);
ali1531_write(0, 0x60, 0x08, dev); ali1531_write(0, 0x60, 0x08, dev);
ali1531_write(0, 0x61, 0x40, dev); ali1531_write(0, 0x61, 0x40, dev);
} }

36
src/chipset/ali1543.c
View File

@@ -96,6 +96,8 @@ typedef struct ali1543_t
*/ */
int ali1533_irq_routing[15] = {9, 3, 0x0a, 4, 5, 7, 6, 1, 0x0b, 0, 0x0c, 0, 0x0e, 0, 0x0f};
void ali1533_ddma_handler(ali1543_t *dev) void ali1533_ddma_handler(ali1543_t *dev)
{ {
for (uint8_t i = 0; i < 8; i++) for (uint8_t i = 0; i < 8; i++)
@@ -131,8 +133,23 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
dev->pci_conf[addr] = val & 0x7f; dev->pci_conf[addr] = val & 0x7f;
break; break;
case 0x42: case 0x42: /* ISA Bus Speed */
dev->pci_conf[addr] = val & 0xcf; dev->pci_conf[addr] = val & 0xcf;
switch(val & 7)
{
case 0:
cpu_set_isa_speed(7.16);
break;
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
cpu_set_isa_pci_div(val & 7);
break;
}
break; break;
case 0x43: case 0x43:
@@ -146,7 +163,7 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
case 0x44: /* Set IRQ Line for Primary IDE if it's on native mode */ case 0x44: /* Set IRQ Line for Primary IDE if it's on native mode */
dev->pci_conf[addr] = 0xdf; dev->pci_conf[addr] = 0xdf;
if (dev->ide_conf[0x09] & 1) if (dev->ide_conf[0x09] & 1)
sff_set_irq_line(dev->ide_controller[0], val & 0x0f); sff_set_irq_line(dev->ide_controller[0], ((val & 0x0f) == 0) ? ali1533_irq_routing[(val & 0x0f) - 1] : PCI_IRQ_DISABLED);
break; break;
case 0x45: /* DDMA Enable */ case 0x45: /* DDMA Enable */
@@ -157,8 +174,8 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
case 0x48: /* PCI IRQ Routing */ case 0x48: /* PCI IRQ Routing */
case 0x49: case 0x49:
dev->pci_conf[addr] = val; dev->pci_conf[addr] = val;
pci_set_irq_routing(((addr & 1) * 2) + 2, ((val & 0xf0) == 0) ? (val & 0xf0) : PCI_IRQ_DISABLED); pci_set_irq_routing(((addr & 1) * 2) + 2, (((val >> 4) & 0x0f) == 0) ? ali1533_irq_routing[((val >> 4) & 0x0f) - 1] : PCI_IRQ_DISABLED);
pci_set_irq_routing(((addr & 1) * 2) + 1, ((val & 0x0f) == 0) ? (val & 0x0f) : PCI_IRQ_DISABLED); pci_set_irq_routing(((addr & 1) * 2) + 1, ((val & 0x0f) == 0) ? ali1533_irq_routing[(val & 0x0f) - 1] : PCI_IRQ_DISABLED);
break; break;
case 0x53: /* USB Enable */ case 0x53: /* USB Enable */
@@ -222,13 +239,12 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
case 0x74: /* USB IRQ Routing */ case 0x74: /* USB IRQ Routing */
dev->pci_conf[addr] = val & 0xdf; dev->pci_conf[addr] = val & 0xdf;
pci_set_irq_routing(dev->usb_slot, ((val & 0x0f) == 0) ? (val & 0x0f) : PCI_IRQ_DISABLED);
break; break;
case 0x75: /* Set IRQ Line for Secondary IDE if it's on native mode */ case 0x75: /* Set IRQ Line for Secondary IDE if it's on native mode */
dev->pci_conf[addr] = val & 0x1f; dev->pci_conf[addr] = val & 0x1f;
if (dev->ide_conf[0x09] & 8) if (dev->ide_conf[0x09] & 8)
sff_set_irq_line(dev->ide_controller[1], val & 0x0f); sff_set_irq_line(dev->ide_controller[1], ((val & 0x0f) == 0) ? ali1533_irq_routing[(val & 0x0f) - 1] : PCI_IRQ_DISABLED);
break; break;
case 0x76: /* PMU IRQ Routing */ case 0x76: /* PMU IRQ Routing */
@@ -319,28 +335,28 @@ void ali5229_ide_handler(ali1543_t *dev)
/* Primary Channel Setup */ /* Primary Channel Setup */
if (dev->ide_conf[0x09] & 0x10) if (dev->ide_conf[0x09] & 0x10)
{ {
ide_pri_enable();
if (!(dev->ide_conf[0x09] & 1)) if (!(dev->ide_conf[0x09] & 1))
sff_set_irq_line(dev->ide_controller[0], dev->ide_conf[0x3c] & 0xf); sff_set_irq_line(dev->ide_controller[0], (dev->ide_conf[0x3c] != 0) ? ali1533_irq_routing[(dev->ide_conf[0x3c] & 0x0f) - 1] : PCI_IRQ_DISABLED);
ide_set_base(0, current_pri_base); ide_set_base(0, current_pri_base);
ide_set_side(0, current_pri_side); ide_set_side(0, current_pri_side);
sff_bus_master_handler(dev->ide_controller[0], dev->ide_conf[0x09] & 0x80, (dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)); sff_bus_master_handler(dev->ide_controller[0], dev->ide_conf[0x09] & 0x80, (dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8));
ide_pri_enable();
ali1543_log("M5229 PRI: BASE %04x SIDE %04x\n", current_pri_base, current_pri_side); ali1543_log("M5229 PRI: BASE %04x SIDE %04x\n", current_pri_base, current_pri_side);
} }
/* Secondary Channel Setup */ /* Secondary Channel Setup */
if (dev->ide_conf[0x09] & 8) if (dev->ide_conf[0x09] & 8)
{ {
ide_sec_enable();
if (!(dev->ide_conf[0x09] & 4)) if (!(dev->ide_conf[0x09] & 4))
sff_set_irq_line(dev->ide_controller[1], dev->ide_conf[0x3c] & 0xf); sff_set_irq_line(dev->ide_controller[1], (dev->ide_conf[0x3c] != 0) ? ali1533_irq_routing[(dev->ide_conf[0x3c] & 0x0f) - 1] : PCI_IRQ_DISABLED);
ide_set_base(1, current_sec_base); ide_set_base(1, current_sec_base);
ide_set_side(1, current_sec_side); ide_set_side(1, current_sec_side);
sff_bus_master_handler(dev->ide_controller[1], dev->ide_conf[0x09] & 0x80, ((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)) + 8); sff_bus_master_handler(dev->ide_controller[1], dev->ide_conf[0x09] & 0x80, ((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)) + 8);
ide_sec_enable();
ali1543_log("M5229 SEC: BASE %04x SIDE %04x\n", current_sec_base, current_sec_side); ali1543_log("M5229 SEC: BASE %04x SIDE %04x\n", current_sec_base, current_sec_side);
} }
} }

6
src/win/Makefile.mingw
View File

@@ -51,6 +51,9 @@ ifeq ($(DEV_BUILD), y)
ifndef I450KX ifndef I450KX
I450KX := y I450KX := y
endif endif
ifndef M154X
M145X := y
endif
ifndef LASERXT ifndef LASERXT
LASERXT := y LASERXT := y
endif endif
@@ -130,6 +133,9 @@ else
ifndef LASERXT ifndef LASERXT
LASERXT := n LASERXT := n
endif endif
ifndef M154X
M145X := n
endif
ifndef MGA ifndef MGA
MGA := n MGA := n
endif endif