The Intel SIO and PIIX* southbridges now have the undocumented (by the datasheets, but fully documented by the Intel motherboard technical specifications) second PIT on ports 48h-4Bh.

This commit is contained in:
OBattler
2021-04-13 03:47:46 +02:00
parent 5a228ba8db
commit 76f3f08d78
4 changed files with 21 additions and 2 deletions

View File

@@ -1374,6 +1374,8 @@ static void
else
dev->board_config[1] |= 0x00;
device_add(&i8254_sec_device);
return dev;
}

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@@ -539,6 +539,8 @@ sio_init(const device_t *info)
timer_add(&dev->timer, NULL, NULL, 0);
device_add(&i8254_sec_device);
return dev;
}

View File

@@ -109,6 +109,7 @@ extern void pit_handler(int set, uint16_t base, int size, void *priv);
#ifdef EMU_DEVICE_H
extern const device_t i8253_device;
extern const device_t i8254_device;
extern const device_t i8254_sec_device;
extern const device_t i8254_ext_io_device;
extern const device_t i8254_ps2_device;
#endif

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@@ -63,6 +63,7 @@ int64_t firsttime = 1;
#define PIT_PS2 16 /* The PIT is the PS/2's second PIT. */
#define PIT_EXT_IO 32 /* The PIT has externally specified port I/O. */
#define PIT_CUSTOM_CLOCK 64 /* The PIT uses custom clock inputs provided by another provider. */
#define PIT_SECONDARY 128 /* The PIT is secondary (ports 0048-004B). */
enum {
@@ -826,8 +827,10 @@ pit_init(const device_t *info)
dev->flags = info->local;
if (!(dev->flags & PIT_EXT_IO))
io_sethandler(0x0040, 0x0004, pit_read, NULL, NULL, pit_write, NULL, NULL, dev);
if (!(dev->flags & PIT_EXT_IO)) {
io_sethandler((dev->flags & PIT_SECONDARY) ? 0x0048 : 0x0040, 0x0004,
pit_read, NULL, NULL, pit_write, NULL, NULL, dev);
}
return dev;
}
@@ -855,6 +858,17 @@ const device_t i8254_device =
};
const device_t i8254_sec_device =
{
"Intel 8254 Programmable Interval Timer (Secondary)",
DEVICE_ISA,
PIT_8254 | PIT_SECONDARY,
pit_init, pit_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t i8254_ext_io_device =
{
"Intel 8254 Programmable Interval Timer (External I/O)",