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Various improvements to PCI and PCI boards.

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This commit is contained in:
OBattler
2017-09-04 05:15:12 +02:00
parent 4c3532f31e
commit 0ef876ef36
12 changed files with 274 additions and 53 deletions
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2
src/fdc37c665.c
View File

@@ -278,7 +278,7 @@ void fdc37c665_reset(void)
memset(fdc37c665_lock, 0, 2);
memset(fdc37c665_regs, 0, 16);
fdc37c665_regs[0x0] = 0x3b;
fdc37c665_regs[0x0] = 0x3a;
fdc37c665_regs[0x1] = 0x9f;
fdc37c665_regs[0x2] = 0xdc;
fdc37c665_regs[0x3] = 0x78;

6
src/fdc37c932fr.c
View File

@@ -199,8 +199,6 @@ void fdc37c932fr_write(uint16_t port, uint8_t val, void *priv)
valxor = val ^ fdc37c932fr_ld_regs[fdc37c932fr_regs[7]][fdc37c932fr_curreg];
if (((fdc37c932fr_curreg & 0xF0) == 0x70) && (fdc37c932fr_regs[7] < 4)) return;
/* Block writes to IDE configuration. */
if (fdc37c932fr_regs[7] == 1) return;
if (fdc37c932fr_regs[7] == 2) return;
if (fdc37c932fr_regs[7] > 5) return;
fdc37c932fr_ld_regs[fdc37c932fr_regs[7]][fdc37c932fr_curreg] = val;
goto process_value;
@@ -419,7 +417,7 @@ void fdc37c932fr_reset(void)
fdc37c932fr_ld_regs[0][0xF2] = 0xFF;
/* Logical device 1: IDE1 */
fdc37c932fr_ld_regs[1][0x30] = 1;
fdc37c932fr_ld_regs[1][0x30] = 0;
fdc37c932fr_ld_regs[1][0x60] = 1;
fdc37c932fr_ld_regs[1][0x61] = 0xF0;
fdc37c932fr_ld_regs[1][0x62] = 3;
@@ -428,7 +426,7 @@ void fdc37c932fr_reset(void)
fdc37c932fr_ld_regs[1][0xF0] = 0xC;
/* Logical device 2: IDE2 */
fdc37c932fr_ld_regs[2][0x30] = 1;
fdc37c932fr_ld_regs[2][0x30] = 0;
fdc37c932fr_ld_regs[2][0x60] = 1;
fdc37c932fr_ld_regs[2][0x61] = 0x70;
fdc37c932fr_ld_regs[2][0x62] = 3;

50
src/hdd/hdd_ide_at.c
View File

@@ -160,6 +160,8 @@ int ide_irq[5] = { 14, 15, 10, 11, 0 };
void ide_irq_raise(IDE *ide)
{
/* pclog("Attempting to raise IRQ %i (board %i)\n", ide_irq[ide->board], ide->board); */
if ((ide->board > 3) || ide->irqstat)
{
ide->irqstat=1;
@@ -172,9 +174,9 @@ void ide_irq_raise(IDE *ide)
if (!(ide->fdisk&2))
{
if (PCI && (ide->board < 2) && ide_bus_master_set_irq)
if (pci_use_mirq(0) && (ide->board < 2))
{
pci_ide_set_irq(ide->board, ide_irq[ide->board]);
pci_set_mirq(0, ide->board);
}
else
{
@@ -185,7 +187,7 @@ void ide_irq_raise(IDE *ide)
{
if (ide_bus_master_set_irq)
{
ide_bus_master_set_irq(ide->board);
ide_bus_master_set_irq(ide->board | 0x40);
}
}
}
@@ -204,14 +206,19 @@ void ide_irq_lower(IDE *ide)
ide_log("Lowering IRQ %i (board %i)\n", ide_irq[ide->board], ide->board);
if (PCI && (ide->board < 2) && ide_bus_master_set_irq)
if (pci_use_mirq(0) && (ide->board < 2))
{
pci_ide_clear_irq(ide->board, ide_irq[ide->board]);
pci_clear_mirq(0, ide->board);
}
else
{
picintc(1 << ide_irq[ide->board]);
}
if (ide_bus_master_set_irq)
{
ide_bus_master_set_irq(ide->board);
}
ide->irqstat=0;
}
@@ -225,6 +232,8 @@ void ide_irq_update(IDE *ide)
return;
}
ide_log("Updating IRQ %i (board %i)\n", ide_irq[ide->board], ide->board);
mask = ide_irq[ide->board];
mask &= 7;
@@ -233,25 +242,41 @@ void ide_irq_update(IDE *ide)
if (ide->irqstat && !pending && !(ide->fdisk & 2))
{
if (PCI && (ide->board < 2) && ide_bus_master_set_irq)
if (pci_use_mirq(0) && (ide->board < 2))
{
pci_ide_set_irq(ide->board, ide_irq[ide->board]);
pci_set_mirq(0, ide->board);
}
else
{
picint(1 << ide_irq[ide->board]);
}
if (ide->board < 2)
{
if (ide_bus_master_set_irq)
{
ide_bus_master_set_irq(ide->board | 0x40);
}
}
}
else if (pending)
{
if (PCI && (ide->board < 2) && ide_bus_master_set_irq)
if (pci_use_mirq(0) && (ide->board < 2))
{
pci_ide_clear_irq(ide->board, ide_irq[ide->board]);
pci_clear_mirq(0, ide->board);
}
else
{
picintc(1 << ide_irq[ide->board]);
}
if (ide->board < 2)
{
if (ide_bus_master_set_irq)
{
ide_bus_master_set_irq(ide->board);
}
}
}
}
/**
@@ -1410,7 +1435,7 @@ uint8_t readide(int ide_board, uint16_t addr)
ide_irq_lower(ide);
if (ide->type == IDE_NONE)
{
return 0;
temp = 0;
}
if (ide_drive_is_cdrom(ide))
{
@@ -1425,7 +1450,7 @@ uint8_t readide(int ide_board, uint16_t addr)
case 0x3F6: /* Alternate Status */
if (ide->type == IDE_NONE)
{
return 0;
temp = 0;
}
if (ide_drive_is_cdrom(ide))
{
@@ -1438,7 +1463,8 @@ uint8_t readide(int ide_board, uint16_t addr)
break;
default:
return 0xff;
temp = 0xff;
break;
}
/* if (ide_board) */ ide_log("Read IDEb %04X %02X %02X %02X %i %04X:%04X %i\n", addr, temp, ide->atastat,(ide->atastat & ~DSC_STAT) | (ide->service ? SERVICE_STAT : 0),cur_ide[ide_board],CS,cpu_state.pc,ide_board);
return temp;

15
src/keyboard_at.c
View File

@@ -96,6 +96,8 @@ static int key_queue_start = 0, key_queue_end = 0;
static uint8_t mouse_queue[16];
int mouse_queue_start = 0, mouse_queue_end = 0;
static uint8_t mouse_enabled;
int first_write = 1;
int dtrans = 0;
@@ -151,7 +153,7 @@ static void keyboard_at_poll(void)
keyboard_at.wantirq = 0;
if (keyboard_at.out_new & 0x100)
{
if (keyboard_at.mem[0] & 0x02)
if ((keyboard_at.mem[0] & 0x02) && mouse_enabled)
picint(0x1000);
keyboard_at.out = keyboard_at.out_new & 0xff;
keyboard_at.out_new = -1;
@@ -731,6 +733,12 @@ bad_command:
}
}
void keyboard_at_mouse_set_enabled(uint8_t enabled)
{
/* pclog("Keyboard AT mouse: %i\n", enabled); */
mouse_enabled = enabled;
}
uint8_t keyboard_at_read(uint16_t port, void *priv)
{
uint8_t temp = 0xff;
@@ -743,7 +751,10 @@ uint8_t keyboard_at_read(uint16_t port, void *priv)
{
/* The PIIX/PIIX3 datasheet mandates that both of these interrupts are cleared on any read of port 0x60. */
picintc(1 << 1);
picintc(1 << 12);
if (mouse_enabled)
{
picintc(1 << 12);
}
}
else
{

1
src/keyboard_at.h
View File

@@ -27,3 +27,4 @@ extern void keyboard_at_reset(void);
extern void keyboard_at_adddata_keyboard_raw(uint8_t val);
extern void keyboard_at_adddata_mouse(uint8_t val);
extern void keyboard_at_set_mouse(void (*mouse_write)(uint8_t val, void *p), void *p);
extern void keyboard_at_mouse_set_enabled(uint8_t enabled);

2
src/machine/machine_at_430fx.c
View File

@@ -211,7 +211,7 @@ void machine_at_p54tp4xe_init(void)
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
i430fx_init();
piix_init(7);
piix3_init(7);
fdc37c665_init();
device_add(&intel_flash_bxt_device);
}

6
src/network/net_ne2000.c
View File

@@ -239,9 +239,9 @@ nic_interrupt(nic_t *dev, int set)
{
if (PCI && dev->is_pci) {
if (set)
pci_set_irq(dev->card, PCI_INTC);
pci_set_irq(dev->card, PCI_INTA);
else
pci_clear_irq(dev->card, PCI_INTC);
pci_clear_irq(dev->card, PCI_INTA);
} else {
if (set)
picint(1<<dev->base_irq);
@@ -1981,7 +1981,7 @@ nic_init(int board)
dev->pci_regs[0x2E] = (PCI_DEVID&0xff);
dev->pci_regs[0x2F] = (PCI_DEVID>>8);
dev->pci_regs[0x3D] = PCI_INTC; /* PCI_IPR */
dev->pci_regs[0x3D] = PCI_INTA; /* PCI_IPR */
/* Enable our address space in PCI. */
dev->pci_bar[0].addr_regs[0] = 0x01;

3
src/pc87306.c
View File

@@ -438,7 +438,8 @@ void pc87306_reset(void)
{
memset(pc87306_regs, 0, 29);
pc87306_regs[0] = 0x4B;
/* pc87306_regs[0] = 0x4B; */
pc87306_regs[0] = 0x0B;
pc87306_regs[1] = 0x01;
pc87306_regs[3] = 0x01;
pc87306_regs[5] = 0x0D;

162
src/pci.c
View File

@@ -33,6 +33,14 @@ static uint8_t elcr[2] = { 0, 0 };
static uint8_t pci_irqs[4];
typedef struct
{
uint8_t enabled;
uint8_t irq_line;
} pci_mirq_t;
static pci_mirq_t pci_mirqs[2];
static int pci_index, pci_func, pci_card, pci_bus, pci_enable, pci_key;
int pci_burst_time, pci_nonburst_time;
@@ -220,6 +228,16 @@ void pci_set_irq_routing(int pci_int, int irq)
pci_irqs[pci_int - 1] = irq;
}
void pci_enable_mirq(int mirq)
{
pci_mirqs[mirq].enabled = 1;
}
void pci_set_mirq_routing(int mirq, int irq)
{
pci_mirqs[mirq].irq_line = irq;
}
static int pci_irq_is_level(int irq)
{
int real_irq = irq & 7;
@@ -234,7 +252,7 @@ static int pci_irq_is_level(int irq)
}
}
void pci_issue_irq(int irq)
static void pci_issue_irq(int irq)
{
/* pci_log("Issuing PCI IRQ %i: ", irq); */
if (pci_irq_is_level(irq))
@@ -249,24 +267,85 @@ void pci_issue_irq(int irq)
}
}
void pci_ide_set_irq(int ide_board, int irq)
uint8_t pci_use_mirq(uint8_t mirq)
{
if (pci_irq_is_level(irq) && (pci_irq_hold[irq] & (1LL << (0x20LL + ide_board))))
if (!PCI || !pci_mirqs[0].enabled)
{
/* IRQ already held, do nothing. */
return 0;
}
if (pci_mirqs[mirq].irq_line & 0x80)
{
return 0;
}
return 1;
}
#define pci_mirq_log pci_log
void pci_set_mirq(uint8_t mirq, uint8_t channel)
{
uint8_t irq_line = 0;
uint8_t level = 0;
if (channel > 1)
{
pci_mirq_log("pci_set_mirq(%02X, %02X): Invalid MIRQ\n", mirq, channel);
return;
}
if (!pci_irq_is_level(irq) || !pci_irq_hold[irq])
if (!pci_mirqs[mirq].enabled)
{
/* Only raise the interrupt if it's edge-triggered or level-triggered and not yet being held. */
pci_issue_irq(irq);
pci_mirq_log("pci_set_mirq(%02X, %02X): MIRQ0 disabled\n", mirq, channel);
return;
}
/* If the IRQ is level-triggered, mark that this card is holding it. */
if (pci_irq_is_level(irq))
if (pci_mirqs[mirq].irq_line > 0x0F)
{
pci_irq_hold[irq] |= (1LL << (0x20LL + ide_board));
pci_mirq_log("pci_set_mirq(%02X, %02X): IRQ line is disabled\n", mirq, channel);
return;
}
else
{
irq_line = pci_mirqs[mirq].irq_line ^ (channel ^ 1);
pci_mirq_log("pci_set_mirq(%02X, %02X): Using IRQ %i\n", mirq, channel, irq_line);
}
if (pci_irq_is_level(irq_line) && (pci_irq_hold[irq_line] & (1 << (0x1C + (mirq << 1) + channel))))
{
/* IRQ already held, do nothing. */
pci_mirq_log("pci_set_mirq(%02X, %02X): MIRQ is already holding the IRQ\n", mirq, channel);
return;
}
else
{
pci_mirq_log("pci_set_mirq(%02X, %02X): MIRQ not yet holding the IRQ\n", mirq, channel);
}
level = pci_irq_is_level(irq_line);
if (!level || !pci_irq_hold[irq_line])
{
pci_mirq_log("pci_set_mirq(%02X, %02X): Issuing %s-triggered IRQ (%sheld)\n", mirq, channel, level ? "level" : "edge", pci_irq_hold[irq_line] ? "" : "not ");
/* Only raise the interrupt if it's edge-triggered or level-triggered and not yet being held. */
pci_issue_irq(irq_line);
}
else if (level && pci_irq_hold[irq_line])
{
pci_mirq_log("pci_set_mirq(%02X, %02X): IRQ line already being held\n", mirq, channel);
}
/* If the IRQ is level-triggered, mark that this MIRQ is holding it. */
if (level)
{
pci_mirq_log("pci_set_mirq(%02X, %02X): Marking that this card is holding the IRQ\n", mirq, channel);
pci_irq_hold[irq_line] |= (1 << (0x1C + (mirq << 1) + channel));
}
else
{
pci_mirq_log("pci_set_mirq(%02X, %02X): Edge-triggered interrupt, not marking\n", mirq, channel);
}
}
@@ -359,19 +438,64 @@ void pci_set_irq(uint8_t card, uint8_t pci_int)
}
}
void pci_ide_clear_irq(int ide_board, int irq)
void pci_clear_mirq(uint8_t mirq, uint8_t channel)
{
if (pci_irq_is_level(irq))
uint8_t irq_line = 0;
uint8_t level = 0;
mirq = 0;
if (mirq > 1)
{
pci_irq_hold[irq] &= ~(1LL << (0x20LL + ide_board));
if (!pci_irq_hold[irq])
pci_mirq_log("pci_clear_mirq(%02X %02X): Invalid MIRQ\n", mirq, channel);
return;
}
if (!pci_mirqs[mirq].enabled)
{
pci_mirq_log("pci_clear_mirq(%02X %02X): MIRQ0 disabled\n", mirq, channel);
return;
}
if (pci_mirqs[mirq].irq_line > 0x0F)
{
pci_mirq_log("pci_clear_mirq(%02X %02X): IRQ line is disabled\n", mirq, channel);
return;
}
else
{
irq_line = pci_mirqs[mirq].irq_line ^ (channel ^ 1);
pci_mirq_log("pci_clear_mirq(%02X %02X): Using IRQ %i\n", mirq, channel, irq_line);
}
if (pci_irq_is_level(irq_line) && !(pci_irq_hold[irq_line] & (1 << (0x1C + (mirq << 1) + channel))))
{
/* IRQ not held, do nothing. */
pci_mirq_log("pci_clear_mirq(%02X %02X): MIRQ is not holding the IRQ\n", mirq, channel);
return;
}
level = pci_irq_is_level(irq_line);
if (level)
{
pci_mirq_log("pci_clear_mirq(%02X %02X): Releasing this MIRQ's hold on the IRQ\n", mirq, channel);
pci_irq_hold[irq_line] &= ~(1 << (0x1C + (mirq << 1) + channel));
if (!pci_irq_hold[irq_line])
{
picintc(1 << irq);
pci_mirq_log("pci_clear_mirq(%02X %02X): IRQ no longer held by any card, clearing it\n", mirq, channel);
picintc(1 << irq_line);
}
else
{
pci_mirq_log("pci_clear_mirq(%02X %02X): IRQ is still being held\n", mirq, channel);
}
}
else
{
picintc(1 << irq);
pci_mirq_log("pci_clear_mirq(%02X %02X): Clearing edge-triggered interrupt\n", mirq, channel);
picintc(1 << irq_line);
}
}
@@ -592,6 +716,12 @@ void pci_init(int type)
pci_irqs[c] = PCI_IRQ_DISABLED;
}
for (c = 0; c < 2; c++)
{
pci_mirqs[c].enabled = 0;
pci_mirqs[c].irq_line = PCI_IRQ_DISABLED;
}
pci_reset_handler.pci_master_reset = NULL;
pci_reset_handler.pci_set_reset = NULL;
pci_reset_handler.super_io_reset = NULL;

12
src/pci.h
View File

@@ -1,8 +1,13 @@
void pci_set_irq_routing(int pci_int, int irq);
void pci_ide_set_irq(int ide_board, int irq);
void pci_enable_mirq(int mirq);
void pci_set_mirq_routing(int mirq, int irq);
uint8_t pci_use_mirq(uint8_t mirq);
void pci_set_mirq(uint8_t mirq, uint8_t channel);
void pci_set_irq(uint8_t card, uint8_t pci_int);
void pci_ide_clear_irq(int ide_board, int irq);
void pci_clear_mirq(uint8_t mirq, uint8_t channel);
void pci_clear_irq(uint8_t card, uint8_t pci_int);
void pci_reset(void);
@@ -23,6 +28,9 @@ uint8_t pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, void
#define PCI_INTC 3
#define PCI_INTD 4
#define PCI_MIRQ0 0
#define PCI_MIRQ1 1
#define PCI_IRQ_DISABLED -1
enum

60
src/piix.c
View File

@@ -26,6 +26,7 @@
#include "ibm.h"
#include "dma.h"
#include "io.h"
#include "keyboard_at.h"
#include "mem.h"
#include "pci.h"
#include "hdd/hdd_ide_at.h"
@@ -50,6 +51,8 @@ void piix_write(int func, int addr, uint8_t val, void *priv)
if (func == 1) /*IDE*/
{
/* pclog("PIIX IDE write: %02X %02X\n", addr, val); */
switch (addr)
{
case 0x04:
@@ -148,6 +151,27 @@ void piix_write(int func, int addr, uint8_t val, void *priv)
else
pci_set_irq_routing(PCI_INTD, val & 0xf);
break;
case 0x70:
pclog("Set MIRQ routing: MIRQ0 -> %02X\n", val);
if (val & 0x80)
pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ0, val & 0xf);
break;
case 0x71:
if (piix_type == 1)
{
pclog("Set MIRQ routing: MIRQ1 -> %02X\n", val);
if (val & 0x80)
pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ1, val & 0xf);
}
else
{
pclog("Set unused MIRQ routing: MIRQ1 -> %02X\n", val);
}
break;
}
if (addr == 0x4C)
{
@@ -174,6 +198,14 @@ void piix_write(int func, int addr, uint8_t val, void *priv)
dma_alias_set();
}
}
else if (addr == 0x4E)
{
if ((val ^ card_piix[addr]) & 0x10)
{
keyboard_at_mouse_set_enabled((val & 0x10) ? 1 : 0);
}
card_piix[addr] = val;
}
else if (addr == 0x6A)
{
if (piix_type == 1)
@@ -384,6 +416,7 @@ static void piix_bus_master_next_addr(int channel)
void piix_bus_master_write(uint16_t port, uint8_t val, void *priv)
{
/* pclog("PIIX Bus master write: %04X %02X\n", port, val); */
int channel = (port & 8) ? 1 : 0;
switch (port & 7)
{
@@ -424,6 +457,7 @@ void piix_bus_master_write(uint16_t port, uint8_t val, void *priv)
uint8_t piix_bus_master_read(uint16_t port, void *priv)
{
/* pclog("PIIX Bus master read: %04X\n", port); */
int channel = (port & 8) ? 1 : 0;
switch (port & 7)
{
@@ -570,7 +604,9 @@ int piix_bus_master_dma_write(int channel, uint8_t *data, int transfer_length)
void piix_bus_master_set_irq(int channel)
{
piix_busmaster[channel].status |= 4;
// piix_busmaster[channel].status |= 4;
piix_busmaster[channel & 0x0F].status &= ~4;
piix_busmaster[channel & 0x0F].status |= (channel >> 4);
}
/* static int reset_reg = 0;
@@ -619,7 +655,7 @@ void piix_reset(void)
card_piix[0x4e] = 0x03;
card_piix[0x60] = card_piix[0x61] = card_piix[0x62] = card_piix[0x63] = 0x80;
card_piix[0x69] = 0x02;
card_piix[0x70] = card_piix[0x71] = 0x80;
card_piix[0x70] = card_piix[0x71] = 0xc0;
card_piix[0x76] = card_piix[0x77] = 0x0c;
card_piix[0x78] = 0x02; card_piix[0x79] = 0x00;
card_piix[0xa0] = 0x08;
@@ -639,8 +675,11 @@ void piix_reset(void)
card_piix_ide[0x0d] = 0x00;
card_piix_ide[0x0e] = 0x00;
card_piix_ide[0x20] = 0x01; card_piix_ide[0x21] = card_piix_ide[0x22] = card_piix_ide[0x23] = 0x00; /*Bus master interface base address*/
card_piix_ide[0x40] = card_piix_ide[0x41] = 0x00;
card_piix_ide[0x42] = card_piix_ide[0x43] = 0x00;
card_piix_ide[0x40] = card_piix_ide[0x42] = 0x00;
card_piix_ide[0x41] = card_piix_ide[0x43] = 0x80;
pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED);
pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED);
}
void piix3_reset(void)
@@ -657,7 +696,7 @@ void piix3_reset(void)
card_piix[0x4e] = card_piix[0x4f] = 0x03;
card_piix[0x60] = card_piix[0x61] = card_piix[0x62] = card_piix[0x63] = 0x80;
card_piix[0x69] = 0x02;
card_piix[0x70] = 0x80;
card_piix[0x70] = 0xc0;
card_piix[0x76] = card_piix[0x77] = 0x0c;
card_piix[0x78] = 0x02; card_piix[0x79] = 0x00;
card_piix[0x80] = card_piix[0x82] = 0x00;
@@ -678,9 +717,11 @@ void piix3_reset(void)
card_piix_ide[0x0d] = 0x00;
card_piix_ide[0x0e] = 0x00;
card_piix_ide[0x20] = 0x01; card_piix_ide[0x21] = card_piix_ide[0x22] = card_piix_ide[0x23] = 0x00; /*Bus master interface base address*/
card_piix_ide[0x40] = card_piix_ide[0x41] = 0x00;
card_piix_ide[0x42] = card_piix_ide[0x43] = 0x00;
card_piix_ide[0x40] = card_piix_ide[0x42] = 0x00;
card_piix_ide[0x41] = card_piix_ide[0x43] = 0x80;
card_piix_ide[0x44] = 0x00;
pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED);
}
void piix_init(int card)
@@ -700,6 +741,9 @@ void piix_init(int card)
dma_alias_set();
pci_reset_handler.pci_set_reset = piix_reset;
pci_enable_mirq(0);
pci_enable_mirq(1);
}
void piix3_init(int card)
@@ -719,4 +763,6 @@ void piix3_init(int card)
dma_alias_set();
pci_reset_handler.pci_set_reset = piix3_reset;
pci_enable_mirq(0);
}

8
src/scsi/scsi_buslogic.c
View File

@@ -552,11 +552,11 @@ BuslogicInterrupt(Buslogic_t *bl, int set)
{
if (set)
{
pci_set_irq(bl->Card, PCI_INTB);
pci_set_irq(bl->Card, PCI_INTA);
}
else
{
pci_clear_irq(bl->Card, PCI_INTB);
pci_clear_irq(bl->Card, PCI_INTA);
}
}
else
@@ -713,7 +713,7 @@ BuslogicAutoSCSIRamSetDefaults(Buslogic_t *bl, uint8_t safe)
HALR->structured.autoSCSIData.u16FastPermittedMask = 0xffff;
HALR->structured.autoSCSIData.u16DisconnectPermittedMask = 0xffff;
HALR->structured.autoSCSIData.uPCIInterruptPin = PCI_INTB;
HALR->structured.autoSCSIData.uPCIInterruptPin = PCI_INTA;
HALR->structured.autoSCSIData.fVesaBusSpeedGreaterThan33MHz = 1;
HALR->structured.autoSCSIData.uAutoSCSIMaximumLUN = 7;
@@ -2702,7 +2702,7 @@ BuslogicPCIRead(int func, int addr, void *p)
case 0x3C:
return bl->Irq;
case 0x3D:
return PCI_INTB;
return PCI_INTA;
}
return(0);