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Initial implementation of STPC chipsets and machines

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This commit is contained in:
RichardG867
2020-07-06 18:45:34 -03:00
parent 042f743a35
commit 11114c97d2
9 changed files with 688 additions and 17 deletions
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549
src/chipset/stpc.c Normal file
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@@ -0,0 +1,549 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the STPC series of SoCs.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct stpc_t
{
/* ISA (port 22h/23h) */
uint8_t isa_offset;
uint8_t isa_regs[256];
/* Host bus interface */
uint16_t host_base;
uint8_t host_offset;
uint8_t host_regs[256];
/* Local bus */
uint16_t localbus_base;
uint8_t localbus_offset;
uint8_t localbus_regs[256];
/* PCI */
uint8_t pci_conf[2][256];
} stpc_t;
#define ENABLE_STPC_LOG 1
#ifdef ENABLE_STPC_LOG
int stpc_do_log = ENABLE_STPC_LOG;
static void
stpc_log(const char *fmt, ...)
{
va_list ap;
if (stpc_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define stpc_log(fmt, ...)
#endif
static void
stpc_recalcmapping(stpc_t *dev)
{
uint8_t reg, bitpair;
uint32_t base, size;
int state;
shadowbios = 0;
shadowbios_write = 0;
for (reg = 0; reg <= 3; reg++) {
for (bitpair = 0; bitpair <= (reg == 3 ? 0 : 3); bitpair++) {
if (reg == 3) {
size = 0x10000;
base = 0xf0000;
} else {
size = 0x4000;
base = 0xc0000 + (size * ((reg * 4) + bitpair));
}
stpc_log("STPC: Shadowing for %05x-%05x (reg %02x bp %d wmask %02x rmask %02x) =", base, base + size - 1, 0x25 + reg, bitpair, 1 << (bitpair * 2), 1 << ((bitpair * 2) + 1));
state = 0;
if (dev->isa_regs[0x25 + reg] & (1 << (bitpair * 2))) {
stpc_log(" w on");
state |= MEM_WRITE_INTERNAL;
if (base >= 0xe0000)
shadowbios_write |= 1;
} else {
stpc_log(" w off");
state |= MEM_WRITE_EXTANY;
}
if (dev->isa_regs[0x25 + reg] & (1 << ((bitpair * 2) + 1))) {
stpc_log("; r on\n");
state |= MEM_READ_INTERNAL;
if (base >= 0xe0000)
shadowbios |= 1;
} else {
stpc_log("; r off\n");
state |= MEM_READ_EXTANY;
}
mem_set_mem_state(base, size, state);
}
}
flushmmucache();
}
static void
stpc_smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
{
mem_set_mem_state_smram(smm, addr, size, is_smram);
}
static void
stpc_host_write(uint16_t addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: host_write(%04x, %02x)\n", addr, val);
if (addr == dev->host_base)
dev->host_offset = val;
else if (addr == dev->host_base + 4)
dev->host_regs[dev->host_offset] = val;
}
static uint8_t
stpc_host_read(uint16_t addr, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (addr == dev->host_base)
ret = dev->host_offset;
else if (addr == dev->host_base + 4)
ret = dev->host_regs[dev->host_offset];
else
ret = 0xff;
stpc_log("STPC: host_read(%04x) = %02x\n", addr, ret);
return ret;
}
static void
stpc_localbus_write(uint16_t addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: localbus_write(%04x, %02x)\n", addr, val);
if (addr == dev->localbus_base)
dev->localbus_offset = val;
else if (addr == dev->localbus_base + 4)
dev->localbus_regs[addr] = val;
}
static uint8_t
stpc_localbus_read(uint16_t addr, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (addr == dev->localbus_base)
ret = dev->localbus_offset;
else if (addr == dev->localbus_base + 4)
ret = dev->localbus_regs[dev->localbus_offset];
else
ret = 0xff;
stpc_log("STPC: localbus_read(%04x) = %02x\n", addr, ret);
return ret;
}
static void
stpc_nb_write(int func, int addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: nb_write(%d, %02x, %02x)\n", func, addr, val);
if (func > 0)
return;
switch (addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x04: case 0x08: case 0x09: case 0x0a:
case 0x0b: case 0x0e: case 0x54:
return;
case 0x05:
val &= 0x01;
break;
case 0x06:
val = 0;
break;
case 0x07:
val = 0x02;
break;
case 0x50:
val &= 0x1f;
break;
case 0x52:
val &= 0x70;
break;
}
dev->pci_conf[0][addr] = val;
}
static uint8_t
stpc_nb_read(int func, int addr, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (func > 0)
ret = 0xff;
else
ret = dev->pci_conf[0][addr];
stpc_log("STPC: nb_read(%d, %02x) = %02x\n", func, addr, ret);
return ret;
}
static void
stpc_sb_write(int func, int addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: sb_write(%d, %02x, %02x)\n", func, addr, val);
if (func > 0)
return;
switch(addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x04: case 0x08: case 0x09: case 0x0a:
case 0x0b: case 0x0e: case 0x54:
return;
case 0x05:
val &= 0x01;
break;
case 0x06:
val = 0;
break;
case 0x07:
val = 0x02;
break;
}
dev->pci_conf[1][addr] = val;
}
/* TODO: IDE and USB OHCI devices */
static uint8_t
stpc_sb_read(int func, int addr, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (func > 0)
ret = 0xff;
else
ret = dev->pci_conf[1][addr];
stpc_log("STPC: sb_read(%d, %02x) = %02x\n", func, addr, ret);
return ret;
}
static void
stpc_remap_host(stpc_t *dev, uint16_t host_base)
{
stpc_log("STPC: Remapping host bus from %04x to %04x\n", dev->host_base, host_base);
io_removehandler(dev->host_base, 5,
stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev);
if (host_base) {
io_sethandler(host_base, 5,
stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev);
}
dev->host_base = host_base;
}
static void
stpc_remap_localbus(stpc_t *dev, uint16_t localbus_base)
{
stpc_log("STPC: Remapping local bus from %04x to %04x\n", dev->localbus_base, localbus_base);
io_removehandler(dev->localbus_base, 5,
stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev);
if (localbus_base) {
io_sethandler(localbus_base, 5,
stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev);
}
dev->localbus_base = localbus_base;
}
static void
stpc_isa_write(uint16_t addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: isa_write(%04x, %02x)\n", addr, val);
if (addr == 0x22) {
dev->isa_offset = val;
} else {
stpc_log("STPC: isa_regs[%02x] = %02x\n", dev->isa_offset, val);
switch (dev->isa_offset) {
case 0x12:
if (dev->isa_regs[0x10] == 0x07)
stpc_remap_host(dev, (dev->host_base & 0xff00) | val);
else if (dev->isa_regs[0x10] == 0x06)
stpc_remap_localbus(dev, (dev->localbus_base & 0xff00) | val);
break;
case 0x13:
if (dev->isa_regs[0x10] == 0x07)
stpc_remap_host(dev, (dev->host_base & 0x00ff) | (val << 8));
else if (dev->isa_regs[0x10] == 0x06)
stpc_remap_localbus(dev, (dev->localbus_base & 0x00ff) | (val << 8));
break;
case 0x21:
val &= 0xfe;
break;
case 0x22:
val &= 0x7f;
break;
case 0x25: case 0x26: case 0x27: case 0x28:
if (dev->isa_offset == 0x28) {
val &= 0xe3;
stpc_smram_map(0, smram[0].host_base, smram[0].size, !!(val & 0x80));
}
dev->isa_regs[dev->isa_offset] = val;
stpc_recalcmapping(dev);
break;
case 0x29:
val &= 0x0f;
break;
case 0x36:
val &= 0x3f;
break;
}
dev->isa_regs[dev->isa_offset] = val;
}
}
static uint8_t
stpc_isa_read(uint16_t addr, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (addr == 0x22)
ret = dev->isa_offset;
else
ret = dev->isa_regs[dev->isa_offset];
stpc_log("STPC: isa_read(%04x) = %02x\n", addr, ret);
return ret;
}
static void
stpc_reset(void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: reset()\n");
memset(dev->isa_regs, 0, sizeof(dev->isa_regs));
dev->isa_regs[0x7b] = 0xff;
io_removehandler(0x22, 2,
stpc_isa_read, NULL, NULL, stpc_isa_write, NULL, NULL, dev);
io_sethandler(0x22, 2,
stpc_isa_read, NULL, NULL, stpc_isa_write, NULL, NULL, dev);
}
static void
stpc_setup(stpc_t *dev)
{
stpc_log("STPC: setup()\n");
memset(dev, 0, sizeof(stpc_t));
/* Northbridge */
dev->pci_conf[0][0x00] = 0x4A;
dev->pci_conf[0][0x01] = 0x10;
dev->pci_conf[0][0x02] = 0x0A;
dev->pci_conf[0][0x03] = 0x02;
dev->pci_conf[0][0x04] = 0x07;
dev->pci_conf[0][0x06] = 0x80;
dev->pci_conf[0][0x07] = 0x02;
dev->pci_conf[0][0x0b] = 0x06;
/* Southbridge */
dev->pci_conf[1][0x00] = 0x4A;
dev->pci_conf[1][0x01] = 0x10;
dev->pci_conf[1][0x02] = 0x10;
dev->pci_conf[1][0x03] = 0x02;
dev->pci_conf[1][0x04] = 0x07;
dev->pci_conf[1][0x06] = 0x80;
dev->pci_conf[1][0x07] = 0x02;
dev->pci_conf[1][0x0a] = 0x01;
dev->pci_conf[1][0x0b] = 0x06;
dev->pci_conf[1][0x0e] = 0x40;
/* IDE */
/* USB */
}
static void
stpc_close(void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: close()\n");
free(dev);
}
static void *
stpc_init(const device_t *info)
{
stpc_t *dev = (stpc_t *) malloc(sizeof(stpc_t));
stpc_log("STPC: init()\n");
pci_add_card(0x0B, stpc_nb_read, stpc_nb_write, dev);
pci_add_card(0x0C, stpc_sb_read, stpc_sb_write, dev);
/* IDE = 0x0D */
/* USB (Atlas only) = 0x0E */
stpc_setup(dev);
stpc_reset(dev);
smram[0].host_base = 0x000a0000;
smram[0].ram_base = 0x000a0000;
smram[0].size = 0x00020000;
mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, smram[0].size);
mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base);
stpc_smram_map(0, smram[0].host_base, smram[0].size, 0);
stpc_smram_map(1, smram[0].host_base, smram[0].size, 1);
device_add(&port_92_pci_device);
return dev;
}
const device_t stpc_consumer2_device =
{
"STPC Consumer-II",
DEVICE_PCI,
0,
stpc_init,
stpc_close,
stpc_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t stpc_elite_device =
{
"STPC Elite",
DEVICE_PCI,
0,
stpc_init,
stpc_close,
stpc_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t stpc_atlas_device =
{
"STPC Atlas",
DEVICE_PCI,
0,
stpc_init,
stpc_close,
stpc_reset,
NULL,
NULL,
NULL,
NULL
};

6
src/cpu/cpu.c
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@@ -61,7 +61,7 @@
#endif
#include "x87_timings.h"
/*#define ENABLE_CPU_LOG 1*/
#define ENABLE_CPU_LOG 1
static void cpu_write(uint16_t addr, uint8_t val, void *priv);
static uint8_t cpu_read(uint16_t addr, void *priv);
@@ -399,9 +399,9 @@ cpu_set(void)
hasfpu = (fpu_type != FPU_NONE);
hascache = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL);
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86 || cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86MX || cpu_s->cpu_type == CPU_Cx6x86L || cpu_s->cpu_type == CPU_CxGX1);
cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx486DX2 || cpu_s->cpu_type == CPU_Cx5x86 || cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86MX || cpu_s->cpu_type == CPU_Cx6x86L || cpu_s->cpu_type == CPU_CxGX1);
#else
cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86);
cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx486DX2 || cpu_s->cpu_type == CPU_Cx5x86);
#endif
cpu_16bitbus = (cpu_s->cpu_type == CPU_286 || cpu_s->cpu_type == CPU_386SX || cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC );

11
src/cpu/cpu.h
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@@ -132,15 +132,18 @@ extern CPU cpus_Am386SX[];
extern CPU cpus_Am386DX[];
extern CPU cpus_486SLC[];
extern CPU cpus_486DLC[];
extern CPU cpus_IBM386SLC[];
extern CPU cpus_IBM486SLC[];
extern CPU cpus_IBM486BL[];
extern CPU cpus_i486S1[];
extern CPU cpus_IBM386SLC[];
extern CPU cpus_IBM486SLC[];
extern CPU cpus_IBM486BL[];
extern CPU cpus_i486S1[];
extern CPU cpus_Am486S1[];
extern CPU cpus_Cx486S1[];
extern CPU cpus_i486[];
extern CPU cpus_Am486[];
extern CPU cpus_Cx486[];
#if defined(DEV_BRANCH) && defined(USE_STPC)
extern CPU cpus_STPC[];
#endif
extern CPU cpus_WinChip[];
extern CPU cpus_WinChip_SS7[];
extern CPU cpus_Pentium5V[];

8
src/cpu/cpu_table.c
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@@ -366,6 +366,14 @@ CPU cpus_Cx486[] = {
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#if defined(DEV_BRANCH) && defined(USE_STPC)
CPU cpus_STPC[] = {
{"STPC 100", CPU_Cx486DX2, fpus_internal, 100000000, 1.0, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"STPC 133", CPU_Cx486DX2, fpus_internal, 133333333, 2.0, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#endif
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
CPU cpus_6x863V[] = {
/*Cyrix 6x86*/

7
src/include/86box/chipset.h
View File

@@ -82,6 +82,13 @@ extern const device_t sis_85c496_ls486e_device;
extern const device_t sis_85c50x_device;
#endif
/* ST */
#if defined(DEV_BRANCH) && defined(USE_STPC)
extern const device_t stpc_consumer2_device;
extern const device_t stpc_elite_device;
extern const device_t stpc_atlas_device;
#endif
/* VIA */
extern const device_t via_vpx_device;
extern const device_t via_vp3_device;

5
src/include/86box/machine.h
View File

@@ -278,6 +278,11 @@ extern int machine_at_4dps_init(const machine_t *);
extern int machine_at_alfredo_init(const machine_t *);
extern int machine_at_486sp3g_init(const machine_t *);
extern int machine_at_486ap4_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_STPC)
extern int machine_at_arb1479_init(const machine_t *);
extern int machine_at_pcm9340_init(const machine_t *);
extern int machine_at_pcm5330_init(const machine_t *);
#endif
#ifdef EMU_DEVICE_H
extern const device_t *at_acera1g_get_device(void);

83
src/machine/m_at_386dx_486.c
View File

@@ -591,3 +591,86 @@ machine_at_486ap4_init(const machine_t *model)
return ret;
}
#if defined(DEV_BRANCH) && defined(USE_STPC)
int
machine_at_arb1479_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/arb1479/1479a.rom",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x0B, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x1F, PCI_CARD_NORMAL, 1, 0, 0, 0);
pci_register_slot(0x1E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x1D, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&w83977f_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&stpc_consumer2_device);
device_add(&sst_flash_29ee020_device);
return ret;
}
int
machine_at_pcm9340_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/pcm9340/9340v110.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x0B, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x1D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x1E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x1F, PCI_CARD_NORMAL, 2, 3, 4, 1);
device_add(&w83977f_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&stpc_elite_device);
device_add(&sst_flash_39sf020_device);
return ret;
}
int
machine_at_pcm5330_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/pcm5330/5330_13b.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x0B, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&w83977f_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&stpc_atlas_device);
device_add(&sst_flash_29ee020_device);
return ret;
}
#endif

23
src/machine/machine_table.c
View File

@@ -171,8 +171,8 @@ const machine_t machines[] = {
{ "[NEAT] DTK 386SX clone", "dtk386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_neat_init, NULL },
{ "[NEAT] Goldstar 386", "goldstar386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_goldstar386_init, NULL },
{ "[SCAT] KMX-C-02", "kmxc02", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 127, machine_at_kmxc02_init, NULL },
{ "[Intel 82335] Shuttle 386SX", "shuttle386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_shuttle386sx_init, NULL },
{ "[Intel 82335] ADI 386SX", "adi386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_adi386sx_init, NULL },
{ "[Intel 82335] Shuttle 386SX", "shuttle386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_shuttle386sx_init, NULL },
{ "[Intel 82335] ADI 386SX", "adi386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_adi386sx_init, NULL },
/* 386SX machines which utilize the MCA bus */
{ "[MCA] IBM PS/2 model 55SX", "ibmps2_m55sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"IBM",cpus_IBM486SLC},{"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 8, 1, 63, machine_ps2_model_55sx_init, NULL },
@@ -194,13 +194,13 @@ const machine_t machines[] = {
{ "[MCA] IBM PS/2 model 80", "ibmps2_m80", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"IBM",cpus_IBM486BL},{"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 12, 1, 63, machine_ps2_model_80_init, NULL },
/* 486 machines with just the ISA slot */
{ "[ACC 2168] Packard Bell PB410A", "pb410a", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 4, 36, 1, 127, machine_at_pb410a_init, NULL },
{ "[ACC 2168] Packard Bell PB410A", "pb410a", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 4, 36, 1, 127, machine_at_pb410a_init, NULL },
/* 486 machines */
{ "[OPTi 495] Award 486 clone", "award486", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_init, NULL },
{ "[OPTi 495] MR 486 clone", "mr486", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_mr_init, NULL },
{ "[OPTi 495] Dataexpert SX495 (486)", "ami486", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[OPTi 895] Jetway J-403TG", "403tg", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT, 1, 64, 1, 127, machine_at_403tg_init, NULL },
{ "[OPTi 895] Jetway J-403TG", "403tg", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT, 1, 64, 1, 127, machine_at_403tg_init, NULL },
{ "[SiS 471] ASUS VL/I-486SV2G (GX4)", "vli486sv2g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_vli486sv2g_init, NULL },
{ "[SiS 471] AMI 486 Clone", "ami471", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_ami471_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_WIN471)
@@ -208,10 +208,10 @@ const machine_t machines[] = {
#endif
{ "[SiS 471] DTK PKM-0038S E-2", "dtk486", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_dtk486_init, NULL },
{ "[SiS 471] Phoenix SiS 471", "px471", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_px471_init, NULL },
{ "[ALi M1429G] Acer A1G", "acera1g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO | MACHINE_PS2, 4, 36, 1, 127, machine_at_acera1g_init, at_acera1g_get_device },
{ "[ALi M1429G] Acer A1G", "acera1g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO | MACHINE_PS2, 4, 36, 1, 127, machine_at_acera1g_init, at_acera1g_get_device },
{ "[ALi M1429] Olystar LIL1429", "ali1429", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_ali1429_init, NULL },
{ "[ALi M1429] AMI WinBIOS 486", "win486", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_winbios1429_init, NULL },
{ "[VLSI 82c480] IBM PS/1 model 2133", "ibmps1_2133", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_NONMI | MACHINE_VIDEO, 1, 64, 1, 127, machine_ps1_m2133_init, ps1_m2133_get_device },
{ "[VLSI 82C480] IBM PS/1 model 2133", "ibmps1_2133", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_NONMI | MACHINE_VIDEO, 1, 64, 1, 127, machine_ps1_m2133_init, ps1_m2133_get_device },
/* 486 machines with utilize the MCA bus */
#if defined(DEV_BRANCH) && defined(USE_PS2M70T4)
@@ -225,6 +225,11 @@ const machine_t machines[] = {
{ "[SiS 496] Lucky Star LS-486E", "ls486e", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 255, machine_at_ls486e_init, NULL },
{ "[SiS 496] Rise Computer R418", "r418", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 255, machine_at_r418_init, NULL },
{ "[SiS 496] Zida Tomato 4DP", "4dps", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 255, machine_at_4dps_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_STPC)
{ "[STPC Consumer-II] Acrosser AR-B1479", "arb1479", MACHINE_TYPE_486, {{"ST", cpus_STPC}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 32, 160, 8, 255, machine_at_arb1479_init, NULL },
{ "[STPC Elite] Advantech PCM-9340", "pcm9340", MACHINE_TYPE_486, {{"ST", cpus_STPC}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 32, 32, 0, 255, machine_at_pcm9340_init, NULL },
{ "[STPC Atlas] AAEON PCM-5330", "pcm5330", MACHINE_TYPE_486, {{"ST", cpus_STPC}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 64, 64, 0, 255, machine_at_pcm5330_init, NULL },
#endif
/* Socket 4 machines */
/* OPTi 596/597 */
@@ -236,11 +241,11 @@ const machine_t machines[] = {
{ "[i430LX] IBM PS/ValuePoint P60", "valuepointp60", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_valuepointp60_init, NULL },
#endif
{ "[i430LX] Intel Premiere/PCI", "revenge", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_batman_init, NULL },
{ "[i430LX] Dell OptiPlex 560L", "opti560l", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_opti560l_init, NULL },
{ "[i430LX] Dell OptiPlex 560L", "opti560l", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_opti560l_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_VPP60)
{ "[i430LX] Dell Dimension XPS P60", "dellxp60", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_dellxp60_init, NULL },
{ "[i430LX] Dell Dimension XPS P60", "dellxp60", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_dellxp60_init, NULL },
#endif
{ "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 192, 2, 127, machine_at_p5mp3_init, NULL },
{ "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 192, 2, 127, machine_at_p5mp3_init, NULL },
{ "[i430LX] Micro Star 586MC1", "586mc1", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_586mc1_init, NULL },
/* Socket 5 machines */

13
src/win/Makefile.mingw
View File

@@ -69,6 +69,9 @@ ifeq ($(DEV_BUILD), y)
ifndef SIEMENS
SIEMENS := y
endif
ifndef STPC
STPC := y
endif
ifndef VGAWONDER
VGAWONDER := y
endif
@@ -133,6 +136,9 @@ else
ifndef SIEMENS
SIEMENS := n
endif
ifndef STPC
STPC := y
endif
ifndef VGAWONDER
VGAWONDER := n
endif
@@ -512,6 +518,11 @@ ifeq ($(SIEMENS), y)
OPTS += -DUSE_SIEMENS
endif
ifeq ($(STPC), y)
OPTS += -DUSE_STPC
STPCOBJ := stpc.o
endif
ifeq ($(596B), y)
OPTS += -DUSE_596B
endif
@@ -572,7 +583,7 @@ CPUOBJ := cpu.o cpu_table.o \
CHIPSETOBJ := acc2168.o cs8230.o ali1429.o headland.o i82335.o \
intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \
neat.o opti495.o opti895.o opti5x7.o scamp.o scat.o \
sis_85c310.o sis_85c471.o sis_85c496.o \
sis_85c310.o sis_85c471.o sis_85c496.o $(STPCOBJ) \
via_apollo.o via_vpx.o via_vt82c586b.o via_vt82c596b.o wd76c10.o vl82c480.o \
amd640.o