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Update ali1429.c

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This commit is contained in:
rueni97
2023-01-08 19:04:40 +03:00
committed by GitHub
parent d7a2bca9d7
commit 112b60eb88
1 changed files with 152 additions and 148 deletions
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300
src/chipset/ali1429.c
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@@ -1,23 +1,21 @@
/* /*
* 86Box A hypervisor and IBM PC system emulator that specializes in * 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM * running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent * PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus. * system designs based on the PCI bus.
* *
* This file is part of the 86Box distribution. * This file is part of the 86Box distribution.
* *
* Implementation of the ALi M1429 chipset. * Implementation of the ALi M1429 chipset.
* *
* Note: This chipset has no datasheet, everything were done via * Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it. * reverse engineering the BIOS of various machines using it.
* *
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
* *
* * Copyright 2020,2021 Tiseno100.
* Authors: Tiseno100, * Copyright 2021,2021 Miran Grca.
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2020-2021 Tiseno100.
* Copyright 2021-2021 Miran Grca.
*/ */
/* /*
@@ -66,14 +64,15 @@
Register 20h: Register 20h:
Bits 2-1-0: Bus Clock Speed Bits 2-1-0: Bus Clock Speed
0 0 0: 7.1519Mhz (ATCLK2) 0 0 0: 7.1519Mhz (ATCLK2)
0 0 1: CLK2IN/4 0 0 1: CLK2IN/4
0 1 0: CLK2IN/5 0 1 0: CLK2IN/5
0 1 1: CLK2IN/6 0 1 1: CLK2IN/6
1 0 0: CLK2IN/8 1 0 0: CLK2IN/8
1 0 1: CLK2IN/10 1 0 1: CLK2IN/10
1 1 0: CLK2IN/12 1 1 0: CLK2IN/12
*/ */
#include <stdarg.h> #include <stdarg.h>
#include <stdint.h> #include <stdint.h>
#include <stdio.h> #include <stdio.h>
@@ -95,11 +94,13 @@
#include <86box/smram.h> #include <86box/smram.h>
#include <86box/chipset.h> #include <86box/chipset.h>
#define GREEN dev->is_g /* Is G Variant */ #define GREEN dev->is_g /* Is G Variant */
#ifdef ENABLE_ALI1429_LOG #ifdef ENABLE_ALI1429_LOG
int ali1429_do_log = ENABLE_ALI1429_LOG; int ali1429_do_log = ENABLE_ALI1429_LOG;
static void static void
ali1429_log(const char *fmt, ...) ali1429_log(const char *fmt, ...)
{ {
@@ -112,25 +113,27 @@ ali1429_log(const char *fmt, ...)
} }
} }
#else #else
# define ali1429_log(fmt, ...) #define ali1429_log(fmt, ...)
#endif #endif
typedef struct typedef struct
{ {
uint8_t is_g, index, cfg_locked, reg_57h, uint8_t is_g, index, cfg_locked, reg_57h,
regs[90]; regs[90];
} ali1429_t; } ali1429_t;
static void static void
ali1429_shadow_recalc(ali1429_t *dev) ali1429_shadow_recalc(ali1429_t *dev)
{ {
uint32_t base, i, can_write, can_read; uint32_t base, i, can_write, can_read;
shadowbios = (dev->regs[0x13] & 0x40) && (dev->regs[0x14] & 0x01); shadowbios = (dev->regs[0x13] & 0x40) && (dev->regs[0x14] & 0x01);
shadowbios_write = (dev->regs[0x13] & 0x40) && (dev->regs[0x14] & 0x02); shadowbios_write = (dev->regs[0x13] & 0x40) && (dev->regs[0x14] & 0x02);
can_write = (dev->regs[0x14] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; can_write = (dev->regs[0x14] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
can_read = (dev->regs[0x14] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; can_read = (dev->regs[0x14] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
for (i = 0; i < 8; i++) { for (i = 0; i < 8; i++) {
base = 0xc0000 + (i << 15); base = 0xc0000 + (i << 15);
@@ -144,149 +147,149 @@ ali1429_shadow_recalc(ali1429_t *dev)
flushmmucache_nopc(); flushmmucache_nopc();
} }
static void static void
ali1429_write(uint16_t addr, uint8_t val, void *priv) ali1429_write(uint16_t addr, uint8_t val, void *priv)
{ {
ali1429_t *dev = (ali1429_t *) priv; ali1429_t *dev = (ali1429_t *)priv;
switch (addr) { switch (addr) {
case 0x22: case 0x22:
dev->index = val; dev->index = val;
break; break;
case 0x23: case 0x23:
#ifdef ENABLE_ALI1429_LOG #ifdef ENABLE_ALI1429_LOG
if (dev->index != 0x03) if (dev->index != 0x03)
ali1429_log("M1429: dev->regs[%02x] = %02x\n", dev->index, val); ali1429_log("M1429: dev->regs[%02x] = %02x\n", dev->index, val);
#endif #endif
if (dev->index == 0x03) if (dev->index == 0x03)
dev->cfg_locked = !(val == 0xc5); dev->cfg_locked = (val != 0xc5);
if (!dev->cfg_locked) { if (!dev->cfg_locked) {
/* Common M1429 Registers */ pclog("M1429: dev->regs[%02x] = %02x\n", dev->index, val);
switch (dev->index) {
case 0x10:
case 0x11:
dev->regs[dev->index] = val;
break;
case 0x12: /* Common M1429 Registers */
dev->regs[dev->index] = val; switch (dev->index) {
if (val & 4) case 0x10: case 0x11:
mem_remap_top(128); dev->regs[dev->index] = val;
else break;
mem_remap_top(0);
break;
case 0x13: case 0x12:
case 0x14: dev->regs[dev->index] = val;
dev->regs[dev->index] = val; if(val & 4)
ali1429_shadow_recalc(dev); mem_remap_top(128);
break; else
mem_remap_top(0);
break;
case 0x15: case 0x13: case 0x14:
case 0x16: dev->regs[dev->index] = val;
case 0x17: ali1429_shadow_recalc(dev);
dev->regs[dev->index] = val; break;
break;
case 0x18: case 0x15: case 0x16:
dev->regs[dev->index] = (val & 0x8f) | 0x20; case 0x17:
cpu_cache_ext_enabled = !!(val & 2); dev->regs[dev->index] = val;
cpu_update_waitstates(); break;
break;
case 0x19: case 0x18:
case 0x1a: dev->regs[dev->index] = (val & 0x8f) | 0x20;
case 0x1e: cpu_cache_ext_enabled = !!(val & 2);
dev->regs[dev->index] = val; cpu_update_waitstates();
break; break;
case 0x20: case 0x19: case 0x1a:
dev->regs[dev->index] = val; case 0x1e:
dev->regs[dev->index] = val;
break;
switch (val & 7) { case 0x20:
case 0: dev->regs[dev->index] = val;
case 7: /* Illegal */
cpu_set_isa_speed(7159091);
break;
case 1: switch(val & 7) {
cpu_set_isa_speed(cpu_busspeed / 4); case 0: case 7: /* Illegal */
break; cpu_set_isa_speed(7159091);
break;
case 2: case 1:
cpu_set_isa_speed(cpu_busspeed / 5); cpu_set_isa_speed(cpu_busspeed / 4);
break; break;
case 3: case 2:
cpu_set_isa_speed(cpu_busspeed / 6); cpu_set_isa_speed(cpu_busspeed / 5);
break; break;
case 4: case 3:
cpu_set_isa_speed(cpu_busspeed / 8); cpu_set_isa_speed(cpu_busspeed / 6);
break; break;
case 5: case 4:
cpu_set_isa_speed(cpu_busspeed / 10); cpu_set_isa_speed(cpu_busspeed / 8);
break; break;
case 6: case 5:
cpu_set_isa_speed(cpu_busspeed / 12); cpu_set_isa_speed(cpu_busspeed / 10);
break; break;
}
break;
case 0x21 ... 0x27: case 6:
dev->regs[dev->index] = val; cpu_set_isa_speed(cpu_busspeed / 12);
break; break;
} }
break;
/* M1429G Only Registers */ case 0x21 ... 0x27:
if (GREEN) { dev->regs[dev->index] = val;
switch (dev->index) { break;
case 0x30 ... 0x41: }
case 0x43:
case 0x45:
case 0x4a:
dev->regs[dev->index] = val;
break;
case 0x57: /* M1429G Only Registers */
dev->reg_57h = val; if (GREEN) {
break; switch (dev->index) {
} case 0x30 ... 0x41:
} case 0x43: case 0x45:
} case 0x4a:
break; dev->regs[dev->index] = val;
break;
case 0x57:
dev->reg_57h = val;
break;
}
}
}
break;
} }
} }
static uint8_t static uint8_t
ali1429_read(uint16_t addr, void *priv) ali1429_read(uint16_t addr, void *priv)
{ {
ali1429_t *dev = (ali1429_t *) priv; ali1429_t *dev = (ali1429_t *)priv;
uint8_t ret = 0xff; uint8_t ret = 0xff;
if ((addr == 0x23) && (dev->index >= 0x10) && (dev->index <= 0x4a)) if ((addr == 0x23) && (dev->index >= 0x10) && (dev->index <= 0x4a))
ret = dev->regs[dev->index]; ret = dev->regs[dev->index];
else if ((addr == 0x23) && (dev->index == 0x57)) else if ((addr == 0x23) && (dev->index == 0x57))
ret = dev->reg_57h; ret = dev->reg_57h;
else if (addr == 0x22) else if (addr == 0x22)
ret = dev->index; ret = dev->index;
return ret; return ret;
} }
static void static void
ali1429_close(void *priv) ali1429_close(void *priv)
{ {
ali1429_t *dev = (ali1429_t *) priv; ali1429_t *dev = (ali1429_t *)priv;
free(dev); free(dev);
} }
static void static void
ali1429_defaults(ali1429_t *dev) ali1429_defaults(ali1429_t *dev)
{ {
@@ -305,27 +308,28 @@ ali1429_defaults(ali1429_t *dev)
/* M1429G Default Registers */ /* M1429G Default Registers */
if (GREEN) { if (GREEN) {
dev->regs[0x31] = 0x88; dev->regs[0x31] = 0x88;
dev->regs[0x32] = 0xc0; dev->regs[0x32] = 0xc0;
dev->regs[0x38] = 0xe5; dev->regs[0x38] = 0xe5;
dev->regs[0x40] = 0xe3; dev->regs[0x40] = 0xe3;
dev->regs[0x41] = 2; dev->regs[0x41] = 2;
dev->regs[0x45] = 0x80; dev->regs[0x45] = 0x80;
} }
} }
static void * static void *
ali1429_init(const device_t *info) ali1429_init(const device_t *info)
{ {
ali1429_t *dev = (ali1429_t *) malloc(sizeof(ali1429_t)); ali1429_t *dev = (ali1429_t *)malloc(sizeof(ali1429_t));
memset(dev, 0, sizeof(ali1429_t)); memset(dev, 0, sizeof(ali1429_t));
dev->cfg_locked = 1; dev->cfg_locked = 1;
GREEN = info->local; GREEN = info->local;
/* M1429 Ports: /* M1429 Ports:
22h Index Port 22h Index Port
23h Data Port 23h Data Port
*/ */
io_sethandler(0x0022, 0x0002, ali1429_read, NULL, NULL, ali1429_write, NULL, NULL, dev); io_sethandler(0x0022, 0x0002, ali1429_read, NULL, NULL, ali1429_write, NULL, NULL, dev);
@@ -337,29 +341,29 @@ ali1429_init(const device_t *info)
} }
const device_t ali1429_device = { const device_t ali1429_device = {
.name = "ALi M1429", .name = "ALi M1429",
.internal_name = "ali1429", .internal_name = "ali1429",
.flags = 0, .flags = 0,
.local = 0, .local = 0,
.init = ali1429_init, .init = ali1429_init,
.close = ali1429_close, .close = ali1429_close,
.reset = NULL, .reset = NULL,
{ .available = NULL }, { .available = NULL },
.speed_changed = NULL, .speed_changed = NULL,
.force_redraw = NULL, .force_redraw = NULL,
.config = NULL .config = NULL
}; };
const device_t ali1429g_device = { const device_t ali1429g_device = {
.name = "ALi M1429G", .name = "ALi M1429G",
.internal_name = "ali1429g", .internal_name = "ali1429g",
.flags = 0, .flags = 0,
.local = 1, .local = 1,
.init = ali1429_init, .init = ali1429_init,
.close = ali1429_close, .close = ali1429_close,
.reset = NULL, .reset = NULL,
{ .available = NULL }, { .available = NULL },
.speed_changed = NULL, .speed_changed = NULL,
.force_redraw = NULL, .force_redraw = NULL,
.config = NULL .config = NULL
}; };