80486DX2-66/86Box-fork
1
0
Fork 0
Code Issues Pull Requests Activity

Apollo VPX bringup

Browse Source 
This commit brings Apollo VPX emulation on 86Box. It includes the Zida Tomato TX100 board. Meant mostly to check issues at WinBioses
This commit is contained in:
tiseno100
2020-04-17 12:34:39 +03:00
committed by GitHub
parent 31c4674a80
commit 16c1584412
7 changed files with 271 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

232
src/chipset/via_vpx.c Normal file
View File

@@ -0,0 +1,232 @@
/*
86Box A hypervisor and IBM PC system emulator that specializes in
running old operating systems and software designed for IBM
PC systems and compatibles from 1981 through fairly recent
system designs based on the PCI bus.
<This file is part of the 86Box distribution.>
VIA Apollo VPX North Bridge emulation
VT82C585VPX used in the Zida Tomato TX100 board
based on the model of VIA MVP3 by mooch & Sarah
Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
Copyright(C) 2020 Tiseno100
Copyright(C) 2020 Melissa Goad
Copyright(C) 2020 Miran Grca
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/chipset.h>
typedef struct via_vpx_t
{
uint8_t pci_conf[2][256];
} via_vpx_t;
static void
vpx_map(uint32_t addr, uint32_t size, int state)
{
switch (state & 3) {
case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 1:
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 2:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
case 3:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
flushmmucache_nopc();
}
static void
via_vpx_pci_regs(via_vpx_t *dev)
{
memset(dev, 0, sizeof(via_vpx_t));
// Host Bridge registers
dev->pci_conf[0][0x00] = 0x06; // VIA
dev->pci_conf[0][0x01] = 0x11;
dev->pci_conf[0][0x02] = 0x85; // VT82C585VPX
dev->pci_conf[0][0x03] = 0x05;
dev->pci_conf[0][0x04] = 7; // Command
dev->pci_conf[0][0x05] = 0;
dev->pci_conf[0][0x06] = 0xa0; // Status
dev->pci_conf[0][0x07] = 2;
dev->pci_conf[0][0x09] = 0; // Program Interface
dev->pci_conf[0][0x0a] = 0; // Sub Class Code
dev->pci_conf[0][0x0b] = 6; // Base Class Code
dev->pci_conf[0][0x0c] = 0; // reserved
dev->pci_conf[0][0x0d] = 0; // Latency Timer
dev->pci_conf[0][0x0e] = 0; // Header Type
dev->pci_conf[0][0x0f] = 0; // Built-in Self test
dev->pci_conf[0][0x58] = 0x40; // DRAM Configuration 1
dev->pci_conf[0][0x59] = 5; // DRAM Configuration 2
dev->pci_conf[0][0x5a] = 1; // Bank 0 Ending
dev->pci_conf[0][0x5b] = 1; // Bank 1 Ending
dev->pci_conf[0][0x5c] = 1; // Bank 2 Ending
dev->pci_conf[0][0x5d] = 1; // Bank 3 Ending
dev->pci_conf[0][0x5e] = 1; // Bank 4 Ending
dev->pci_conf[0][0x5f] = 1; // Bank 5 Ending
dev->pci_conf[0][0x64] = 0xab; // DRAM reference timing
}
static void
host_bridge_write(int func, int addr, uint8_t val, void *priv)
{
via_vpx_t *dev = (via_vpx_t *) priv;
// Read-Only registers. Exact same as MVP3
if ((addr < 4) || ((addr >= 5) && (addr < 7)) || ((addr >= 8) && (addr < 0xd)) || ((addr >= 0xe) && (addr < 0x12)) ||
((addr >= 0x14) && (addr < 0x50)) || ((addr >= 0x79) && (addr < 0x7e)) || ((addr >= 0x85) && (addr < 0x88)) ||
((addr >= 0x8c) && (addr < 0xa8)) || ((addr >= 0xad) && (addr < 0xfd)))
return;
switch(addr){
case 0x04: // Command
dev->pci_conf[0][0x04] = (dev->pci_conf[0][0x04] & ~0x40) | (val & 0x40);
case 0x07: // Status
dev->pci_conf[0][0x07] &= ~(val & 0xb0);
break;
case 0x61: // Shadow RAM control 1
if ((dev->pci_conf[0][0x61] ^ val) & 0x03)
vpx_map(0xc0000, 0x04000, val & 0x03);
if ((dev->pci_conf[0][0x61] ^ val) & 0x0c)
vpx_map(0xc4000, 0x04000, (val & 0x0c) >> 2);
if ((dev->pci_conf[0][0x61] ^ val) & 0x30)
vpx_map(0xc8000, 0x04000, (val & 0x30) >> 4);
if ((dev->pci_conf[0][0x61] ^ val) & 0xc0)
vpx_map(0xcc000, 0x04000, (val & 0xc0) >> 6);
dev->pci_conf[0][0x61] = val;
return;
case 0x62: // Shadow RAM Control 2
if ((dev->pci_conf[0][0x62] ^ val) & 0x03)
vpx_map(0xd0000, 0x04000, val & 0x03);
if ((dev->pci_conf[0][0x62] ^ val) & 0x0c)
vpx_map(0xd4000, 0x04000, (val & 0x0c) >> 2);
if ((dev->pci_conf[0][0x62] ^ val) & 0x30)
vpx_map(0xd8000, 0x04000, (val & 0x30) >> 4);
if ((dev->pci_conf[0][0x62] ^ val) & 0xc0)
vpx_map(0xdc000, 0x04000, (val & 0xc0) >> 6);
dev->pci_conf[0][0x62] = val;
return;
case 0x63: // Shadow RAM Control 3
if ((dev->pci_conf[0][0x63] ^ val) & 0x30) {
vpx_map(0xf0000, 0x10000, (val & 0x30) >> 4);
shadowbios = (((val & 0x30) >> 4) & 0x02);
}
if ((dev->pci_conf[0][0x63] ^ val) & 0xc0)
vpx_map(0xe0000, 0x10000, (val & 0xc0) >> 6);
dev->pci_conf[0][0x63] = val;
return;
//In case we throw somewhere
default:
dev->pci_conf[0][addr] = val;
break;
}
}
static uint8_t
via_vpx_read(int func, int addr, void *priv)
{
via_vpx_t *dev = (via_vpx_t *) priv;
uint8_t ret = 0xff;
switch(func) {
case 0:
ret = dev->pci_conf[0][addr];
break;
}
return ret;
}
static void
via_vpx_write(int func, int addr, uint8_t val, void *priv)
{
switch(func) {
case 0:
host_bridge_write(func, addr, val, priv);
break;
}
}
static void
via_vpx_reset(void *priv)
{
via_vpx_write(0, 0x63, via_vpx_read(0, 0x63, priv) & 0xcf, priv);
}
static void *
via_vpx_init(const device_t *info)
{
via_vpx_t *dev = (via_vpx_t *) malloc(sizeof(via_vpx_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, via_vpx_read, via_vpx_write, dev);
via_vpx_pci_regs(dev);
return dev;
}
static void
via_vpx_close(void *priv)
{
via_vpx_t *dev = (via_vpx_t *) priv;
free(dev);
}
const device_t via_vpx_device = {
"VIA Apollo VPX",
DEVICE_PCI,
0,
via_vpx_init,
via_vpx_close,
via_vpx_reset,
NULL,
NULL,
NULL,
NULL
};

1
src/include/86box/chipset.h
View File

@@ -63,6 +63,7 @@ extern const device_t sis_85c50x_device;
#endif
/* VIA */
extern const device_t via_vpx_device;
extern const device_t via_vp3_device;
extern const device_t via_mvp3_device;
extern const device_t via_apro_device;

5
src/include/86box/machine.h
View File

@@ -302,12 +302,13 @@ extern int machine_at_586t2_init(const machine_t *);
extern int machine_at_807ds_init(const machine_t *);
extern int machine_at_p5mms98_init(const machine_t *);
extern int machine_at_tx100_init(const machine_t *);
extern int machine_at_advanceii_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *at_pb640_get_device(void);
#endif
extern int machine_at_advanceii_init(const machine_t *);
/* m_at_super7_ss7.c */
extern int machine_at_ax59pro_init(const machine_t *);
extern int machine_at_mvp3_init(const machine_t *);

30
src/machine/m_at_socket7_s7.c
View File

@@ -833,6 +833,36 @@ machine_at_p5mms98_init(const machine_t *model)
return ret;
}
int
machine_at_tx100_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/tx100/T100108E.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
device_add(&via_vpx_device);
device_add(&via_vt82c586b_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&um8669f_device); //IT8661F
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
return ret;
}
int
machine_at_advanceii_init(const machine_t *model)
{

4
src/machine/machine_table.c
View File

@@ -250,7 +250,9 @@ const machine_t machines[] = {
{ "[Socket 7 TX] Iwill P55XB2", "p55xb2", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_p55xb2_init, NULL },
{ "[Socket 7 TX] PC Partner TXA807DS", "807ds", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_807ds_init, NULL },
{ "[Socket 7 TX] SuperMicro P5MMS98", "p5mms98", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_p5mms98_init, NULL },
{ "[Socket 7 VPX] Zida Tomato TX100", "tx100", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_tx100_init, NULL },
{ "[Socket 7 VP3] QDI Advance II", "advanceii", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_advanceii_init, NULL },
//Super Socket 7 machines

2
src/win/Makefile.mingw
View File

@@ -519,7 +519,7 @@ CPUOBJ := cpu.o cpu_table.o \
CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \
intel_4x0.o neat.o opti495.o scamp.o scat.o \
sis_85c471.o sis_85c496.o \
via_apollo.o wd76c10.o
via_apollo.o via_apx.o wd76c10.o
MCHOBJ := machine.o machine_table.o \
m_xt.o m_xt_compaq.o \

2
src/win/Makefile_ndr.mingw
View File

@@ -523,7 +523,7 @@ CPUOBJ := cpu.o cpu_table.o \
CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \
intel_4x0.o neat.o opti495.o scamp.o scat.o \
sis_85c471.o sis_85c496.o \
via_apollo.o wd76c10.o
via_apollo.o via_vpx.o wd76c10.o
MCHOBJ := machine.o machine_table.o \
m_xt.o m_xt_compaq.o \