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Make MSR 17h read-only and return a suitable Platform ID

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Fixes some programs misidentifying Celeron Mendocinos as Slot 1 instead of Socket 370
This commit is contained in:
Alexander Babikov
2021-10-16 23:50:49 +05:00
parent 38ca621ac5
commit 1a04b93165
2 changed files with 4 additions and 9 deletions
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12
src/cpu/cpu.c
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@@ -2310,8 +2310,10 @@ amd_k_invalid_rdmsr:
if (cpu_s->cpu_type != CPU_PENTIUM2D) if (cpu_s->cpu_type != CPU_PENTIUM2D)
goto i686_invalid_rdmsr; goto i686_invalid_rdmsr;
EAX = msr.ecx17 & 0xffffffff; if (cpu_f->package == CPU_PKG_SLOT2)
EDX = msr.ecx17 >> 32; EDX |= 0x80000;
else if (cpu_f->package == CPU_PKG_SOCKET370)
EDX |= 0x100000;
break; break;
case 0x1B: case 0x1B:
EAX = msr.apic_base & 0xffffffff; EAX = msr.apic_base & 0xffffffff;
@@ -2725,12 +2727,6 @@ amd_k_invalid_wrmsr:
case 0x10: case 0x10:
tsc = EAX | ((uint64_t)EDX << 32); tsc = EAX | ((uint64_t)EDX << 32);
break; break;
case 0x17:
if (cpu_s->cpu_type != CPU_PENTIUM2D)
goto i686_invalid_wrmsr;
msr.ecx17 = EAX | ((uint64_t)EDX << 32);
break;
case 0x1b: case 0x1b:
cpu_log("APIC_BASE write: %08X%08X\n", EDX, EAX); cpu_log("APIC_BASE write: %08X%08X\n", EDX, EAX);
// msr.apic_base = EAX | ((uint64_t)EDX << 32); // msr.apic_base = EAX | ((uint64_t)EDX << 32);

1
src/cpu/cpu.h
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@@ -236,7 +236,6 @@ typedef struct {
uint32_t cesr; /* 0x00000011 */ uint32_t cesr; /* 0x00000011 */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */ /* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t ecx17; /* 0x00000017 - Only on Pentium II Deschutes */
uint64_t apic_base; /* 0x0000001b - Should the Pentium not also have this? */ uint64_t apic_base; /* 0x0000001b - Should the Pentium not also have this? */
uint64_t ecx79; /* 0x00000079 */ uint64_t ecx79; /* 0x00000079 */